2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Gerd Hoffmann <kraxel@redhat.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "hw/pci/pci.h"
23 #include "hw/pci/msi.h"
24 #include "qemu/timer.h"
25 #include "hw/audio/audio.h"
26 #include "intel-hda.h"
27 #include "intel-hda-defs.h"
28 #include "sysemu/dma.h"
30 /* --------------------------------------------------------------------- */
33 static Property hda_props[] = {
34 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
35 DEFINE_PROP_END_OF_LIST()
38 static const TypeInfo hda_codec_bus_info = {
41 .instance_size = sizeof(HDACodecBus),
44 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size,
45 hda_codec_response_func response,
46 hda_codec_xfer_func xfer)
48 qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
49 bus->response = response;
53 static int hda_codec_dev_init(DeviceState *qdev)
55 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus);
56 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
57 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
60 dev->cad = bus->next_cad;
65 bus->next_cad = dev->cad + 1;
66 return cdc->init(dev);
69 static int hda_codec_dev_exit(DeviceState *qdev)
71 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
72 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
80 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
85 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
86 DeviceState *qdev = kid->child;
87 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
88 if (cdev->cad == cad) {
95 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
97 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
98 bus->response(dev, solicited, response);
101 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
102 uint8_t *buf, uint32_t len)
104 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
105 return bus->xfer(dev, stnr, output, buf, len);
108 /* --------------------------------------------------------------------- */
109 /* intel hda emulation */
111 typedef struct IntelHDAStream IntelHDAStream;
112 typedef struct IntelHDAState IntelHDAState;
113 typedef struct IntelHDAReg IntelHDAReg;
121 struct IntelHDAStream {
134 uint32_t bsize, be, bp;
137 struct IntelHDAState {
174 IntelHDAStream st[8];
179 int64_t wall_base_ns;
182 const IntelHDAReg *last_reg;
186 uint32_t repeat_count;
194 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic"
196 #define INTEL_HDA(obj) \
197 OBJECT_CHECK(IntelHDAState, (obj), TYPE_INTEL_HDA_GENERIC)
200 const char *name; /* register name */
201 uint32_t size; /* size in bytes */
202 uint32_t reset; /* reset value */
203 uint32_t wmask; /* write mask */
204 uint32_t wclear; /* write 1 to clear bits */
205 uint32_t offset; /* location in IntelHDAState */
206 uint32_t shift; /* byte access entries for dwords */
208 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
209 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
212 static void intel_hda_reset(DeviceState *dev);
214 /* --------------------------------------------------------------------- */
216 static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase)
220 addr = ((uint64_t)ubase << 32) | lbase;
224 static void intel_hda_update_int_sts(IntelHDAState *d)
229 /* update controller status */
230 if (d->rirb_sts & ICH6_RBSTS_IRQ) {
233 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
236 if (d->state_sts & d->wake_en) {
240 /* update stream status */
241 for (i = 0; i < 8; i++) {
242 /* buffer completion interrupt */
243 if (d->st[i].ctl & (1 << 26)) {
248 /* update global status */
249 if (sts & d->int_ctl) {
256 static void intel_hda_update_irq(IntelHDAState *d)
258 int msi = d->msi && msi_enabled(&d->pci);
261 intel_hda_update_int_sts(d);
262 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) {
267 dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__,
268 level, msi ? "msi" : "intx");
271 msi_notify(&d->pci, 0);
274 pci_set_irq(&d->pci, level);
278 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
280 uint32_t cad, nid, data;
281 HDACodecDevice *codec;
282 HDACodecDeviceClass *cdc;
284 cad = (verb >> 28) & 0x0f;
285 if (verb & (1 << 27)) {
286 /* indirect node addressing, not specified in HDA 1.0 */
287 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__);
290 nid = (verb >> 20) & 0x7f;
291 data = verb & 0xfffff;
293 codec = hda_codec_find(&d->codecs, cad);
295 dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__);
298 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
299 cdc->command(codec, nid, data);
303 static void intel_hda_corb_run(IntelHDAState *d)
308 if (d->ics & ICH6_IRS_BUSY) {
309 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw);
310 intel_hda_send_command(d, d->icw);
315 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
316 dprint(d, 2, "%s: !run\n", __FUNCTION__);
319 if ((d->corb_rp & 0xff) == d->corb_wp) {
320 dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__);
323 if (d->rirb_count == d->rirb_cnt) {
324 dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__);
328 rp = (d->corb_rp + 1) & 0xff;
329 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
330 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp);
333 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb);
334 intel_hda_send_command(d, verb);
338 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
340 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
341 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
345 if (d->ics & ICH6_IRS_BUSY) {
346 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
347 __FUNCTION__, response, dev->cad);
349 d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
350 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
354 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
355 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__);
359 ex = (solicited ? 0 : (1 << 4)) | dev->cad;
360 wp = (d->rirb_wp + 1) & 0xff;
361 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
362 stl_le_pci_dma(&d->pci, addr + 8*wp, response);
363 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex);
366 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
367 __FUNCTION__, wp, response, ex);
370 if (d->rirb_count == d->rirb_cnt) {
371 dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count);
372 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
373 d->rirb_sts |= ICH6_RBSTS_IRQ;
374 intel_hda_update_irq(d);
376 } else if ((d->corb_rp & 0xff) == d->corb_wp) {
377 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__,
378 d->rirb_count, d->rirb_cnt);
379 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
380 d->rirb_sts |= ICH6_RBSTS_IRQ;
381 intel_hda_update_irq(d);
386 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
387 uint8_t *buf, uint32_t len)
389 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
390 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
392 uint32_t s, copy, left;
396 st = output ? d->st + 4 : d->st;
397 for (s = 0; s < 4; s++) {
398 if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
406 if (st->bpl == NULL) {
409 if (st->ctl & (1 << 26)) {
411 * Wait with the next DMA xfer until the guest
412 * has acked the buffer completion interrupt
420 if (copy > st->bsize - st->lpib)
421 copy = st->bsize - st->lpib;
422 if (copy > st->bpl[st->be].len - st->bp)
423 copy = st->bpl[st->be].len - st->bp;
425 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
426 st->be, st->bp, st->bpl[st->be].len, copy);
428 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output);
434 if (st->bpl[st->be].len == st->bp) {
435 /* bpl entry filled */
436 if (st->bpl[st->be].flags & 0x01) {
441 if (st->be == st->bentries) {
442 /* bpl wrap around */
448 if (d->dp_lbase & 0x01) {
450 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
451 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib);
453 dprint(d, 3, "dma: --\n");
456 st->ctl |= (1 << 26); /* buffer completion interrupt */
457 intel_hda_update_irq(d);
462 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
468 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
469 st->bentries = st->lvi +1;
471 st->bpl = g_malloc(sizeof(bpl) * st->bentries);
472 for (i = 0; i < st->bentries; i++, addr += 16) {
473 pci_dma_read(&d->pci, addr, buf, 16);
474 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf);
475 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
476 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
477 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
478 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
487 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
490 HDACodecDevice *cdev;
492 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
493 DeviceState *qdev = kid->child;
494 HDACodecDeviceClass *cdc;
496 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
497 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev);
499 cdc->stream(cdev, stream, running, output);
504 /* --------------------------------------------------------------------- */
506 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
508 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
509 intel_hda_reset(DEVICE(d));
513 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
515 intel_hda_update_irq(d);
518 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
520 intel_hda_update_irq(d);
523 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
525 intel_hda_update_irq(d);
528 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
532 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns;
533 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
536 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
538 intel_hda_corb_run(d);
541 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
543 intel_hda_corb_run(d);
546 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
548 if (d->rirb_wp & ICH6_RIRBWP_RST) {
553 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
555 intel_hda_update_irq(d);
557 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
558 /* cleared ICH6_RBSTS_IRQ */
560 intel_hda_corb_run(d);
564 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
566 if (d->ics & ICH6_IRS_BUSY) {
567 intel_hda_corb_run(d);
571 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
573 bool output = reg->stream >= 4;
574 IntelHDAStream *st = d->st + reg->stream;
576 if (st->ctl & 0x01) {
578 dprint(d, 1, "st #%d: reset\n", reg->stream);
579 st->ctl = SD_STS_FIFO_READY << 24;
581 if ((st->ctl & 0x02) != (old & 0x02)) {
582 uint32_t stnr = (st->ctl >> 20) & 0x0f;
583 /* run bit flipped */
584 if (st->ctl & 0x02) {
586 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
587 reg->stream, stnr, st->cbl);
588 intel_hda_parse_bdl(d, st);
589 intel_hda_notify_codecs(d, stnr, true, output);
592 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
593 intel_hda_notify_codecs(d, stnr, false, output);
596 intel_hda_update_irq(d);
599 /* --------------------------------------------------------------------- */
601 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
603 static const struct IntelHDAReg regtab[] = {
605 [ ICH6_REG_GCAP ] = {
610 [ ICH6_REG_VMIN ] = {
614 [ ICH6_REG_VMAJ ] = {
619 [ ICH6_REG_OUTPAY ] = {
624 [ ICH6_REG_INPAY ] = {
629 [ ICH6_REG_GCTL ] = {
633 .offset = offsetof(IntelHDAState, g_ctl),
634 .whandler = intel_hda_set_g_ctl,
636 [ ICH6_REG_WAKEEN ] = {
640 .offset = offsetof(IntelHDAState, wake_en),
641 .whandler = intel_hda_set_wake_en,
643 [ ICH6_REG_STATESTS ] = {
648 .offset = offsetof(IntelHDAState, state_sts),
649 .whandler = intel_hda_set_state_sts,
653 [ ICH6_REG_INTCTL ] = {
657 .offset = offsetof(IntelHDAState, int_ctl),
658 .whandler = intel_hda_set_int_ctl,
660 [ ICH6_REG_INTSTS ] = {
664 .wclear = 0xc00000ff,
665 .offset = offsetof(IntelHDAState, int_sts),
669 [ ICH6_REG_WALLCLK ] = {
672 .offset = offsetof(IntelHDAState, wall_clk),
673 .rhandler = intel_hda_get_wall_clk,
675 [ ICH6_REG_WALLCLK + 0x2000 ] = {
676 .name = "WALLCLK(alias)",
678 .offset = offsetof(IntelHDAState, wall_clk),
679 .rhandler = intel_hda_get_wall_clk,
683 [ ICH6_REG_CORBLBASE ] = {
687 .offset = offsetof(IntelHDAState, corb_lbase),
689 [ ICH6_REG_CORBUBASE ] = {
693 .offset = offsetof(IntelHDAState, corb_ubase),
695 [ ICH6_REG_CORBWP ] = {
699 .offset = offsetof(IntelHDAState, corb_wp),
700 .whandler = intel_hda_set_corb_wp,
702 [ ICH6_REG_CORBRP ] = {
706 .offset = offsetof(IntelHDAState, corb_rp),
708 [ ICH6_REG_CORBCTL ] = {
712 .offset = offsetof(IntelHDAState, corb_ctl),
713 .whandler = intel_hda_set_corb_ctl,
715 [ ICH6_REG_CORBSTS ] = {
720 .offset = offsetof(IntelHDAState, corb_sts),
722 [ ICH6_REG_CORBSIZE ] = {
726 .offset = offsetof(IntelHDAState, corb_size),
728 [ ICH6_REG_RIRBLBASE ] = {
732 .offset = offsetof(IntelHDAState, rirb_lbase),
734 [ ICH6_REG_RIRBUBASE ] = {
738 .offset = offsetof(IntelHDAState, rirb_ubase),
740 [ ICH6_REG_RIRBWP ] = {
744 .offset = offsetof(IntelHDAState, rirb_wp),
745 .whandler = intel_hda_set_rirb_wp,
747 [ ICH6_REG_RINTCNT ] = {
751 .offset = offsetof(IntelHDAState, rirb_cnt),
753 [ ICH6_REG_RIRBCTL ] = {
757 .offset = offsetof(IntelHDAState, rirb_ctl),
759 [ ICH6_REG_RIRBSTS ] = {
764 .offset = offsetof(IntelHDAState, rirb_sts),
765 .whandler = intel_hda_set_rirb_sts,
767 [ ICH6_REG_RIRBSIZE ] = {
771 .offset = offsetof(IntelHDAState, rirb_size),
774 [ ICH6_REG_DPLBASE ] = {
778 .offset = offsetof(IntelHDAState, dp_lbase),
780 [ ICH6_REG_DPUBASE ] = {
784 .offset = offsetof(IntelHDAState, dp_ubase),
791 .offset = offsetof(IntelHDAState, icw),
796 .offset = offsetof(IntelHDAState, irr),
803 .offset = offsetof(IntelHDAState, ics),
804 .whandler = intel_hda_set_ics,
807 #define HDA_STREAM(_t, _i) \
808 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
810 .name = _t stringify(_i) " CTL", \
812 .wmask = 0x1cff001f, \
813 .offset = offsetof(IntelHDAState, st[_i].ctl), \
814 .whandler = intel_hda_set_st_ctl, \
816 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
818 .name = _t stringify(_i) " CTL(stnr)", \
821 .wmask = 0x00ff0000, \
822 .offset = offsetof(IntelHDAState, st[_i].ctl), \
823 .whandler = intel_hda_set_st_ctl, \
825 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
827 .name = _t stringify(_i) " CTL(sts)", \
830 .wmask = 0x1c000000, \
831 .wclear = 0x1c000000, \
832 .offset = offsetof(IntelHDAState, st[_i].ctl), \
833 .whandler = intel_hda_set_st_ctl, \
834 .reset = SD_STS_FIFO_READY << 24 \
836 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
838 .name = _t stringify(_i) " LPIB", \
840 .offset = offsetof(IntelHDAState, st[_i].lpib), \
842 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
844 .name = _t stringify(_i) " LPIB(alias)", \
846 .offset = offsetof(IntelHDAState, st[_i].lpib), \
848 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
850 .name = _t stringify(_i) " CBL", \
852 .wmask = 0xffffffff, \
853 .offset = offsetof(IntelHDAState, st[_i].cbl), \
855 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
857 .name = _t stringify(_i) " LVI", \
860 .offset = offsetof(IntelHDAState, st[_i].lvi), \
862 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
864 .name = _t stringify(_i) " FIFOS", \
866 .reset = HDA_BUFFER_SIZE, \
868 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
870 .name = _t stringify(_i) " FMT", \
873 .offset = offsetof(IntelHDAState, st[_i].fmt), \
875 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
877 .name = _t stringify(_i) " BDLPL", \
879 .wmask = 0xffffff80, \
880 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
882 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
884 .name = _t stringify(_i) " BDLPU", \
886 .wmask = 0xffffffff, \
887 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
902 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr)
904 const IntelHDAReg *reg;
906 if (addr >= ARRAY_SIZE(regtab)) {
910 if (reg->name == NULL) {
916 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
920 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
922 uint8_t *addr = (void*)d;
925 return (uint32_t*)addr;
928 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
939 time_t now = time(NULL);
940 if (d->last_write && d->last_reg == reg && d->last_val == val) {
942 if (d->last_sec != now) {
943 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
948 if (d->repeat_count) {
949 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
951 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
959 assert(reg->offset != 0);
961 addr = intel_hda_reg_addr(d, reg);
966 wmask <<= reg->shift;
970 *addr |= wmask & val;
971 *addr &= ~(val & reg->wclear);
974 reg->whandler(d, reg, old);
978 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
988 reg->rhandler(d, reg);
991 if (reg->offset == 0) {
992 /* constant read-only register */
995 addr = intel_hda_reg_addr(d, reg);
1003 time_t now = time(NULL);
1004 if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
1006 if (d->last_sec != now) {
1007 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1009 d->repeat_count = 0;
1012 if (d->repeat_count) {
1013 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1015 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1020 d->repeat_count = 0;
1026 static void intel_hda_regs_reset(IntelHDAState *d)
1031 for (i = 0; i < ARRAY_SIZE(regtab); i++) {
1032 if (regtab[i].name == NULL) {
1035 if (regtab[i].offset == 0) {
1038 addr = intel_hda_reg_addr(d, regtab + i);
1039 *addr = regtab[i].reset;
1043 /* --------------------------------------------------------------------- */
1045 static void intel_hda_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
1047 IntelHDAState *d = opaque;
1048 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1050 intel_hda_reg_write(d, reg, val, 0xff);
1053 static void intel_hda_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
1055 IntelHDAState *d = opaque;
1056 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1058 intel_hda_reg_write(d, reg, val, 0xffff);
1061 static void intel_hda_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
1063 IntelHDAState *d = opaque;
1064 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1066 intel_hda_reg_write(d, reg, val, 0xffffffff);
1069 static uint32_t intel_hda_mmio_readb(void *opaque, hwaddr addr)
1071 IntelHDAState *d = opaque;
1072 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1074 return intel_hda_reg_read(d, reg, 0xff);
1077 static uint32_t intel_hda_mmio_readw(void *opaque, hwaddr addr)
1079 IntelHDAState *d = opaque;
1080 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1082 return intel_hda_reg_read(d, reg, 0xffff);
1085 static uint32_t intel_hda_mmio_readl(void *opaque, hwaddr addr)
1087 IntelHDAState *d = opaque;
1088 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1090 return intel_hda_reg_read(d, reg, 0xffffffff);
1093 static const MemoryRegionOps intel_hda_mmio_ops = {
1096 intel_hda_mmio_readb,
1097 intel_hda_mmio_readw,
1098 intel_hda_mmio_readl,
1101 intel_hda_mmio_writeb,
1102 intel_hda_mmio_writew,
1103 intel_hda_mmio_writel,
1106 .endianness = DEVICE_NATIVE_ENDIAN,
1109 /* --------------------------------------------------------------------- */
1111 static void intel_hda_reset(DeviceState *dev)
1114 IntelHDAState *d = INTEL_HDA(dev);
1115 HDACodecDevice *cdev;
1117 intel_hda_regs_reset(d);
1118 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1121 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
1122 DeviceState *qdev = kid->child;
1123 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
1124 device_reset(DEVICE(cdev));
1125 d->state_sts |= (1 << cdev->cad);
1127 intel_hda_update_irq(d);
1130 static void intel_hda_realize(PCIDevice *pci, Error **errp)
1132 IntelHDAState *d = INTEL_HDA(pci);
1133 uint8_t *conf = d->pci.config;
1135 d->name = object_get_typename(OBJECT(d));
1137 pci_config_set_interrupt_pin(conf, 1);
1139 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1142 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d,
1143 "intel-hda", 0x4000);
1144 pci_register_bar(&d->pci, 0, 0, &d->mmio);
1146 msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60, 1, true, false);
1149 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs),
1150 intel_hda_response, intel_hda_xfer);
1153 static void intel_hda_exit(PCIDevice *pci)
1155 IntelHDAState *d = INTEL_HDA(pci);
1157 msi_uninit(&d->pci);
1160 static int intel_hda_post_load(void *opaque, int version)
1162 IntelHDAState* d = opaque;
1165 dprint(d, 1, "%s\n", __FUNCTION__);
1166 for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1167 if (d->st[i].ctl & 0x02) {
1168 intel_hda_parse_bdl(d, &d->st[i]);
1171 intel_hda_update_irq(d);
1175 static const VMStateDescription vmstate_intel_hda_stream = {
1176 .name = "intel-hda-stream",
1178 .fields = (VMStateField[]) {
1179 VMSTATE_UINT32(ctl, IntelHDAStream),
1180 VMSTATE_UINT32(lpib, IntelHDAStream),
1181 VMSTATE_UINT32(cbl, IntelHDAStream),
1182 VMSTATE_UINT32(lvi, IntelHDAStream),
1183 VMSTATE_UINT32(fmt, IntelHDAStream),
1184 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1185 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1186 VMSTATE_END_OF_LIST()
1190 static const VMStateDescription vmstate_intel_hda = {
1191 .name = "intel-hda",
1193 .post_load = intel_hda_post_load,
1194 .fields = (VMStateField[]) {
1195 VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1198 VMSTATE_UINT32(g_ctl, IntelHDAState),
1199 VMSTATE_UINT32(wake_en, IntelHDAState),
1200 VMSTATE_UINT32(state_sts, IntelHDAState),
1201 VMSTATE_UINT32(int_ctl, IntelHDAState),
1202 VMSTATE_UINT32(int_sts, IntelHDAState),
1203 VMSTATE_UINT32(wall_clk, IntelHDAState),
1204 VMSTATE_UINT32(corb_lbase, IntelHDAState),
1205 VMSTATE_UINT32(corb_ubase, IntelHDAState),
1206 VMSTATE_UINT32(corb_rp, IntelHDAState),
1207 VMSTATE_UINT32(corb_wp, IntelHDAState),
1208 VMSTATE_UINT32(corb_ctl, IntelHDAState),
1209 VMSTATE_UINT32(corb_sts, IntelHDAState),
1210 VMSTATE_UINT32(corb_size, IntelHDAState),
1211 VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1212 VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1213 VMSTATE_UINT32(rirb_wp, IntelHDAState),
1214 VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1215 VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1216 VMSTATE_UINT32(rirb_sts, IntelHDAState),
1217 VMSTATE_UINT32(rirb_size, IntelHDAState),
1218 VMSTATE_UINT32(dp_lbase, IntelHDAState),
1219 VMSTATE_UINT32(dp_ubase, IntelHDAState),
1220 VMSTATE_UINT32(icw, IntelHDAState),
1221 VMSTATE_UINT32(irr, IntelHDAState),
1222 VMSTATE_UINT32(ics, IntelHDAState),
1223 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1224 vmstate_intel_hda_stream,
1227 /* additional state info */
1228 VMSTATE_UINT32(rirb_count, IntelHDAState),
1229 VMSTATE_INT64(wall_base_ns, IntelHDAState),
1231 VMSTATE_END_OF_LIST()
1235 static Property intel_hda_properties[] = {
1236 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1237 DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1),
1238 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false),
1239 DEFINE_PROP_END_OF_LIST(),
1242 static void intel_hda_class_init(ObjectClass *klass, void *data)
1244 DeviceClass *dc = DEVICE_CLASS(klass);
1245 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1247 k->realize = intel_hda_realize;
1248 k->exit = intel_hda_exit;
1249 k->vendor_id = PCI_VENDOR_ID_INTEL;
1250 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
1251 dc->reset = intel_hda_reset;
1252 dc->vmsd = &vmstate_intel_hda;
1253 dc->props = intel_hda_properties;
1256 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data)
1258 DeviceClass *dc = DEVICE_CLASS(klass);
1259 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1261 k->device_id = 0x2668;
1263 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1264 dc->desc = "Intel HD Audio Controller (ich6)";
1267 static void intel_hda_class_init_ich9(ObjectClass *klass, void *data)
1269 DeviceClass *dc = DEVICE_CLASS(klass);
1270 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1272 k->device_id = 0x293e;
1274 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1275 dc->desc = "Intel HD Audio Controller (ich9)";
1278 static const TypeInfo intel_hda_info = {
1279 .name = TYPE_INTEL_HDA_GENERIC,
1280 .parent = TYPE_PCI_DEVICE,
1281 .instance_size = sizeof(IntelHDAState),
1282 .class_init = intel_hda_class_init,
1286 static const TypeInfo intel_hda_info_ich6 = {
1287 .name = "intel-hda",
1288 .parent = TYPE_INTEL_HDA_GENERIC,
1289 .class_init = intel_hda_class_init_ich6,
1292 static const TypeInfo intel_hda_info_ich9 = {
1293 .name = "ich9-intel-hda",
1294 .parent = TYPE_INTEL_HDA_GENERIC,
1295 .class_init = intel_hda_class_init_ich9,
1298 static void hda_codec_device_class_init(ObjectClass *klass, void *data)
1300 DeviceClass *k = DEVICE_CLASS(klass);
1301 k->init = hda_codec_dev_init;
1302 k->exit = hda_codec_dev_exit;
1303 set_bit(DEVICE_CATEGORY_SOUND, k->categories);
1304 k->bus_type = TYPE_HDA_BUS;
1305 k->props = hda_props;
1308 static const TypeInfo hda_codec_device_type_info = {
1309 .name = TYPE_HDA_CODEC_DEVICE,
1310 .parent = TYPE_DEVICE,
1311 .instance_size = sizeof(HDACodecDevice),
1313 .class_size = sizeof(HDACodecDeviceClass),
1314 .class_init = hda_codec_device_class_init,
1318 * create intel hda controller with codec attached to it,
1319 * so '-soundhw hda' works.
1321 static int intel_hda_and_codec_init(PCIBus *bus)
1323 DeviceState *controller;
1327 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda"));
1328 hdabus = QLIST_FIRST(&controller->child_bus);
1329 codec = qdev_create(hdabus, "hda-duplex");
1330 qdev_init_nofail(codec);
1334 static void intel_hda_register_types(void)
1336 type_register_static(&hda_codec_bus_info);
1337 type_register_static(&intel_hda_info);
1338 type_register_static(&intel_hda_info_ich6);
1339 type_register_static(&intel_hda_info_ich9);
1340 type_register_static(&hda_codec_device_type_info);
1341 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init);
1344 type_init(intel_hda_register_types)