2 * Arm PrimeCell PL110 Color LCD Controller
4 * Copyright (c) 2005-2009 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GNU LGPL
10 #include "qemu/osdep.h"
11 #include "hw/sysbus.h"
12 #include "ui/console.h"
13 #include "framebuffer.h"
14 #include "ui/pixel_ops.h"
16 #define PL110_CR_EN 0x001
17 #define PL110_CR_BGR 0x100
18 #define PL110_CR_BEBO 0x200
19 #define PL110_CR_BEPO 0x400
20 #define PL110_CR_PWR 0x800
30 BPP_16_565, /* PL111 only */
31 BPP_12 /* PL111 only */
35 /* The Versatile/PB uses a slightly modified PL110 controller. */
43 #define TYPE_PL110 "pl110"
44 #define PL110(obj) OBJECT_CHECK(PL110State, (obj), TYPE_PL110)
46 typedef struct PL110State {
47 SysBusDevice parent_obj;
50 MemoryRegionSection fbsection;
62 enum pl110_bppmode bpp;
65 uint32_t palette[256];
66 uint32_t raw_palette[128];
70 static int vmstate_pl110_post_load(void *opaque, int version_id);
72 static const VMStateDescription vmstate_pl110 = {
75 .minimum_version_id = 1,
76 .post_load = vmstate_pl110_post_load,
77 .fields = (VMStateField[]) {
78 VMSTATE_INT32(version, PL110State),
79 VMSTATE_UINT32_ARRAY(timing, PL110State, 4),
80 VMSTATE_UINT32(cr, PL110State),
81 VMSTATE_UINT32(upbase, PL110State),
82 VMSTATE_UINT32(lpbase, PL110State),
83 VMSTATE_UINT32(int_status, PL110State),
84 VMSTATE_UINT32(int_mask, PL110State),
85 VMSTATE_INT32(cols, PL110State),
86 VMSTATE_INT32(rows, PL110State),
87 VMSTATE_UINT32(bpp, PL110State),
88 VMSTATE_INT32(invalidate, PL110State),
89 VMSTATE_UINT32_ARRAY(palette, PL110State, 256),
90 VMSTATE_UINT32_ARRAY(raw_palette, PL110State, 128),
91 VMSTATE_UINT32_V(mux_ctrl, PL110State, 2),
96 static const unsigned char pl110_id[] =
97 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
99 static const unsigned char pl111_id[] = {
100 0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
104 /* Indexed by pl110_version */
105 static const unsigned char *idregs[] = {
107 /* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board
108 * has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware
109 * itself has the same ID values as a stock PL110, and guests (in
110 * particular Linux) rely on this. We emulate what the hardware does,
111 * rather than what the docs claim it ought to do.
118 #include "pl110_template.h"
120 #include "pl110_template.h"
122 #include "pl110_template.h"
124 #include "pl110_template.h"
126 #include "pl110_template.h"
128 static int pl110_enabled(PL110State *s)
130 return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
133 static void pl110_update_display(void *opaque)
135 PL110State *s = (PL110State *)opaque;
137 DisplaySurface *surface = qemu_console_surface(s->con);
146 if (!pl110_enabled(s)) {
150 sbd = SYS_BUS_DEVICE(s);
152 switch (surface_bits_per_pixel(surface)) {
156 fntable = pl110_draw_fn_8;
160 fntable = pl110_draw_fn_15;
164 fntable = pl110_draw_fn_16;
168 fntable = pl110_draw_fn_24;
172 fntable = pl110_draw_fn_32;
176 fprintf(stderr, "pl110: Bad color depth\n");
179 if (s->cr & PL110_CR_BGR)
184 if ((s->version != PL111) && (s->bpp == BPP_16)) {
185 /* The PL110's native 16 bit mode is 5551; however
186 * most boards with a PL110 implement an external
187 * mux which allows bits to be reshuffled to give
188 * 565 format. The mux is typically controlled by
189 * an external system register.
190 * This is controlled by a GPIO input pin
191 * so boards can wire it up to their register.
193 * The PL111 straightforwardly implements both
194 * 5551 and 565 under control of the bpp field
195 * in the LCDControl register.
197 switch (s->mux_ctrl) {
198 case 3: /* 565 BGR */
199 bpp_offset = (BPP_16_565 - BPP_16);
203 case 0: /* 888; also if we have loaded vmstate from an old version */
204 case 2: /* 565 RGB */
206 /* treat as 565 but honour BGR bit */
207 bpp_offset += (BPP_16_565 - BPP_16);
212 if (s->cr & PL110_CR_BEBO)
213 fn = fntable[s->bpp + 8 + bpp_offset];
214 else if (s->cr & PL110_CR_BEPO)
215 fn = fntable[s->bpp + 16 + bpp_offset];
217 fn = fntable[s->bpp + bpp_offset];
241 dest_width *= s->cols;
244 framebuffer_update_memory_section(&s->fbsection,
245 sysbus_address_space(sbd),
250 framebuffer_update_display(surface, &s->fbsection,
252 src_width, dest_width, 0,
258 dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1);
263 static void pl110_invalidate_display(void * opaque)
265 PL110State *s = (PL110State *)opaque;
267 if (pl110_enabled(s)) {
268 qemu_console_resize(s->con, s->cols, s->rows);
272 static void pl110_update_palette(PL110State *s, int n)
274 DisplaySurface *surface = qemu_console_surface(s->con);
277 unsigned int r, g, b;
279 raw = s->raw_palette[n];
281 for (i = 0; i < 2; i++) {
282 r = (raw & 0x1f) << 3;
284 g = (raw & 0x1f) << 3;
286 b = (raw & 0x1f) << 3;
287 /* The I bit is ignored. */
289 switch (surface_bits_per_pixel(surface)) {
291 s->palette[n] = rgb_to_pixel8(r, g, b);
294 s->palette[n] = rgb_to_pixel15(r, g, b);
297 s->palette[n] = rgb_to_pixel16(r, g, b);
301 s->palette[n] = rgb_to_pixel32(r, g, b);
308 static void pl110_resize(PL110State *s, int width, int height)
310 if (width != s->cols || height != s->rows) {
311 if (pl110_enabled(s)) {
312 qemu_console_resize(s->con, width, height);
319 /* Update interrupts. */
320 static void pl110_update(PL110State *s)
322 /* TODO: Implement interrupts. */
325 static uint64_t pl110_read(void *opaque, hwaddr offset,
328 PL110State *s = (PL110State *)opaque;
330 if (offset >= 0xfe0 && offset < 0x1000) {
331 return idregs[s->version][(offset - 0xfe0) >> 2];
333 if (offset >= 0x200 && offset < 0x400) {
334 return s->raw_palette[(offset - 0x200) >> 2];
336 switch (offset >> 2) {
337 case 0: /* LCDTiming0 */
339 case 1: /* LCDTiming1 */
341 case 2: /* LCDTiming2 */
343 case 3: /* LCDTiming3 */
345 case 4: /* LCDUPBASE */
347 case 5: /* LCDLPBASE */
349 case 6: /* LCDIMSC */
350 if (s->version != PL110) {
354 case 7: /* LCDControl */
355 if (s->version != PL110) {
360 return s->int_status;
362 return s->int_status & s->int_mask;
363 case 11: /* LCDUPCURR */
364 /* TODO: Implement vertical refresh. */
366 case 12: /* LCDLPCURR */
369 qemu_log_mask(LOG_GUEST_ERROR,
370 "pl110_read: Bad offset %x\n", (int)offset);
375 static void pl110_write(void *opaque, hwaddr offset,
376 uint64_t val, unsigned size)
378 PL110State *s = (PL110State *)opaque;
381 /* For simplicity invalidate the display whenever a control register
384 if (offset >= 0x200 && offset < 0x400) {
386 n = (offset - 0x200) >> 2;
387 s->raw_palette[(offset - 0x200) >> 2] = val;
388 pl110_update_palette(s, n);
391 switch (offset >> 2) {
392 case 0: /* LCDTiming0 */
394 n = ((val & 0xfc) + 4) * 4;
395 pl110_resize(s, n, s->rows);
397 case 1: /* LCDTiming1 */
399 n = (val & 0x3ff) + 1;
400 pl110_resize(s, s->cols, n);
402 case 2: /* LCDTiming2 */
405 case 3: /* LCDTiming3 */
408 case 4: /* LCDUPBASE */
411 case 5: /* LCDLPBASE */
414 case 6: /* LCDIMSC */
415 if (s->version != PL110) {
422 case 7: /* LCDControl */
423 if (s->version != PL110) {
428 s->bpp = (val >> 1) & 7;
429 if (pl110_enabled(s)) {
430 qemu_console_resize(s->con, s->cols, s->rows);
433 case 10: /* LCDICR */
434 s->int_status &= ~val;
438 qemu_log_mask(LOG_GUEST_ERROR,
439 "pl110_write: Bad offset %x\n", (int)offset);
443 static const MemoryRegionOps pl110_ops = {
445 .write = pl110_write,
446 .endianness = DEVICE_NATIVE_ENDIAN,
449 static void pl110_mux_ctrl_set(void *opaque, int line, int level)
451 PL110State *s = (PL110State *)opaque;
455 static int vmstate_pl110_post_load(void *opaque, int version_id)
457 PL110State *s = opaque;
458 /* Make sure we redraw, and at the right size */
459 pl110_invalidate_display(s);
463 static const GraphicHwOps pl110_gfx_ops = {
464 .invalidate = pl110_invalidate_display,
465 .gfx_update = pl110_update_display,
468 static int pl110_initfn(SysBusDevice *sbd)
470 DeviceState *dev = DEVICE(sbd);
471 PL110State *s = PL110(dev);
473 memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000);
474 sysbus_init_mmio(sbd, &s->iomem);
475 sysbus_init_irq(sbd, &s->irq);
476 qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1);
477 s->con = graphic_console_init(dev, 0, &pl110_gfx_ops, s);
481 static void pl110_init(Object *obj)
483 PL110State *s = PL110(obj);
488 static void pl110_versatile_init(Object *obj)
490 PL110State *s = PL110(obj);
492 s->version = PL110_VERSATILE;
495 static void pl111_init(Object *obj)
497 PL110State *s = PL110(obj);
502 static void pl110_class_init(ObjectClass *klass, void *data)
504 DeviceClass *dc = DEVICE_CLASS(klass);
505 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
507 k->init = pl110_initfn;
508 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
509 dc->vmsd = &vmstate_pl110;
512 static const TypeInfo pl110_info = {
514 .parent = TYPE_SYS_BUS_DEVICE,
515 .instance_size = sizeof(PL110State),
516 .instance_init = pl110_init,
517 .class_init = pl110_class_init,
520 static const TypeInfo pl110_versatile_info = {
521 .name = "pl110_versatile",
522 .parent = TYPE_PL110,
523 .instance_init = pl110_versatile_init,
526 static const TypeInfo pl111_info = {
528 .parent = TYPE_PL110,
529 .instance_init = pl111_init,
532 static void pl110_register_types(void)
534 type_register_static(&pl110_info);
535 type_register_static(&pl110_versatile_info);
536 type_register_static(&pl111_info);
539 type_init(pl110_register_types)