2 comedi/drivers/ni_pcimio.c
3 Hardware driver for NI PCI-MIO E series cards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
20 Description: National Instruments PCI-MIO-E series and M series (all boards)
21 Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
22 Herman Bruyninckx, Terry Barnaby
24 Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
25 PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
26 PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
27 PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
28 PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224,
29 PCI-6225, PXI-6225, PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PXIe-6251,
30 PCI-6254, PCI-6259, PCIe-6259,
31 PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
32 PCI-6711, PXI-6711, PCI-6713, PXI-6713,
33 PXI-6071E, PCI-6070E, PXI-6070E,
34 PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
36 Updated: Mon, 09 Jan 2012 14:52:48 +0000
38 These boards are almost identical to the AT-MIO E series, except that
39 they use the PCI bus instead of ISA (i.e., AT). See the notes for
40 the ni_atmio.o driver for additional information about these boards.
42 Autocalibration is supported on many of the devices, using the
43 comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
44 M-Series boards do analog input and analog output calibration entirely
45 in software. The software calibration corrects
46 the analog input for offset, gain and
47 nonlinearity. The analog outputs are corrected for offset and gain.
48 See the comedilib documentation on comedi_get_softcal_converter() for
51 By default, the driver uses DMA to transfer analog input data to
52 memory. When DMA is enabled, not all triggering features are
55 Digital I/O may not work on 673x.
57 Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
58 With this board all of the convertors perform one simultaineous sample during
59 a scan interval. The period for a scan is used for the convert time in a
60 Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
62 The RTSI trigger bus is supported on these cards on
63 subdevice 10. See the comedilib documentation for details.
65 Information (number of channels, bits, etc.) for some devices may be
66 incorrect. Please check this and submit a bug if there are problems
69 SCXI is probably broken for m-series boards.
72 - When DMA is enabled, COMEDI_EV_CONVERT does
77 The PCI-MIO E series driver was originally written by
78 Tomasz Motylewski <...>, and ported to comedi by ds.
82 341079b.pdf PCI E Series Register-Level Programmer Manual
83 340934b.pdf DAQ-STC reference manual
85 322080b.pdf 6711/6713/6715 User Manual
87 320945c.pdf PCI E Series User Manual
88 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
92 need to deal with external reference for DAC, and other DAC
93 properties in board properties
95 deal with at-mio-16de-10 revision D to N changes, etc.
97 need to add other CALDAC type
99 need to slow down DAC loading. I don't trust NI's claim that
100 two writes to the PCI bus slows IO enough. I would prefer to
101 use udelay(). Timing specs: (clock)
109 #include <linux/module.h>
110 #include <linux/delay.h>
112 #include "../comedi_pci.h"
114 #include <asm/byteorder.h>
121 /* These are not all the possible ao ranges for 628x boards.
122 They can do OFFSET +- REFERENCE where OFFSET can be
123 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
124 be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
125 63 different possibilities. An AO channel
126 can not act as it's own OFFSET or REFERENCE.
128 static const struct comedi_lrange range_ni_M_628x_ao = {
142 static const struct comedi_lrange range_ni_M_625x_ao = {
150 enum ni_pcimio_boardid {
151 BOARD_PCIMIO_16XE_50,
152 BOARD_PCIMIO_16XE_10,
210 static const struct ni_board_struct ni_boards[] = {
211 [BOARD_PCIMIO_16XE_50] = {
212 .name = "pci-mio-16xe-50",
214 .ai_maxdata = 0xffff,
215 .ai_fifo_depth = 2048,
217 .gainlkup = ai_gain_8,
220 .ao_maxdata = 0x0fff,
221 .ao_range_table = &range_bipolar10,
223 .caldac = { dac8800, dac8043 },
225 [BOARD_PCIMIO_16XE_10] = {
226 .name = "pci-mio-16xe-10", /* aka pci-6030E */
228 .ai_maxdata = 0xffff,
229 .ai_fifo_depth = 512,
231 .gainlkup = ai_gain_14,
234 .ao_maxdata = 0xffff,
235 .ao_fifo_depth = 2048,
236 .ao_range_table = &range_ni_E_ao_ext,
238 .caldac = { dac8800, dac8043, ad8522 },
243 .ai_maxdata = 0xffff,
244 .ai_fifo_depth = 512,
246 .gainlkup = ai_gain_4,
249 .ao_maxdata = 0xffff,
250 .ao_range_table = &range_bipolar10,
252 .caldac = { ad8804_debug },
257 .ai_maxdata = 0xffff,
258 .ai_fifo_depth = 512,
260 .gainlkup = ai_gain_14,
263 .ao_maxdata = 0xffff,
264 .ao_fifo_depth = 2048,
265 .ao_range_table = &range_ni_E_ao_ext,
267 .caldac = { dac8800, dac8043, ad8522 },
269 [BOARD_PCIMIO_16E_1] = {
270 .name = "pci-mio-16e-1", /* aka pci-6070e */
272 .ai_maxdata = 0x0fff,
273 .ai_fifo_depth = 512,
274 .gainlkup = ai_gain_16,
277 .ao_maxdata = 0x0fff,
278 .ao_fifo_depth = 2048,
279 .ao_range_table = &range_ni_E_ao_ext,
281 .caldac = { mb88341 },
283 [BOARD_PCIMIO_16E_4] = {
284 .name = "pci-mio-16e-4", /* aka pci-6040e */
286 .ai_maxdata = 0x0fff,
287 .ai_fifo_depth = 512,
288 .gainlkup = ai_gain_16,
290 * there have been reported problems with
291 * full speed on this board
295 .ao_maxdata = 0x0fff,
296 .ao_fifo_depth = 512,
297 .ao_range_table = &range_ni_E_ao_ext,
299 .caldac = { ad8804_debug }, /* doc says mb88341 */
304 .ai_maxdata = 0x0fff,
305 .ai_fifo_depth = 512,
306 .gainlkup = ai_gain_16,
309 .ao_maxdata = 0x0fff,
310 .ao_fifo_depth = 512,
311 .ao_range_table = &range_ni_E_ao_ext,
313 .caldac = { mb88341 },
318 .ai_maxdata = 0xffff,
319 .ai_fifo_depth = 512,
321 .gainlkup = ai_gain_14,
324 .ao_maxdata = 0xffff,
325 .ao_fifo_depth = 2048,
326 .ao_range_table = &range_ni_E_ao_ext,
328 .caldac = { dac8800, dac8043, ad8522 },
333 .ai_maxdata = 0xffff,
334 .ai_fifo_depth = 512,
336 .gainlkup = ai_gain_14,
338 .caldac = { dac8800, dac8043, ad8522 },
343 .ai_maxdata = 0xffff,
344 .ai_fifo_depth = 512,
346 .gainlkup = ai_gain_14,
348 .caldac = { dac8800, dac8043, ad8522 },
353 .ai_maxdata = 0x0fff,
354 .ai_fifo_depth = 512,
356 .gainlkup = ai_gain_16,
359 .ao_maxdata = 0x0fff,
360 .ao_fifo_depth = 2048,
361 .ao_range_table = &range_ni_E_ao_ext,
363 .caldac = { ad8804_debug },
368 .ai_maxdata = 0x0fff,
369 .ai_fifo_depth = 512,
370 .gainlkup = ai_gain_4,
372 .caldac = { ad8804_debug }, /* manual is wrong */
377 .ai_maxdata = 0x0fff,
378 .ai_fifo_depth = 512,
379 .gainlkup = ai_gain_4,
382 .ao_maxdata = 0x0fff,
383 .ao_range_table = &range_bipolar10,
385 .caldac = { ad8804_debug }, /* manual is wrong */
390 .ai_maxdata = 0x0fff,
391 .ai_fifo_depth = 512,
392 .gainlkup = ai_gain_4,
395 .ao_maxdata = 0x0fff,
396 .ao_range_table = &range_bipolar10,
398 .caldac = { ad8804_debug }, /* manual is wrong */
404 .ai_maxdata = 0x0fff,
405 .ai_fifo_depth = 512,
406 .gainlkup = ai_gain_4,
409 .ao_maxdata = 0x0fff,
410 .ao_range_table = &range_ni_E_ao_ext,
412 .caldac = { ad8804_debug }, /* manual is wrong */
418 .ai_maxdata = 0xffff,
419 .ai_fifo_depth = 512,
421 .gainlkup = ai_gain_4,
423 .caldac = { ad8804_debug },
428 .ai_maxdata = 0xffff,
429 .ai_fifo_depth = 512,
431 .gainlkup = ai_gain_4,
434 .ao_maxdata = 0x0fff,
435 .ao_range_table = &range_bipolar10,
437 .caldac = { ad8804_debug },
442 .ai_maxdata = 0xffff,
443 .ai_fifo_depth = 512,
445 .gainlkup = ai_gain_16,
448 .ao_maxdata = 0xffff,
449 .ao_fifo_depth = 2048,
450 .ao_range_table = &range_ni_E_ao_ext,
452 /* manual is wrong */
453 .caldac = { ad8804_debug, ad8804_debug, ad8522 },
458 .ai_maxdata = 0x0fff,
459 .ai_fifo_depth = 8192,
461 .gainlkup = ai_gain_611x,
464 .ao_maxdata = 0xffff,
465 .reg_type = ni_reg_611x,
466 .ao_range_table = &range_bipolar10,
467 .ao_fifo_depth = 2048,
469 .caldac = { ad8804, ad8804 },
474 .ai_maxdata = 0x0fff,
475 .ai_fifo_depth = 8192,
476 .gainlkup = ai_gain_611x,
479 .ao_maxdata = 0xffff,
480 .reg_type = ni_reg_611x,
481 .ao_range_table = &range_bipolar10,
482 .ao_fifo_depth = 2048,
484 .caldac = { ad8804, ad8804 },
487 /* The 6115 boards probably need their own driver */
488 [BOARD_PCI6115] = { /* .device_id = 0x2ed0, */
491 .ai_maxdata = 0x0fff,
492 .ai_fifo_depth = 8192,
493 .gainlkup = ai_gain_611x,
496 .ao_maxdata = 0xffff,
498 .ao_fifo_depth = 2048,
502 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
506 [BOARD_PXI6115] = { /* .device_id = ????, */
509 .ai_maxdata = 0x0fff,
510 .ai_fifo_depth = 8192,
511 .gainlkup = ai_gain_611x,
514 .ao_maxdata = 0xffff,
516 .ao_fifo_depth = 2048,
520 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
526 .ao_maxdata = 0x0fff,
527 /* data sheet says 8192, but fifo really holds 16384 samples */
528 .ao_fifo_depth = 16384,
529 .ao_range_table = &range_bipolar10,
531 .reg_type = ni_reg_6711,
532 .caldac = { ad8804_debug },
537 .ao_maxdata = 0x0fff,
538 .ao_fifo_depth = 16384,
539 .ao_range_table = &range_bipolar10,
541 .reg_type = ni_reg_6711,
542 .caldac = { ad8804_debug },
547 .ao_maxdata = 0x0fff,
548 .ao_fifo_depth = 16384,
549 .ao_range_table = &range_bipolar10,
551 .reg_type = ni_reg_6713,
552 .caldac = { ad8804_debug, ad8804_debug },
557 .ao_maxdata = 0x0fff,
558 .ao_fifo_depth = 16384,
559 .ao_range_table = &range_bipolar10,
561 .reg_type = ni_reg_6713,
562 .caldac = { ad8804_debug, ad8804_debug },
567 .ao_maxdata = 0xffff,
568 .ao_fifo_depth = 8192,
569 .ao_range_table = &range_bipolar10,
571 .reg_type = ni_reg_6711,
572 .caldac = { ad8804_debug },
575 [BOARD_PXI6731] = { /* .device_id = ????, */
578 .ao_maxdata = 0xffff,
579 .ao_fifo_depth = 8192,
580 .ao_range_table = &range_bipolar10,
581 .reg_type = ni_reg_6711,
582 .caldac = { ad8804_debug },
588 .ao_maxdata = 0xffff,
589 .ao_fifo_depth = 16384,
590 .ao_range_table = &range_bipolar10,
592 .reg_type = ni_reg_6713,
593 .caldac = { ad8804_debug, ad8804_debug },
598 .ao_maxdata = 0xffff,
599 .ao_fifo_depth = 16384,
600 .ao_range_table = &range_bipolar10,
602 .reg_type = ni_reg_6713,
603 .caldac = { ad8804_debug, ad8804_debug },
608 .ai_maxdata = 0x0fff,
609 .ai_fifo_depth = 512,
611 .gainlkup = ai_gain_16,
614 .ao_maxdata = 0x0fff,
615 .ao_fifo_depth = 2048,
616 .ao_range_table = &range_ni_E_ao_ext,
618 .caldac = { ad8804_debug },
623 .ai_maxdata = 0x0fff,
624 .ai_fifo_depth = 512,
626 .gainlkup = ai_gain_16,
629 .ao_maxdata = 0x0fff,
630 .ao_fifo_depth = 2048,
631 .ao_range_table = &range_ni_E_ao_ext,
633 .caldac = { ad8804_debug },
638 .ai_maxdata = 0xffff,
639 .ai_fifo_depth = 512,
641 .gainlkup = ai_gain_16,
644 .ao_maxdata = 0xffff,
645 .ao_fifo_depth = 2048,
646 .ao_range_table = &range_ni_E_ao_ext,
648 .caldac = { mb88341, mb88341, ad8522 },
653 .ai_maxdata = 0xffff,
654 .ai_fifo_depth = 512,
656 .gainlkup = ai_gain_14,
659 .ao_maxdata = 0xffff,
660 .ao_fifo_depth = 2048,
661 .ao_range_table = &range_ni_E_ao_ext,
663 .caldac = { dac8800, dac8043, ad8522 },
668 .ai_maxdata = 0xffff,
669 .ai_fifo_depth = 512,
671 .gainlkup = ai_gain_4,
674 .ao_maxdata = 0xffff,
675 .ao_range_table = &range_bipolar10,
677 .caldac = { ad8804_debug },
682 .ai_maxdata = 0xffff,
683 .ai_fifo_depth = 512, /* FIXME: guess */
684 .gainlkup = ai_gain_622x,
686 .reg_type = ni_reg_622x,
687 .caldac = { caldac_none },
692 .ai_maxdata = 0xffff,
693 .ai_fifo_depth = 4095,
694 .gainlkup = ai_gain_622x,
697 .ao_maxdata = 0xffff,
698 .ao_fifo_depth = 8191,
699 .ao_range_table = &range_bipolar10,
700 .reg_type = ni_reg_622x,
702 .caldac = { caldac_none },
704 [BOARD_PCI6221_37PIN] = {
705 .name = "pci-6221_37pin",
707 .ai_maxdata = 0xffff,
708 .ai_fifo_depth = 4095,
709 .gainlkup = ai_gain_622x,
712 .ao_maxdata = 0xffff,
713 .ao_fifo_depth = 8191,
714 .ao_range_table = &range_bipolar10,
715 .reg_type = ni_reg_622x,
717 .caldac = { caldac_none },
722 .ai_maxdata = 0xffff,
723 .ai_fifo_depth = 4095,
724 .gainlkup = ai_gain_622x,
726 .reg_type = ni_reg_622x,
728 .caldac = { caldac_none },
733 .ai_maxdata = 0xffff,
734 .ai_fifo_depth = 4095,
735 .gainlkup = ai_gain_622x,
737 .reg_type = ni_reg_622x,
739 .caldac = { caldac_none },
744 .ai_maxdata = 0xffff,
745 .ai_fifo_depth = 4095,
746 .gainlkup = ai_gain_622x,
749 .ao_maxdata = 0xffff,
750 .ao_fifo_depth = 8191,
751 .ao_range_table = &range_bipolar10,
752 .reg_type = ni_reg_622x,
755 .caldac = { caldac_none },
760 .ai_maxdata = 0xffff,
761 .ai_fifo_depth = 4095,
762 .gainlkup = ai_gain_622x,
765 .ao_maxdata = 0xffff,
766 .ao_fifo_depth = 8191,
767 .ao_range_table = &range_bipolar10,
768 .reg_type = ni_reg_622x,
771 .caldac = { caldac_none },
776 .ai_maxdata = 0xffff,
777 .ai_fifo_depth = 4095,
778 .gainlkup = ai_gain_622x,
781 .ao_maxdata = 0xffff,
782 .ao_fifo_depth = 8191,
783 .ao_range_table = &range_bipolar10,
784 .reg_type = ni_reg_622x,
787 .caldac = { caldac_none },
792 .ai_maxdata = 0xffff,
793 .ai_fifo_depth = 4095,
794 .gainlkup = ai_gain_628x,
796 .reg_type = ni_reg_625x,
797 .caldac = { caldac_none },
802 .ai_maxdata = 0xffff,
803 .ai_fifo_depth = 4095,
804 .gainlkup = ai_gain_628x,
807 .ao_maxdata = 0xffff,
808 .ao_fifo_depth = 8191,
809 .ao_range_table = &range_ni_M_625x_ao,
810 .reg_type = ni_reg_625x,
812 .caldac = { caldac_none },
817 .ai_maxdata = 0xffff,
818 .ai_fifo_depth = 4095,
819 .gainlkup = ai_gain_628x,
822 .ao_maxdata = 0xffff,
823 .ao_fifo_depth = 8191,
824 .ao_range_table = &range_ni_M_625x_ao,
825 .reg_type = ni_reg_625x,
827 .caldac = { caldac_none },
832 .ai_maxdata = 0xffff,
833 .ai_fifo_depth = 4095,
834 .gainlkup = ai_gain_628x,
837 .ao_maxdata = 0xffff,
838 .ao_fifo_depth = 8191,
839 .ao_range_table = &range_ni_M_625x_ao,
840 .reg_type = ni_reg_625x,
842 .caldac = { caldac_none },
847 .ai_maxdata = 0xffff,
848 .ai_fifo_depth = 4095,
849 .gainlkup = ai_gain_628x,
851 .reg_type = ni_reg_625x,
853 .caldac = { caldac_none },
858 .ai_maxdata = 0xffff,
859 .ai_fifo_depth = 4095,
860 .gainlkup = ai_gain_628x,
863 .ao_maxdata = 0xffff,
864 .ao_fifo_depth = 8191,
865 .ao_range_table = &range_ni_M_625x_ao,
866 .reg_type = ni_reg_625x,
869 .caldac = { caldac_none },
874 .ai_maxdata = 0xffff,
875 .ai_fifo_depth = 4095,
876 .gainlkup = ai_gain_628x,
879 .ao_maxdata = 0xffff,
880 .ao_fifo_depth = 8191,
881 .ao_range_table = &range_ni_M_625x_ao,
882 .reg_type = ni_reg_625x,
885 .caldac = { caldac_none },
890 .ai_maxdata = 0x3ffff,
891 .ai_fifo_depth = 2047,
892 .gainlkup = ai_gain_628x,
894 .ao_fifo_depth = 8191,
895 .reg_type = ni_reg_628x,
896 .caldac = { caldac_none },
901 .ai_maxdata = 0x3ffff,
902 .ai_fifo_depth = 2047,
903 .gainlkup = ai_gain_628x,
906 .ao_maxdata = 0xffff,
907 .ao_fifo_depth = 8191,
908 .ao_range_table = &range_ni_M_628x_ao,
909 .reg_type = ni_reg_628x,
911 .caldac = { caldac_none },
916 .ai_maxdata = 0x3ffff,
917 .ai_fifo_depth = 2047,
918 .gainlkup = ai_gain_628x,
921 .ao_maxdata = 0xffff,
922 .ao_fifo_depth = 8191,
923 .ao_range_table = &range_ni_M_628x_ao,
924 .reg_type = ni_reg_628x,
926 .caldac = { caldac_none },
931 .ai_maxdata = 0x3ffff,
932 .ai_fifo_depth = 2047,
933 .gainlkup = ai_gain_628x,
935 .reg_type = ni_reg_628x,
937 .caldac = { caldac_none },
942 .ai_maxdata = 0x3ffff,
943 .ai_fifo_depth = 2047,
944 .gainlkup = ai_gain_628x,
947 .ao_maxdata = 0xffff,
948 .ao_fifo_depth = 8191,
949 .ao_range_table = &range_ni_M_628x_ao,
950 .reg_type = ni_reg_628x,
953 .caldac = { caldac_none },
958 .ai_maxdata = 0xffff,
959 .ai_fifo_depth = 1024,
960 .gainlkup = ai_gain_6143,
962 .reg_type = ni_reg_6143,
963 .caldac = { ad8804_debug, ad8804_debug },
968 .ai_maxdata = 0xffff,
969 .ai_fifo_depth = 1024,
970 .gainlkup = ai_gain_6143,
972 .reg_type = ni_reg_6143,
973 .caldac = { ad8804_debug, ad8804_debug },
977 #include "ni_mio_common.c"
979 static int pcimio_ai_change(struct comedi_device *dev,
980 struct comedi_subdevice *s)
982 struct ni_private *devpriv = dev->private;
985 ret = mite_buf_change(devpriv->ai_mite_ring, s);
992 static int pcimio_ao_change(struct comedi_device *dev,
993 struct comedi_subdevice *s)
995 struct ni_private *devpriv = dev->private;
998 ret = mite_buf_change(devpriv->ao_mite_ring, s);
1005 static int pcimio_gpct0_change(struct comedi_device *dev,
1006 struct comedi_subdevice *s)
1008 struct ni_private *devpriv = dev->private;
1011 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s);
1018 static int pcimio_gpct1_change(struct comedi_device *dev,
1019 struct comedi_subdevice *s)
1021 struct ni_private *devpriv = dev->private;
1024 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s);
1031 static int pcimio_dio_change(struct comedi_device *dev,
1032 struct comedi_subdevice *s)
1034 struct ni_private *devpriv = dev->private;
1037 ret = mite_buf_change(devpriv->cdo_mite_ring, s);
1044 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1046 struct ni_private *devpriv = dev->private;
1047 static const int Start_Cal_EEPROM = 0x400;
1048 static const unsigned window_size = 10;
1049 static const int serial_number_eeprom_offset = 0x4;
1050 static const int serial_number_eeprom_length = 0x4;
1051 unsigned old_iodwbsr_bits;
1052 unsigned old_iodwbsr1_bits;
1053 unsigned old_iodwcr1_bits;
1056 old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR);
1057 old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1058 old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1059 writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1060 writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr),
1061 devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1062 writel(0x1 | old_iodwcr1_bits,
1063 devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1064 writel(0xf, devpriv->mite->mite_io_addr + 0x30);
1066 BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1067 for (i = 0; i < serial_number_eeprom_length; ++i) {
1068 char *byte_ptr = (char *)&devpriv->serial_number + i;
1069 *byte_ptr = ni_readb(dev, serial_number_eeprom_offset + i);
1071 devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1073 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1074 devpriv->eeprom_buffer[i] = ni_readb(dev, Start_Cal_EEPROM + i);
1076 writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1077 writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1078 writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1079 writel(0x0, devpriv->mite->mite_io_addr + 0x30);
1082 static void init_6143(struct comedi_device *dev)
1084 const struct ni_board_struct *board = dev->board_ptr;
1085 struct ni_private *devpriv = dev->private;
1087 /* Disable interrupts */
1088 ni_stc_writew(dev, 0, Interrupt_Control_Register);
1090 /* Initialise 6143 AI specific bits */
1092 /* Set G0,G1 DMA mode to E series version */
1093 ni_writeb(dev, 0x00, Magic_6143);
1094 /* Set EOCMode, ADCMode and pipelinedelay */
1095 ni_writeb(dev, 0x80, PipelineDelay_6143);
1097 ni_writeb(dev, 0x00, EOC_Set_6143);
1099 /* Set the FIFO half full level */
1100 ni_writel(dev, board->ai_fifo_depth / 2, AIFIFO_Flag_6143);
1102 /* Strobe Relay disable bit */
1103 devpriv->ai_calib_source_enabled = 0;
1104 ni_writew(dev, devpriv->ai_calib_source |
1105 Calibration_Channel_6143_RelayOff,
1106 Calibration_Channel_6143);
1107 ni_writew(dev, devpriv->ai_calib_source, Calibration_Channel_6143);
1110 static void pcimio_detach(struct comedi_device *dev)
1112 struct ni_private *devpriv = dev->private;
1114 mio_common_detach(dev);
1116 free_irq(dev->irq, dev);
1118 mite_free_ring(devpriv->ai_mite_ring);
1119 mite_free_ring(devpriv->ao_mite_ring);
1120 mite_free_ring(devpriv->cdo_mite_ring);
1121 mite_free_ring(devpriv->gpct_mite_ring[0]);
1122 mite_free_ring(devpriv->gpct_mite_ring[1]);
1123 mite_detach(devpriv->mite);
1127 comedi_pci_disable(dev);
1130 static int pcimio_auto_attach(struct comedi_device *dev,
1131 unsigned long context)
1133 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1134 const struct ni_board_struct *board = NULL;
1135 struct ni_private *devpriv;
1139 if (context < ARRAY_SIZE(ni_boards))
1140 board = &ni_boards[context];
1143 dev->board_ptr = board;
1144 dev->board_name = board->name;
1146 ret = comedi_pci_enable(dev);
1150 ret = ni_alloc_private(dev);
1153 devpriv = dev->private;
1155 devpriv->mite = mite_alloc(pcidev);
1159 if (board->reg_type & ni_reg_m_series_mask)
1160 devpriv->is_m_series = 1;
1161 if (board->reg_type & ni_reg_6xxx_mask)
1162 devpriv->is_6xxx = 1;
1163 if (board->reg_type == ni_reg_611x)
1164 devpriv->is_611x = 1;
1165 if (board->reg_type == ni_reg_6143)
1166 devpriv->is_6143 = 1;
1167 if (board->reg_type == ni_reg_622x)
1168 devpriv->is_622x = 1;
1169 if (board->reg_type == ni_reg_625x)
1170 devpriv->is_625x = 1;
1171 if (board->reg_type == ni_reg_628x)
1172 devpriv->is_628x = 1;
1173 if (board->reg_type & ni_reg_67xx_mask)
1174 devpriv->is_67xx = 1;
1175 if (board->reg_type == ni_reg_6711)
1176 devpriv->is_6711 = 1;
1177 if (board->reg_type == ni_reg_6713)
1178 devpriv->is_6713 = 1;
1180 ret = mite_setup(dev, devpriv->mite);
1184 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1185 if (!devpriv->ai_mite_ring)
1187 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1188 if (!devpriv->ao_mite_ring)
1190 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1191 if (!devpriv->cdo_mite_ring)
1193 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1194 if (!devpriv->gpct_mite_ring[0])
1196 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1197 if (!devpriv->gpct_mite_ring[1])
1200 if (devpriv->is_m_series)
1201 m_series_init_eeprom_buffer(dev);
1202 if (devpriv->is_6143)
1207 ret = request_irq(irq, ni_E_interrupt, IRQF_SHARED,
1208 dev->board_name, dev);
1213 ret = ni_E_init(dev, 0, 1);
1217 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1218 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1219 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1220 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1221 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1226 static struct comedi_driver ni_pcimio_driver = {
1227 .driver_name = "ni_pcimio",
1228 .module = THIS_MODULE,
1229 .auto_attach = pcimio_auto_attach,
1230 .detach = pcimio_detach,
1233 static int ni_pcimio_pci_probe(struct pci_dev *dev,
1234 const struct pci_device_id *id)
1236 return comedi_pci_auto_config(dev, &ni_pcimio_driver, id->driver_data);
1239 static const struct pci_device_id ni_pcimio_pci_table[] = {
1240 { PCI_VDEVICE(NI, 0x0162), BOARD_PCIMIO_16XE_50 }, /* 0x1620? */
1241 { PCI_VDEVICE(NI, 0x1170), BOARD_PCIMIO_16XE_10 },
1242 { PCI_VDEVICE(NI, 0x1180), BOARD_PCIMIO_16E_1 },
1243 { PCI_VDEVICE(NI, 0x1190), BOARD_PCIMIO_16E_4 },
1244 { PCI_VDEVICE(NI, 0x11b0), BOARD_PXI6070E },
1245 { PCI_VDEVICE(NI, 0x11c0), BOARD_PXI6040E },
1246 { PCI_VDEVICE(NI, 0x11d0), BOARD_PXI6030E },
1247 { PCI_VDEVICE(NI, 0x1270), BOARD_PCI6032E },
1248 { PCI_VDEVICE(NI, 0x1330), BOARD_PCI6031E },
1249 { PCI_VDEVICE(NI, 0x1340), BOARD_PCI6033E },
1250 { PCI_VDEVICE(NI, 0x1350), BOARD_PCI6071E },
1251 { PCI_VDEVICE(NI, 0x14e0), BOARD_PCI6110 },
1252 { PCI_VDEVICE(NI, 0x14f0), BOARD_PCI6111 },
1253 { PCI_VDEVICE(NI, 0x1580), BOARD_PXI6031E },
1254 { PCI_VDEVICE(NI, 0x15b0), BOARD_PXI6071E },
1255 { PCI_VDEVICE(NI, 0x1880), BOARD_PCI6711 },
1256 { PCI_VDEVICE(NI, 0x1870), BOARD_PCI6713 },
1257 { PCI_VDEVICE(NI, 0x18b0), BOARD_PCI6052E },
1258 { PCI_VDEVICE(NI, 0x18c0), BOARD_PXI6052E },
1259 { PCI_VDEVICE(NI, 0x2410), BOARD_PCI6733 },
1260 { PCI_VDEVICE(NI, 0x2420), BOARD_PXI6733 },
1261 { PCI_VDEVICE(NI, 0x2430), BOARD_PCI6731 },
1262 { PCI_VDEVICE(NI, 0x2890), BOARD_PCI6036E },
1263 { PCI_VDEVICE(NI, 0x28c0), BOARD_PCI6014 },
1264 { PCI_VDEVICE(NI, 0x2a60), BOARD_PCI6023E },
1265 { PCI_VDEVICE(NI, 0x2a70), BOARD_PCI6024E },
1266 { PCI_VDEVICE(NI, 0x2a80), BOARD_PCI6025E },
1267 { PCI_VDEVICE(NI, 0x2ab0), BOARD_PXI6025E },
1268 { PCI_VDEVICE(NI, 0x2b80), BOARD_PXI6713 },
1269 { PCI_VDEVICE(NI, 0x2b90), BOARD_PXI6711 },
1270 { PCI_VDEVICE(NI, 0x2c80), BOARD_PCI6035E },
1271 { PCI_VDEVICE(NI, 0x2ca0), BOARD_PCI6034E },
1272 { PCI_VDEVICE(NI, 0x70aa), BOARD_PCI6229 },
1273 { PCI_VDEVICE(NI, 0x70ab), BOARD_PCI6259 },
1274 { PCI_VDEVICE(NI, 0x70ac), BOARD_PCI6289 },
1275 { PCI_VDEVICE(NI, 0x70af), BOARD_PCI6221 },
1276 { PCI_VDEVICE(NI, 0x70b0), BOARD_PCI6220 },
1277 { PCI_VDEVICE(NI, 0x70b4), BOARD_PCI6250 },
1278 { PCI_VDEVICE(NI, 0x70b6), BOARD_PCI6280 },
1279 { PCI_VDEVICE(NI, 0x70b7), BOARD_PCI6254 },
1280 { PCI_VDEVICE(NI, 0x70b8), BOARD_PCI6251 },
1281 { PCI_VDEVICE(NI, 0x70bc), BOARD_PCI6284 },
1282 { PCI_VDEVICE(NI, 0x70bd), BOARD_PCI6281 },
1283 { PCI_VDEVICE(NI, 0x70bf), BOARD_PXI6281 },
1284 { PCI_VDEVICE(NI, 0x70c0), BOARD_PCI6143 },
1285 { PCI_VDEVICE(NI, 0x70f2), BOARD_PCI6224 },
1286 { PCI_VDEVICE(NI, 0x70f3), BOARD_PXI6224 },
1287 { PCI_VDEVICE(NI, 0x710d), BOARD_PXI6143 },
1288 { PCI_VDEVICE(NI, 0x716c), BOARD_PCI6225 },
1289 { PCI_VDEVICE(NI, 0x716d), BOARD_PXI6225 },
1290 { PCI_VDEVICE(NI, 0x717f), BOARD_PCIE6259 },
1291 { PCI_VDEVICE(NI, 0x71bc), BOARD_PCI6221_37PIN },
1292 { PCI_VDEVICE(NI, 0x717d), BOARD_PCIE6251 },
1293 { PCI_VDEVICE(NI, 0x72e8), BOARD_PXIE6251 },
1296 MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1298 static struct pci_driver ni_pcimio_pci_driver = {
1299 .name = "ni_pcimio",
1300 .id_table = ni_pcimio_pci_table,
1301 .probe = ni_pcimio_pci_probe,
1302 .remove = comedi_pci_auto_unconfig,
1304 module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1306 MODULE_AUTHOR("Comedi http://www.comedi.org");
1307 MODULE_DESCRIPTION("Comedi low-level driver");
1308 MODULE_LICENSE("GPL");