2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
21 This file is meant to be included by another file, e.g.,
22 ni_atmio.c or ni_pcimio.c.
24 Interrupt support originally added by Truxton Fulton
27 References (from ftp://ftp.natinst.com/support/manuals):
29 340747b.pdf AT-MIO E series Register Level Programmer Manual
30 341079b.pdf PCI E Series RLPM
31 340934b.pdf DAQ-STC reference manual
32 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
35 Other possibly relevant info:
37 320517c.pdf User manual (obsolete)
38 320517f.pdf User manual (new)
40 320906c.pdf maximum signal ratings
42 321791a.pdf discontinuation of at-mio-16e-10 rev. c
43 321808a.pdf about at-mio-16e-10 rev P
44 321837a.pdf discontinuation of at-mio-16de-10 rev d
45 321838a.pdf about at-mio-16de-10 rev N
49 - the interrupt routine needs to be cleaned up
51 2006-02-07: S-Series PCI-6143: Support has been added but is not
52 fully tested as yet. Terry Barnaby, BEAM Ltd.
55 #include <linux/interrupt.h>
56 #include <linux/sched.h>
57 #include <linux/delay.h>
62 #define NI_TIMEOUT 1000
63 static const unsigned old_RTSI_clock_channel = 7;
65 /* Note: this table must match the ai_gain_* definitions */
66 static const short ni_gainlkup[][16] = {
67 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
68 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
69 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
70 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
71 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
72 [ai_gain_4] = {0, 1, 4, 7},
73 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
74 0x003, 0x004, 0x005, 0x006},
75 [ai_gain_622x] = {0, 1, 4, 5},
76 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
77 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
80 static const struct comedi_lrange range_ni_E_ai = {
101 static const struct comedi_lrange range_ni_E_ai_limited = {
114 static const struct comedi_lrange range_ni_E_ai_limited14 = {
133 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
142 static const struct comedi_lrange range_ni_E_ai_611x = {
155 static const struct comedi_lrange range_ni_M_ai_622x = {
164 static const struct comedi_lrange range_ni_M_ai_628x = {
176 static const struct comedi_lrange range_ni_E_ao_ext = {
185 static const struct comedi_lrange *const ni_range_lkup[] = {
186 [ai_gain_16] = &range_ni_E_ai,
187 [ai_gain_8] = &range_ni_E_ai_limited,
188 [ai_gain_14] = &range_ni_E_ai_limited14,
189 [ai_gain_4] = &range_ni_E_ai_bipolar4,
190 [ai_gain_611x] = &range_ni_E_ai_611x,
191 [ai_gain_622x] = &range_ni_M_ai_622x,
192 [ai_gain_628x] = &range_ni_M_ai_628x,
193 [ai_gain_6143] = &range_bipolar5
198 AIMODE_HALF_FULL = 1,
203 enum ni_common_subdevices {
209 NI_CALIBRATION_SUBDEV,
212 NI_CS5529_CALIBRATION_SUBDEV,
220 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
222 switch (counter_index) {
224 return NI_GPCT0_SUBDEV;
226 return NI_GPCT1_SUBDEV;
231 return NI_GPCT0_SUBDEV;
234 enum timebase_nanoseconds {
236 TIMEBASE_2_NS = 10000
239 #define SERIAL_DISABLED 0
240 #define SERIAL_600NS 600
241 #define SERIAL_1_2US 1200
242 #define SERIAL_10US 10000
244 static const int num_adc_stages_611x = 3;
246 static void ni_writel(struct comedi_device *dev, uint32_t data, int reg)
249 writel(data, dev->mmio + reg);
251 outl(data, dev->iobase + reg);
254 static void ni_writew(struct comedi_device *dev, uint16_t data, int reg)
257 writew(data, dev->mmio + reg);
259 outw(data, dev->iobase + reg);
262 static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg)
265 writeb(data, dev->mmio + reg);
267 outb(data, dev->iobase + reg);
270 static uint32_t ni_readl(struct comedi_device *dev, int reg)
273 return readl(dev->mmio + reg);
275 return inl(dev->iobase + reg);
278 static uint16_t ni_readw(struct comedi_device *dev, int reg)
281 return readw(dev->mmio + reg);
283 return inw(dev->iobase + reg);
286 static uint8_t ni_readb(struct comedi_device *dev, int reg)
289 return readb(dev->mmio + reg);
291 return inb(dev->iobase + reg);
295 * We automatically take advantage of STC registers that can be
296 * read/written directly in the I/O space of the board.
298 * The AT-MIO and DAQCard devices map the low 8 STC registers to
301 * Most PCIMIO devices also map the low 8 STC registers but the
302 * 611x devices map the read registers to iobase+(addr-1)*2.
303 * For now non-windowed STC access is disabled if a PCIMIO device
304 * is detected (devpriv->mite has been initialized).
306 * The M series devices do not used windowed registers for the
307 * STC registers. The functions below handle the mapping of the
308 * windowed STC registers to the m series register offsets.
311 static void m_series_stc_writel(struct comedi_device *dev,
312 uint32_t data, int reg)
317 case AI_SC_Load_A_Registers:
318 offset = M_Offset_AI_SC_Load_A;
320 case AI_SI_Load_A_Registers:
321 offset = M_Offset_AI_SI_Load_A;
323 case AO_BC_Load_A_Register:
324 offset = M_Offset_AO_BC_Load_A;
326 case AO_UC_Load_A_Register:
327 offset = M_Offset_AO_UC_Load_A;
329 case AO_UI_Load_A_Register:
330 offset = M_Offset_AO_UI_Load_A;
332 case G_Load_A_Register(0):
333 offset = M_Offset_G0_Load_A;
335 case G_Load_A_Register(1):
336 offset = M_Offset_G1_Load_A;
338 case G_Load_B_Register(0):
339 offset = M_Offset_G0_Load_B;
341 case G_Load_B_Register(1):
342 offset = M_Offset_G1_Load_B;
345 dev_warn(dev->class_dev,
346 "%s: bug! unhandled register=0x%x in switch\n",
350 ni_writel(dev, data, offset);
353 static void m_series_stc_writew(struct comedi_device *dev,
354 uint16_t data, int reg)
360 offset = M_Offset_AI_FIFO_Clear;
362 case AI_Command_1_Register:
363 offset = M_Offset_AI_Command_1;
365 case AI_Command_2_Register:
366 offset = M_Offset_AI_Command_2;
368 case AI_Mode_1_Register:
369 offset = M_Offset_AI_Mode_1;
371 case AI_Mode_2_Register:
372 offset = M_Offset_AI_Mode_2;
374 case AI_Mode_3_Register:
375 offset = M_Offset_AI_Mode_3;
377 case AI_Output_Control_Register:
378 offset = M_Offset_AI_Output_Control;
380 case AI_Personal_Register:
381 offset = M_Offset_AI_Personal;
383 case AI_SI2_Load_A_Register:
384 /* this is a 32 bit register on m series boards */
385 ni_writel(dev, data, M_Offset_AI_SI2_Load_A);
387 case AI_SI2_Load_B_Register:
388 /* this is a 32 bit register on m series boards */
389 ni_writel(dev, data, M_Offset_AI_SI2_Load_B);
391 case AI_START_STOP_Select_Register:
392 offset = M_Offset_AI_START_STOP_Select;
394 case AI_Trigger_Select_Register:
395 offset = M_Offset_AI_Trigger_Select;
397 case Analog_Trigger_Etc_Register:
398 offset = M_Offset_Analog_Trigger_Etc;
400 case AO_Command_1_Register:
401 offset = M_Offset_AO_Command_1;
403 case AO_Command_2_Register:
404 offset = M_Offset_AO_Command_2;
406 case AO_Mode_1_Register:
407 offset = M_Offset_AO_Mode_1;
409 case AO_Mode_2_Register:
410 offset = M_Offset_AO_Mode_2;
412 case AO_Mode_3_Register:
413 offset = M_Offset_AO_Mode_3;
415 case AO_Output_Control_Register:
416 offset = M_Offset_AO_Output_Control;
418 case AO_Personal_Register:
419 offset = M_Offset_AO_Personal;
421 case AO_Start_Select_Register:
422 offset = M_Offset_AO_Start_Select;
424 case AO_Trigger_Select_Register:
425 offset = M_Offset_AO_Trigger_Select;
427 case Clock_and_FOUT_Register:
428 offset = M_Offset_Clock_and_FOUT;
430 case Configuration_Memory_Clear:
431 offset = M_Offset_Configuration_Memory_Clear;
434 offset = M_Offset_AO_FIFO_Clear;
436 case DIO_Control_Register:
437 dev_dbg(dev->class_dev,
438 "%s: FIXME: register 0x%x does not map cleanly on to m-series boards\n",
441 case G_Autoincrement_Register(0):
442 offset = M_Offset_G0_Autoincrement;
444 case G_Autoincrement_Register(1):
445 offset = M_Offset_G1_Autoincrement;
447 case G_Command_Register(0):
448 offset = M_Offset_G0_Command;
450 case G_Command_Register(1):
451 offset = M_Offset_G1_Command;
453 case G_Input_Select_Register(0):
454 offset = M_Offset_G0_Input_Select;
456 case G_Input_Select_Register(1):
457 offset = M_Offset_G1_Input_Select;
459 case G_Mode_Register(0):
460 offset = M_Offset_G0_Mode;
462 case G_Mode_Register(1):
463 offset = M_Offset_G1_Mode;
465 case Interrupt_A_Ack_Register:
466 offset = M_Offset_Interrupt_A_Ack;
468 case Interrupt_A_Enable_Register:
469 offset = M_Offset_Interrupt_A_Enable;
471 case Interrupt_B_Ack_Register:
472 offset = M_Offset_Interrupt_B_Ack;
474 case Interrupt_B_Enable_Register:
475 offset = M_Offset_Interrupt_B_Enable;
477 case Interrupt_Control_Register:
478 offset = M_Offset_Interrupt_Control;
480 case IO_Bidirection_Pin_Register:
481 offset = M_Offset_IO_Bidirection_Pin;
483 case Joint_Reset_Register:
484 offset = M_Offset_Joint_Reset;
486 case RTSI_Trig_A_Output_Register:
487 offset = M_Offset_RTSI_Trig_A_Output;
489 case RTSI_Trig_B_Output_Register:
490 offset = M_Offset_RTSI_Trig_B_Output;
492 case RTSI_Trig_Direction_Register:
493 offset = M_Offset_RTSI_Trig_Direction;
496 * FIXME: DIO_Output_Register (16 bit reg) is replaced by
497 * M_Offset_Static_Digital_Output (32 bit) and
498 * M_Offset_SCXI_Serial_Data_Out (8 bit)
501 dev_warn(dev->class_dev,
502 "%s: bug! unhandled register=0x%x in switch\n",
506 ni_writew(dev, data, offset);
509 static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
514 case G_HW_Save_Register(0):
515 offset = M_Offset_G0_HW_Save;
517 case G_HW_Save_Register(1):
518 offset = M_Offset_G1_HW_Save;
520 case G_Save_Register(0):
521 offset = M_Offset_G0_Save;
523 case G_Save_Register(1):
524 offset = M_Offset_G1_Save;
527 dev_warn(dev->class_dev,
528 "%s: bug! unhandled register=0x%x in switch\n",
532 return ni_readl(dev, offset);
535 static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
540 case AI_Status_1_Register:
541 offset = M_Offset_AI_Status_1;
543 case AO_Status_1_Register:
544 offset = M_Offset_AO_Status_1;
546 case AO_Status_2_Register:
547 offset = M_Offset_AO_Status_2;
549 case DIO_Serial_Input_Register:
550 return ni_readb(dev, M_Offset_SCXI_Serial_Data_In);
551 case Joint_Status_1_Register:
552 offset = M_Offset_Joint_Status_1;
554 case Joint_Status_2_Register:
555 offset = M_Offset_Joint_Status_2;
557 case G_Status_Register:
558 offset = M_Offset_G01_Status;
561 dev_warn(dev->class_dev,
562 "%s: bug! unhandled register=0x%x in switch\n",
566 return ni_readw(dev, offset);
569 static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg)
571 struct ni_private *devpriv = dev->private;
574 if (devpriv->is_m_series) {
575 m_series_stc_writew(dev, data, reg);
577 spin_lock_irqsave(&devpriv->window_lock, flags);
578 if (!devpriv->mite && reg < 8) {
579 ni_writew(dev, data, reg * 2);
581 ni_writew(dev, reg, Window_Address);
582 ni_writew(dev, data, Window_Data);
584 spin_unlock_irqrestore(&devpriv->window_lock, flags);
588 static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg)
590 struct ni_private *devpriv = dev->private;
592 if (devpriv->is_m_series) {
593 m_series_stc_writel(dev, data, reg);
595 ni_stc_writew(dev, data >> 16, reg);
596 ni_stc_writew(dev, data & 0xffff, reg + 1);
600 static uint16_t ni_stc_readw(struct comedi_device *dev, int reg)
602 struct ni_private *devpriv = dev->private;
606 if (devpriv->is_m_series) {
607 val = m_series_stc_readw(dev, reg);
609 spin_lock_irqsave(&devpriv->window_lock, flags);
610 if (!devpriv->mite && reg < 8) {
611 val = ni_readw(dev, reg * 2);
613 ni_writew(dev, reg, Window_Address);
614 val = ni_readw(dev, Window_Data);
616 spin_unlock_irqrestore(&devpriv->window_lock, flags);
621 static uint32_t ni_stc_readl(struct comedi_device *dev, int reg)
623 struct ni_private *devpriv = dev->private;
626 if (devpriv->is_m_series) {
627 val = m_series_stc_readl(dev, reg);
629 val = ni_stc_readw(dev, reg) << 16;
630 val |= ni_stc_readw(dev, reg + 1);
635 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
636 unsigned bit_mask, unsigned bit_values)
638 struct ni_private *devpriv = dev->private;
641 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
643 case Interrupt_A_Enable_Register:
644 devpriv->int_a_enable_reg &= ~bit_mask;
645 devpriv->int_a_enable_reg |= bit_values & bit_mask;
646 ni_stc_writew(dev, devpriv->int_a_enable_reg,
647 Interrupt_A_Enable_Register);
649 case Interrupt_B_Enable_Register:
650 devpriv->int_b_enable_reg &= ~bit_mask;
651 devpriv->int_b_enable_reg |= bit_values & bit_mask;
652 ni_stc_writew(dev, devpriv->int_b_enable_reg,
653 Interrupt_B_Enable_Register);
655 case IO_Bidirection_Pin_Register:
656 devpriv->io_bidirection_pin_reg &= ~bit_mask;
657 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
658 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg,
659 IO_Bidirection_Pin_Register);
662 devpriv->ai_ao_select_reg &= ~bit_mask;
663 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
664 ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select);
667 devpriv->g0_g1_select_reg &= ~bit_mask;
668 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
669 ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select);
672 dev_err(dev->class_dev, "called with invalid register %d\n",
677 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
681 /* DMA channel setup */
683 /* negative channel means no channel */
684 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
690 (ni_stc_dma_channel_select_bitfield(channel) <<
691 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
694 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
697 /* negative channel means no channel */
698 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
704 (ni_stc_dma_channel_select_bitfield(channel) <<
705 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
708 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
711 /* negative mite_channel means no channel */
712 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
718 if (mite_channel >= 0)
719 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
722 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
726 /* negative mite_channel means no channel */
727 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
730 struct ni_private *devpriv = dev->private;
733 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
734 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
735 if (mite_channel >= 0) {
736 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
737 under the assumption the cdio dma selection works just like ai/ao/gpct.
738 Definitely works for dma channels 0 and 1. */
739 devpriv->cdio_dma_select_reg |=
740 (ni_stc_dma_channel_select_bitfield(mite_channel) <<
741 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
743 ni_writeb(dev, devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
745 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
748 static int ni_request_ai_mite_channel(struct comedi_device *dev)
750 struct ni_private *devpriv = dev->private;
753 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
754 BUG_ON(devpriv->ai_mite_chan);
755 devpriv->ai_mite_chan =
756 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
757 if (!devpriv->ai_mite_chan) {
758 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
759 dev_err(dev->class_dev,
760 "failed to reserve mite dma channel for analog input\n");
763 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
764 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
765 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
769 static int ni_request_ao_mite_channel(struct comedi_device *dev)
771 struct ni_private *devpriv = dev->private;
774 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
775 BUG_ON(devpriv->ao_mite_chan);
776 devpriv->ao_mite_chan =
777 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
778 if (!devpriv->ao_mite_chan) {
779 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
780 dev_err(dev->class_dev,
781 "failed to reserve mite dma channel for analog outut\n");
784 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
785 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
786 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
790 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
792 enum comedi_io_direction direction)
794 struct ni_private *devpriv = dev->private;
796 struct mite_channel *mite_chan;
798 BUG_ON(gpct_index >= NUM_GPCT);
799 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
800 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
802 mite_request_channel(devpriv->mite,
803 devpriv->gpct_mite_ring[gpct_index]);
805 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
806 dev_err(dev->class_dev,
807 "failed to reserve mite dma channel for counter\n");
810 mite_chan->dir = direction;
811 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
813 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
814 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
820 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
823 struct ni_private *devpriv = dev->private;
826 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
827 BUG_ON(devpriv->cdo_mite_chan);
828 devpriv->cdo_mite_chan =
829 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
830 if (!devpriv->cdo_mite_chan) {
831 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
832 dev_err(dev->class_dev,
833 "failed to reserve mite dma channel for correlated digital output\n");
836 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
837 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
838 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
843 static void ni_release_ai_mite_channel(struct comedi_device *dev)
846 struct ni_private *devpriv = dev->private;
849 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
850 if (devpriv->ai_mite_chan) {
851 ni_set_ai_dma_channel(dev, -1);
852 mite_release_channel(devpriv->ai_mite_chan);
853 devpriv->ai_mite_chan = NULL;
855 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
859 static void ni_release_ao_mite_channel(struct comedi_device *dev)
862 struct ni_private *devpriv = dev->private;
865 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
866 if (devpriv->ao_mite_chan) {
867 ni_set_ao_dma_channel(dev, -1);
868 mite_release_channel(devpriv->ao_mite_chan);
869 devpriv->ao_mite_chan = NULL;
871 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
876 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
879 struct ni_private *devpriv = dev->private;
882 BUG_ON(gpct_index >= NUM_GPCT);
883 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
884 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
885 struct mite_channel *mite_chan =
886 devpriv->counter_dev->counters[gpct_index].mite_chan;
888 ni_set_gpct_dma_channel(dev, gpct_index, -1);
889 ni_tio_set_mite_channel(&devpriv->
890 counter_dev->counters[gpct_index],
892 mite_release_channel(mite_chan);
894 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
898 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
901 struct ni_private *devpriv = dev->private;
904 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
905 if (devpriv->cdo_mite_chan) {
906 ni_set_cdo_dma_channel(dev, -1);
907 mite_release_channel(devpriv->cdo_mite_chan);
908 devpriv->cdo_mite_chan = NULL;
910 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
915 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
916 unsigned gpct_index, short enable)
918 struct ni_private *devpriv = dev->private;
922 if (devpriv->is_m_series || gpct_index > 1)
926 * e-series boards use the second irq signals to generate
927 * dma requests for their counters
929 if (gpct_index == 0) {
930 reg = Second_IRQ_A_Enable_Register;
932 val = G0_Gate_Second_Irq_Enable;
934 reg = Second_IRQ_B_Enable_Register;
936 val = G1_Gate_Second_Irq_Enable;
938 ni_stc_writew(dev, val, reg);
942 static void ni_clear_ai_fifo(struct comedi_device *dev)
944 struct ni_private *devpriv = dev->private;
945 static const int timeout = 10000;
948 if (devpriv->is_6143) {
949 /* Flush the 6143 data FIFO */
950 ni_writel(dev, 0x10, AIFIFO_Control_6143);
951 ni_writel(dev, 0x00, AIFIFO_Control_6143);
952 /* Wait for complete */
953 for (i = 0; i < timeout; i++) {
954 if (!(ni_readl(dev, AIFIFO_Status_6143) & 0x10))
959 dev_err(dev->class_dev, "FIFO flush timeout\n");
961 ni_stc_writew(dev, 1, ADC_FIFO_Clear);
962 if (devpriv->is_625x) {
963 ni_writeb(dev, 0, M_Offset_Static_AI_Control(0));
964 ni_writeb(dev, 1, M_Offset_Static_AI_Control(0));
966 /* the NI example code does 3 convert pulses for 625x boards,
967 but that appears to be wrong in practice. */
968 ni_stc_writew(dev, AI_CONVERT_Pulse,
969 AI_Command_1_Register);
970 ni_stc_writew(dev, AI_CONVERT_Pulse,
971 AI_Command_1_Register);
972 ni_stc_writew(dev, AI_CONVERT_Pulse,
973 AI_Command_1_Register);
979 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
982 struct ni_private *devpriv = dev->private;
985 spin_lock_irqsave(&devpriv->window_lock, flags);
986 ni_writew(dev, addr, AO_Window_Address_611x);
987 ni_writew(dev, data, AO_Window_Data_611x);
988 spin_unlock_irqrestore(&devpriv->window_lock, flags);
991 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
994 struct ni_private *devpriv = dev->private;
997 spin_lock_irqsave(&devpriv->window_lock, flags);
998 ni_writew(dev, addr, AO_Window_Address_611x);
999 ni_writel(dev, data, AO_Window_Data_611x);
1000 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1003 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
1005 struct ni_private *devpriv = dev->private;
1006 unsigned long flags;
1007 unsigned short data;
1009 spin_lock_irqsave(&devpriv->window_lock, flags);
1010 ni_writew(dev, addr, AO_Window_Address_611x);
1011 data = ni_readw(dev, AO_Window_Data_611x);
1012 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1016 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
1017 * share registers (such as Interrupt_A_Register) without interfering with
1020 * NOTE: the switch/case statements are optimized out for a constant argument
1021 * so this is actually quite fast--- If you must wrap another function around this
1022 * make it inline to avoid a large speed penalty.
1024 * value should only be 1 or 0.
1026 static inline void ni_set_bits(struct comedi_device *dev, int reg,
1027 unsigned bits, unsigned value)
1029 unsigned bit_values;
1035 ni_set_bitfield(dev, reg, bits, bit_values);
1039 static void ni_sync_ai_dma(struct comedi_device *dev)
1041 struct ni_private *devpriv = dev->private;
1042 struct comedi_subdevice *s = dev->read_subdev;
1043 unsigned long flags;
1045 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1046 if (devpriv->ai_mite_chan)
1047 mite_sync_input_dma(devpriv->ai_mite_chan, s);
1048 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1051 static int ni_ai_drain_dma(struct comedi_device *dev)
1053 struct ni_private *devpriv = dev->private;
1055 static const int timeout = 10000;
1056 unsigned long flags;
1059 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1060 if (devpriv->ai_mite_chan) {
1061 for (i = 0; i < timeout; i++) {
1062 if ((ni_stc_readw(dev, AI_Status_1_Register) &
1064 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1070 dev_err(dev->class_dev, "timed out\n");
1071 dev_err(dev->class_dev,
1072 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1073 mite_bytes_in_transit(devpriv->ai_mite_chan),
1074 ni_stc_readw(dev, AI_Status_1_Register));
1078 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1080 ni_sync_ai_dma(dev);
1085 static void mite_handle_b_linkc(struct mite_struct *mite,
1086 struct comedi_device *dev)
1088 struct ni_private *devpriv = dev->private;
1089 struct comedi_subdevice *s = dev->write_subdev;
1090 unsigned long flags;
1092 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1093 if (devpriv->ao_mite_chan)
1094 mite_sync_output_dma(devpriv->ao_mite_chan, s);
1095 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1098 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
1100 static const int timeout = 10000;
1103 for (i = 0; i < timeout; i++) {
1104 unsigned short b_status;
1106 b_status = ni_stc_readw(dev, AO_Status_1_Register);
1107 if (b_status & AO_FIFO_Half_Full_St)
1109 /* if we poll too often, the pci bus activity seems
1110 to slow the dma transfer down */
1114 dev_err(dev->class_dev, "timed out waiting for dma load\n");
1123 static void ni_ao_fifo_load(struct comedi_device *dev,
1124 struct comedi_subdevice *s, int n)
1126 struct ni_private *devpriv = dev->private;
1131 for (i = 0; i < n; i++) {
1132 comedi_buf_read_samples(s, &d, 1);
1134 if (devpriv->is_6xxx) {
1135 packed_data = d & 0xffff;
1136 /* 6711 only has 16 bit wide ao fifo */
1137 if (!devpriv->is_6711) {
1138 comedi_buf_read_samples(s, &d, 1);
1140 packed_data |= (d << 16) & 0xffff0000;
1142 ni_writel(dev, packed_data, DAC_FIFO_Data_611x);
1144 ni_writew(dev, d, DAC_FIFO_Data);
1150 * There's a small problem if the FIFO gets really low and we
1151 * don't have the data to fill it. Basically, if after we fill
1152 * the FIFO with all the data available, the FIFO is _still_
1153 * less than half full, we never clear the interrupt. If the
1154 * IRQ is in edge mode, we never get another interrupt, because
1155 * this one wasn't cleared. If in level mode, we get flooded
1156 * with interrupts that we can't fulfill, because nothing ever
1157 * gets put into the buffer.
1159 * This kind of situation is recoverable, but it is easier to
1160 * just pretend we had a FIFO underrun, since there is a good
1161 * chance it will happen anyway. This is _not_ the case for
1162 * RT code, as RT code might purposely be running close to the
1163 * metal. Needs to be fixed eventually.
1165 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1166 struct comedi_subdevice *s)
1168 const struct ni_board_struct *board = dev->board_ptr;
1169 unsigned int nbytes;
1170 unsigned int nsamples;
1172 nbytes = comedi_buf_read_n_available(s);
1174 s->async->events |= COMEDI_CB_OVERFLOW;
1178 nsamples = comedi_bytes_to_samples(s, nbytes);
1179 if (nsamples > board->ao_fifo_depth / 2)
1180 nsamples = board->ao_fifo_depth / 2;
1182 ni_ao_fifo_load(dev, s, nsamples);
1187 static int ni_ao_prep_fifo(struct comedi_device *dev,
1188 struct comedi_subdevice *s)
1190 const struct ni_board_struct *board = dev->board_ptr;
1191 struct ni_private *devpriv = dev->private;
1192 unsigned int nbytes;
1193 unsigned int nsamples;
1196 ni_stc_writew(dev, 1, DAC_FIFO_Clear);
1197 if (devpriv->is_6xxx)
1198 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1200 /* load some data */
1201 nbytes = comedi_buf_read_n_available(s);
1205 nsamples = comedi_bytes_to_samples(s, nbytes);
1206 if (nsamples > board->ao_fifo_depth)
1207 nsamples = board->ao_fifo_depth;
1209 ni_ao_fifo_load(dev, s, nsamples);
1214 static void ni_ai_fifo_read(struct comedi_device *dev,
1215 struct comedi_subdevice *s, int n)
1217 struct ni_private *devpriv = dev->private;
1218 struct comedi_async *async = s->async;
1220 unsigned short data;
1223 if (devpriv->is_611x) {
1224 for (i = 0; i < n / 2; i++) {
1225 dl = ni_readl(dev, ADC_FIFO_Data_611x);
1226 /* This may get the hi/lo data in the wrong order */
1227 data = (dl >> 16) & 0xffff;
1228 comedi_buf_write_samples(s, &data, 1);
1230 comedi_buf_write_samples(s, &data, 1);
1232 /* Check if there's a single sample stuck in the FIFO */
1234 dl = ni_readl(dev, ADC_FIFO_Data_611x);
1236 comedi_buf_write_samples(s, &data, 1);
1238 } else if (devpriv->is_6143) {
1239 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1240 for (i = 0; i < n / 2; i++) {
1241 dl = ni_readl(dev, AIFIFO_Data_6143);
1243 data = (dl >> 16) & 0xffff;
1244 comedi_buf_write_samples(s, &data, 1);
1246 comedi_buf_write_samples(s, &data, 1);
1249 /* Assume there is a single sample stuck in the FIFO */
1250 /* Get stranded sample into FIFO */
1251 ni_writel(dev, 0x01, AIFIFO_Control_6143);
1252 dl = ni_readl(dev, AIFIFO_Data_6143);
1253 data = (dl >> 16) & 0xffff;
1254 comedi_buf_write_samples(s, &data, 1);
1257 if (n > sizeof(devpriv->ai_fifo_buffer) /
1258 sizeof(devpriv->ai_fifo_buffer[0])) {
1259 dev_err(dev->class_dev,
1260 "bug! ai_fifo_buffer too small\n");
1261 async->events |= COMEDI_CB_ERROR;
1264 for (i = 0; i < n; i++) {
1265 devpriv->ai_fifo_buffer[i] =
1266 ni_readw(dev, ADC_FIFO_Data_Register);
1268 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1272 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1274 const struct ni_board_struct *board = dev->board_ptr;
1275 struct comedi_subdevice *s = dev->read_subdev;
1278 n = board->ai_fifo_depth / 2;
1280 ni_ai_fifo_read(dev, s, n);
1287 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1289 struct ni_private *devpriv = dev->private;
1290 struct comedi_subdevice *s = dev->read_subdev;
1292 unsigned short data;
1293 unsigned short fifo_empty;
1296 if (devpriv->is_611x) {
1297 while ((ni_stc_readw(dev, AI_Status_1_Register) &
1298 AI_FIFO_Empty_St) == 0) {
1299 dl = ni_readl(dev, ADC_FIFO_Data_611x);
1301 /* This may get the hi/lo data in the wrong order */
1303 comedi_buf_write_samples(s, &data, 1);
1305 comedi_buf_write_samples(s, &data, 1);
1307 } else if (devpriv->is_6143) {
1309 while (ni_readl(dev, AIFIFO_Status_6143) & 0x04) {
1310 dl = ni_readl(dev, AIFIFO_Data_6143);
1312 /* This may get the hi/lo data in the wrong order */
1314 comedi_buf_write_samples(s, &data, 1);
1316 comedi_buf_write_samples(s, &data, 1);
1319 /* Check if stranded sample is present */
1320 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
1321 /* Get stranded sample into FIFO */
1322 ni_writel(dev, 0x01, AIFIFO_Control_6143);
1323 dl = ni_readl(dev, AIFIFO_Data_6143);
1324 data = (dl >> 16) & 0xffff;
1325 comedi_buf_write_samples(s, &data, 1);
1329 fifo_empty = ni_stc_readw(dev, AI_Status_1_Register) &
1331 while (fifo_empty == 0) {
1334 sizeof(devpriv->ai_fifo_buffer) /
1335 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1336 fifo_empty = ni_stc_readw(dev,
1337 AI_Status_1_Register) &
1341 devpriv->ai_fifo_buffer[i] =
1342 ni_readw(dev, ADC_FIFO_Data_Register);
1344 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1349 static void get_last_sample_611x(struct comedi_device *dev)
1351 struct ni_private *devpriv = dev->private;
1352 struct comedi_subdevice *s = dev->read_subdev;
1353 unsigned short data;
1356 if (!devpriv->is_611x)
1359 /* Check if there's a single sample stuck in the FIFO */
1360 if (ni_readb(dev, XXX_Status) & 0x80) {
1361 dl = ni_readl(dev, ADC_FIFO_Data_611x);
1363 comedi_buf_write_samples(s, &data, 1);
1367 static void get_last_sample_6143(struct comedi_device *dev)
1369 struct ni_private *devpriv = dev->private;
1370 struct comedi_subdevice *s = dev->read_subdev;
1371 unsigned short data;
1374 if (!devpriv->is_6143)
1377 /* Check if there's a single sample stuck in the FIFO */
1378 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
1379 /* Get stranded sample into FIFO */
1380 ni_writel(dev, 0x01, AIFIFO_Control_6143);
1381 dl = ni_readl(dev, AIFIFO_Data_6143);
1383 /* This may get the hi/lo data in the wrong order */
1384 data = (dl >> 16) & 0xffff;
1385 comedi_buf_write_samples(s, &data, 1);
1389 static void shutdown_ai_command(struct comedi_device *dev)
1391 struct comedi_subdevice *s = dev->read_subdev;
1394 ni_ai_drain_dma(dev);
1396 ni_handle_fifo_dregs(dev);
1397 get_last_sample_611x(dev);
1398 get_last_sample_6143(dev);
1400 s->async->events |= COMEDI_CB_EOA;
1403 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1405 struct ni_private *devpriv = dev->private;
1407 if (devpriv->aimode == AIMODE_SCAN) {
1409 static const int timeout = 10;
1412 for (i = 0; i < timeout; i++) {
1413 ni_sync_ai_dma(dev);
1414 if ((s->async->events & COMEDI_CB_EOS))
1419 ni_handle_fifo_dregs(dev);
1420 s->async->events |= COMEDI_CB_EOS;
1423 /* handle special case of single scan using AI_End_On_End_Of_Scan */
1424 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan))
1425 shutdown_ai_command(dev);
1428 static void handle_gpct_interrupt(struct comedi_device *dev,
1429 unsigned short counter_index)
1432 struct ni_private *devpriv = dev->private;
1433 struct comedi_subdevice *s;
1435 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1437 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1439 comedi_handle_events(dev, s);
1443 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1445 unsigned short ack = 0;
1447 if (a_status & AI_SC_TC_St)
1448 ack |= AI_SC_TC_Interrupt_Ack;
1449 if (a_status & AI_START1_St)
1450 ack |= AI_START1_Interrupt_Ack;
1451 if (a_status & AI_START_St)
1452 ack |= AI_START_Interrupt_Ack;
1453 if (a_status & AI_STOP_St)
1454 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1455 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */;
1457 ni_stc_writew(dev, ack, Interrupt_A_Ack_Register);
1460 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1461 unsigned ai_mite_status)
1463 struct comedi_subdevice *s = dev->read_subdev;
1464 struct comedi_cmd *cmd = &s->async->cmd;
1466 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1467 if (s->type == COMEDI_SUBD_UNUSED)
1471 if (ai_mite_status & CHSR_LINKC)
1472 ni_sync_ai_dma(dev);
1474 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1475 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1476 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1477 dev_err(dev->class_dev,
1478 "unknown mite interrupt (ai_mite_status=%08x)\n",
1480 s->async->events |= COMEDI_CB_ERROR;
1481 /* disable_irq(dev->irq); */
1485 /* test for all uncommon interrupt events at the same time */
1486 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1487 AI_SC_TC_St | AI_START1_St)) {
1488 if (status == 0xffff) {
1489 dev_err(dev->class_dev, "Card removed?\n");
1490 /* we probably aren't even running a command now,
1491 * so it's a good idea to be careful. */
1492 if (comedi_is_subdevice_running(s)) {
1493 s->async->events |= COMEDI_CB_ERROR;
1494 comedi_handle_events(dev, s);
1498 if (status & (AI_Overrun_St | AI_Overflow_St |
1499 AI_SC_TC_Error_St)) {
1500 dev_err(dev->class_dev, "ai error a_status=%04x\n",
1503 shutdown_ai_command(dev);
1505 s->async->events |= COMEDI_CB_ERROR;
1506 if (status & (AI_Overrun_St | AI_Overflow_St))
1507 s->async->events |= COMEDI_CB_OVERFLOW;
1509 comedi_handle_events(dev, s);
1512 if (status & AI_SC_TC_St) {
1513 if (cmd->stop_src == TRIG_COUNT)
1514 shutdown_ai_command(dev);
1518 if (status & AI_FIFO_Half_Full_St) {
1520 static const int timeout = 10;
1521 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1522 *fail to get the fifo less than half full, so loop to be sure.*/
1523 for (i = 0; i < timeout; ++i) {
1524 ni_handle_fifo_half_full(dev);
1525 if ((ni_stc_readw(dev, AI_Status_1_Register) &
1526 AI_FIFO_Half_Full_St) == 0)
1530 #endif /* !PCIDMA */
1532 if ((status & AI_STOP_St))
1533 ni_handle_eos(dev, s);
1535 comedi_handle_events(dev, s);
1538 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1540 unsigned short ack = 0;
1542 if (b_status & AO_BC_TC_St)
1543 ack |= AO_BC_TC_Interrupt_Ack;
1544 if (b_status & AO_Overrun_St)
1545 ack |= AO_Error_Interrupt_Ack;
1546 if (b_status & AO_START_St)
1547 ack |= AO_START_Interrupt_Ack;
1548 if (b_status & AO_START1_St)
1549 ack |= AO_START1_Interrupt_Ack;
1550 if (b_status & AO_UC_TC_St)
1551 ack |= AO_UC_TC_Interrupt_Ack;
1552 if (b_status & AO_UI2_TC_St)
1553 ack |= AO_UI2_TC_Interrupt_Ack;
1554 if (b_status & AO_UPDATE_St)
1555 ack |= AO_UPDATE_Interrupt_Ack;
1557 ni_stc_writew(dev, ack, Interrupt_B_Ack_Register);
1560 static void handle_b_interrupt(struct comedi_device *dev,
1561 unsigned short b_status, unsigned ao_mite_status)
1563 struct comedi_subdevice *s = dev->write_subdev;
1564 /* unsigned short ack=0; */
1567 /* Currently, mite.c requires us to handle LINKC */
1568 if (ao_mite_status & CHSR_LINKC) {
1569 struct ni_private *devpriv = dev->private;
1571 mite_handle_b_linkc(devpriv->mite, dev);
1574 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1575 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1576 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1577 dev_err(dev->class_dev,
1578 "unknown mite interrupt (ao_mite_status=%08x)\n",
1580 s->async->events |= COMEDI_CB_ERROR;
1584 if (b_status == 0xffff)
1586 if (b_status & AO_Overrun_St) {
1587 dev_err(dev->class_dev,
1588 "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1589 b_status, ni_stc_readw(dev, AO_Status_2_Register));
1590 s->async->events |= COMEDI_CB_OVERFLOW;
1593 if (b_status & AO_BC_TC_St)
1594 s->async->events |= COMEDI_CB_EOA;
1597 if (b_status & AO_FIFO_Request_St) {
1600 ret = ni_ao_fifo_half_empty(dev, s);
1602 dev_err(dev->class_dev, "AO buffer underrun\n");
1603 ni_set_bits(dev, Interrupt_B_Enable_Register,
1604 AO_FIFO_Interrupt_Enable |
1605 AO_Error_Interrupt_Enable, 0);
1606 s->async->events |= COMEDI_CB_OVERFLOW;
1611 comedi_handle_events(dev, s);
1614 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1615 void *data, unsigned int num_bytes,
1616 unsigned int chan_index)
1618 struct ni_private *devpriv = dev->private;
1619 struct comedi_async *async = s->async;
1620 struct comedi_cmd *cmd = &async->cmd;
1621 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1622 unsigned short *array = data;
1623 unsigned int *larray = data;
1626 for (i = 0; i < nsamples; i++) {
1628 if (s->subdev_flags & SDF_LSAMPL)
1629 larray[i] = le32_to_cpu(larray[i]);
1631 array[i] = le16_to_cpu(array[i]);
1633 if (s->subdev_flags & SDF_LSAMPL)
1634 larray[i] += devpriv->ai_offset[chan_index];
1636 array[i] += devpriv->ai_offset[chan_index];
1638 chan_index %= cmd->chanlist_len;
1644 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1646 struct ni_private *devpriv = dev->private;
1647 struct comedi_subdevice *s = dev->read_subdev;
1649 unsigned long flags;
1651 retval = ni_request_ai_mite_channel(dev);
1655 /* write alloc the entire buffer */
1656 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1658 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1659 if (!devpriv->ai_mite_chan) {
1660 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1664 if (devpriv->is_611x || devpriv->is_6143)
1665 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1666 else if (devpriv->is_628x)
1667 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1669 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1672 mite_dma_arm(devpriv->ai_mite_chan);
1673 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1678 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1680 struct ni_private *devpriv = dev->private;
1681 struct comedi_subdevice *s = dev->write_subdev;
1683 unsigned long flags;
1685 retval = ni_request_ao_mite_channel(dev);
1689 /* read alloc the entire buffer */
1690 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1692 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1693 if (devpriv->ao_mite_chan) {
1694 if (devpriv->is_611x || devpriv->is_6713) {
1695 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1697 /* doing 32 instead of 16 bit wide transfers from memory
1698 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1699 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1701 mite_dma_arm(devpriv->ao_mite_chan);
1705 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1713 used for both cancel ioctl and board initialization
1715 this is pretty harsh for a cancel, but it works...
1718 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1720 struct ni_private *devpriv = dev->private;
1722 ni_release_ai_mite_channel(dev);
1723 /* ai configuration */
1724 ni_stc_writew(dev, AI_Configuration_Start | AI_Reset,
1725 Joint_Reset_Register);
1727 ni_set_bits(dev, Interrupt_A_Enable_Register,
1728 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1729 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1730 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1731 AI_FIFO_Interrupt_Enable, 0);
1733 ni_clear_ai_fifo(dev);
1735 if (!devpriv->is_6143)
1736 ni_writeb(dev, 0, Misc_Command);
1738 ni_stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1739 ni_stc_writew(dev, AI_Start_Stop | AI_Mode_1_Reserved
1740 /*| AI_Trigger_Once */,
1741 AI_Mode_1_Register);
1742 ni_stc_writew(dev, 0x0000, AI_Mode_2_Register);
1743 /* generate FIFO interrupts on non-empty */
1744 ni_stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1745 if (devpriv->is_611x) {
1747 AI_SHIFTIN_Pulse_Width |
1749 AI_LOCALMUX_CLK_Pulse_Width,
1750 AI_Personal_Register);
1752 AI_SCAN_IN_PROG_Output_Select(3) |
1753 AI_EXTMUX_CLK_Output_Select(0) |
1754 AI_LOCALMUX_CLK_Output_Select(2) |
1755 AI_SC_TC_Output_Select(3) |
1756 AI_CONVERT_Output_Select
1757 (AI_CONVERT_Output_Enable_High),
1758 AI_Output_Control_Register);
1759 } else if (devpriv->is_6143) {
1760 ni_stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1762 AI_LOCALMUX_CLK_Pulse_Width,
1763 AI_Personal_Register);
1765 AI_SCAN_IN_PROG_Output_Select(3) |
1766 AI_EXTMUX_CLK_Output_Select(0) |
1767 AI_LOCALMUX_CLK_Output_Select(2) |
1768 AI_SC_TC_Output_Select(3) |
1769 AI_CONVERT_Output_Select
1770 (AI_CONVERT_Output_Enable_Low),
1771 AI_Output_Control_Register);
1773 unsigned ai_output_control_bits;
1776 AI_SHIFTIN_Pulse_Width |
1778 AI_CONVERT_Pulse_Width |
1779 AI_LOCALMUX_CLK_Pulse_Width,
1780 AI_Personal_Register);
1781 ai_output_control_bits =
1782 AI_SCAN_IN_PROG_Output_Select(3) |
1783 AI_EXTMUX_CLK_Output_Select(0) |
1784 AI_LOCALMUX_CLK_Output_Select(2) |
1785 AI_SC_TC_Output_Select(3);
1786 if (devpriv->is_622x)
1787 ai_output_control_bits |=
1788 AI_CONVERT_Output_Select
1789 (AI_CONVERT_Output_Enable_High);
1791 ai_output_control_bits |=
1792 AI_CONVERT_Output_Select
1793 (AI_CONVERT_Output_Enable_Low);
1794 ni_stc_writew(dev, ai_output_control_bits,
1795 AI_Output_Control_Register);
1797 /* the following registers should not be changed, because there
1798 * are no backup registers in devpriv. If you want to change
1799 * any of these, add a backup register and other appropriate code:
1800 * AI_Mode_1_Register
1801 * AI_Mode_3_Register
1802 * AI_Personal_Register
1803 * AI_Output_Control_Register
1806 AI_SC_TC_Error_Confirm |
1807 AI_START_Interrupt_Ack |
1808 AI_START2_Interrupt_Ack |
1809 AI_START1_Interrupt_Ack |
1810 AI_SC_TC_Interrupt_Ack |
1811 AI_Error_Interrupt_Ack |
1812 AI_STOP_Interrupt_Ack,
1813 Interrupt_A_Ack_Register); /* clear interrupts */
1815 ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1820 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1822 unsigned long flags;
1825 /* lock to avoid race with interrupt handler */
1826 spin_lock_irqsave(&dev->spinlock, flags);
1828 ni_handle_fifo_dregs(dev);
1830 ni_sync_ai_dma(dev);
1832 count = comedi_buf_n_bytes_ready(s);
1833 spin_unlock_irqrestore(&dev->spinlock, flags);
1838 static void ni_prime_channelgain_list(struct comedi_device *dev)
1842 ni_stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1843 for (i = 0; i < NI_TIMEOUT; ++i) {
1844 if (!(ni_stc_readw(dev, AI_Status_1_Register) &
1845 AI_FIFO_Empty_St)) {
1846 ni_stc_writew(dev, 1, ADC_FIFO_Clear);
1851 dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1854 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1855 unsigned int n_chan,
1858 const struct ni_board_struct *board = dev->board_ptr;
1859 struct ni_private *devpriv = dev->private;
1860 unsigned int chan, range, aref;
1862 unsigned int dither;
1863 unsigned range_code;
1865 ni_stc_writew(dev, 1, Configuration_Memory_Clear);
1867 if ((list[0] & CR_ALT_SOURCE)) {
1868 unsigned bypass_bits;
1870 chan = CR_CHAN(list[0]);
1871 range = CR_RANGE(list[0]);
1872 range_code = ni_gainlkup[board->gainlkup][range];
1873 dither = (list[0] & CR_ALT_FILTER) != 0;
1874 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1875 bypass_bits |= chan;
1877 (devpriv->ai_calib_source) &
1878 (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1879 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1880 MSeries_AI_Bypass_Mode_Mux_Mask |
1881 MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1882 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1884 bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1885 /* don't use 2's complement encoding */
1886 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1887 ni_writel(dev, bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1889 ni_writel(dev, 0, M_Offset_AI_Config_FIFO_Bypass);
1891 for (i = 0; i < n_chan; i++) {
1892 unsigned config_bits = 0;
1894 chan = CR_CHAN(list[i]);
1895 aref = CR_AREF(list[i]);
1896 range = CR_RANGE(list[i]);
1897 dither = (list[i] & CR_ALT_FILTER) != 0;
1899 range_code = ni_gainlkup[board->gainlkup][range];
1900 devpriv->ai_offset[i] = 0;
1904 MSeries_AI_Config_Channel_Type_Differential_Bits;
1908 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1912 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1917 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1919 MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
1920 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1921 if (i == n_chan - 1)
1922 config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1924 config_bits |= MSeries_AI_Config_Dither_Bit;
1925 /* don't use 2's complement encoding */
1926 config_bits |= MSeries_AI_Config_Polarity_Bit;
1927 ni_writew(dev, config_bits, M_Offset_AI_Config_FIFO_Data);
1929 ni_prime_channelgain_list(dev);
1933 * Notes on the 6110 and 6111:
1934 * These boards a slightly different than the rest of the series, since
1935 * they have multiple A/D converters.
1936 * From the driver side, the configuration memory is a
1938 * Configuration Memory Low:
1940 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1941 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1942 * 1001 gain=0.1 (+/- 50)
1951 * Configuration Memory High:
1952 * bits 12-14: Channel Type
1953 * 001 for differential
1954 * 000 for calibration
1955 * bit 11: coupling (this is not currently handled)
1959 * valid channels are 0-3
1961 static void ni_load_channelgain_list(struct comedi_device *dev,
1962 struct comedi_subdevice *s,
1963 unsigned int n_chan, unsigned int *list)
1965 const struct ni_board_struct *board = dev->board_ptr;
1966 struct ni_private *devpriv = dev->private;
1967 unsigned int offset = (s->maxdata + 1) >> 1;
1968 unsigned int chan, range, aref;
1970 unsigned int hi, lo;
1971 unsigned int dither;
1973 if (devpriv->is_m_series) {
1974 ni_m_series_load_channelgain_list(dev, n_chan, list);
1977 if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1978 if (devpriv->changain_state
1979 && devpriv->changain_spec == list[0]) {
1983 devpriv->changain_state = 1;
1984 devpriv->changain_spec = list[0];
1986 devpriv->changain_state = 0;
1989 ni_stc_writew(dev, 1, Configuration_Memory_Clear);
1991 /* Set up Calibration mode if required */
1992 if (devpriv->is_6143) {
1993 if ((list[0] & CR_ALT_SOURCE)
1994 && !devpriv->ai_calib_source_enabled) {
1995 /* Strobe Relay enable bit */
1996 ni_writew(dev, devpriv->ai_calib_source |
1997 Calibration_Channel_6143_RelayOn,
1998 Calibration_Channel_6143);
1999 ni_writew(dev, devpriv->ai_calib_source,
2000 Calibration_Channel_6143);
2001 devpriv->ai_calib_source_enabled = 1;
2002 msleep_interruptible(100); /* Allow relays to change */
2003 } else if (!(list[0] & CR_ALT_SOURCE)
2004 && devpriv->ai_calib_source_enabled) {
2005 /* Strobe Relay disable bit */
2006 ni_writew(dev, devpriv->ai_calib_source |
2007 Calibration_Channel_6143_RelayOff,
2008 Calibration_Channel_6143);
2009 ni_writew(dev, devpriv->ai_calib_source,
2010 Calibration_Channel_6143);
2011 devpriv->ai_calib_source_enabled = 0;
2012 msleep_interruptible(100); /* Allow relays to change */
2016 for (i = 0; i < n_chan; i++) {
2017 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
2018 chan = devpriv->ai_calib_source;
2020 chan = CR_CHAN(list[i]);
2021 aref = CR_AREF(list[i]);
2022 range = CR_RANGE(list[i]);
2023 dither = (list[i] & CR_ALT_FILTER) != 0;
2025 /* fix the external/internal range differences */
2026 range = ni_gainlkup[board->gainlkup][range];
2027 if (devpriv->is_611x)
2028 devpriv->ai_offset[i] = offset;
2030 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2033 if ((list[i] & CR_ALT_SOURCE)) {
2034 if (devpriv->is_611x)
2035 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
2036 Calibration_Channel_Select_611x);
2038 if (devpriv->is_611x)
2040 else if (devpriv->is_6143)
2044 hi |= AI_DIFFERENTIAL;
2056 hi |= AI_CONFIG_CHANNEL(chan);
2058 ni_writew(dev, hi, Configuration_Memory_High);
2060 if (!devpriv->is_6143) {
2062 if (i == n_chan - 1)
2063 lo |= AI_LAST_CHANNEL;
2067 ni_writew(dev, lo, Configuration_Memory_Low);
2071 /* prime the channel/gain list */
2072 if (!devpriv->is_611x && !devpriv->is_6143)
2073 ni_prime_channelgain_list(dev);
2076 static int ni_ai_insn_read(struct comedi_device *dev,
2077 struct comedi_subdevice *s,
2078 struct comedi_insn *insn,
2081 struct ni_private *devpriv = dev->private;
2082 unsigned int mask = (s->maxdata + 1) >> 1;
2088 ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
2090 ni_clear_ai_fifo(dev);
2092 signbits = devpriv->ai_offset[0];
2093 if (devpriv->is_611x) {
2094 for (n = 0; n < num_adc_stages_611x; n++) {
2095 ni_stc_writew(dev, AI_CONVERT_Pulse,
2096 AI_Command_1_Register);
2099 for (n = 0; n < insn->n; n++) {
2100 ni_stc_writew(dev, AI_CONVERT_Pulse,
2101 AI_Command_1_Register);
2102 /* The 611x has screwy 32-bit FIFOs. */
2104 for (i = 0; i < NI_TIMEOUT; i++) {
2105 if (ni_readb(dev, XXX_Status) & 0x80) {
2106 d = ni_readl(dev, ADC_FIFO_Data_611x);
2111 if (!(ni_stc_readw(dev, AI_Status_1_Register) &
2112 AI_FIFO_Empty_St)) {
2113 d = ni_readl(dev, ADC_FIFO_Data_611x);
2118 if (i == NI_TIMEOUT) {
2119 dev_err(dev->class_dev, "timeout\n");
2125 } else if (devpriv->is_6143) {
2126 for (n = 0; n < insn->n; n++) {
2127 ni_stc_writew(dev, AI_CONVERT_Pulse,
2128 AI_Command_1_Register);
2130 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
2132 for (i = 0; i < NI_TIMEOUT; i++) {
2133 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
2134 /* Get stranded sample into FIFO */
2135 ni_writel(dev, 0x01,
2136 AIFIFO_Control_6143);
2137 dl = ni_readl(dev, AIFIFO_Data_6143);
2141 if (i == NI_TIMEOUT) {
2142 dev_err(dev->class_dev, "timeout\n");
2145 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
2148 for (n = 0; n < insn->n; n++) {
2149 ni_stc_writew(dev, AI_CONVERT_Pulse,
2150 AI_Command_1_Register);
2151 for (i = 0; i < NI_TIMEOUT; i++) {
2152 if (!(ni_stc_readw(dev, AI_Status_1_Register) &
2156 if (i == NI_TIMEOUT) {
2157 dev_err(dev->class_dev, "timeout\n");
2160 if (devpriv->is_m_series) {
2161 dl = ni_readl(dev, M_Offset_AI_FIFO_Data);
2165 d = ni_readw(dev, ADC_FIFO_Data_Register);
2166 d += signbits; /* subtle: needs to be short addition */
2174 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2177 struct ni_private *devpriv = dev->private;
2180 switch (flags & CMDF_ROUND_MASK) {
2181 case CMDF_ROUND_NEAREST:
2183 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2185 case CMDF_ROUND_DOWN:
2186 divider = (nanosec) / devpriv->clock_ns;
2189 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2195 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2197 struct ni_private *devpriv = dev->private;
2199 return devpriv->clock_ns * (timer + 1);
2202 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2203 unsigned num_channels)
2205 const struct ni_board_struct *board = dev->board_ptr;
2206 struct ni_private *devpriv = dev->private;
2208 /* simultaneously-sampled inputs */
2209 if (devpriv->is_611x || devpriv->is_6143)
2210 return board->ai_speed;
2212 /* multiplexed inputs */
2213 return board->ai_speed * num_channels;
2216 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2217 struct comedi_cmd *cmd)
2219 const struct ni_board_struct *board = dev->board_ptr;
2220 struct ni_private *devpriv = dev->private;
2223 unsigned int sources;
2225 /* Step 1 : check if triggers are trivially valid */
2227 err |= comedi_check_trigger_src(&cmd->start_src,
2228 TRIG_NOW | TRIG_INT | TRIG_EXT);
2229 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2230 TRIG_TIMER | TRIG_EXT);
2232 sources = TRIG_TIMER | TRIG_EXT;
2233 if (devpriv->is_611x || devpriv->is_6143)
2234 sources |= TRIG_NOW;
2235 err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2237 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2238 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2243 /* Step 2a : make sure trigger sources are unique */
2245 err |= comedi_check_trigger_is_unique(cmd->start_src);
2246 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2247 err |= comedi_check_trigger_is_unique(cmd->convert_src);
2248 err |= comedi_check_trigger_is_unique(cmd->stop_src);
2250 /* Step 2b : and mutually compatible */
2255 /* Step 3: check if arguments are trivially valid */
2257 switch (cmd->start_src) {
2260 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2263 tmp = CR_CHAN(cmd->start_arg);
2267 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2268 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2272 if (cmd->scan_begin_src == TRIG_TIMER) {
2273 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2274 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2275 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2278 } else if (cmd->scan_begin_src == TRIG_EXT) {
2279 /* external trigger */
2280 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2284 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2285 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2286 } else { /* TRIG_OTHER */
2287 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2290 if (cmd->convert_src == TRIG_TIMER) {
2291 if (devpriv->is_611x || devpriv->is_6143) {
2292 err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2295 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2297 err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2301 } else if (cmd->convert_src == TRIG_EXT) {
2302 /* external trigger */
2303 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2307 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2308 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2309 } else if (cmd->convert_src == TRIG_NOW) {
2310 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2313 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2316 if (cmd->stop_src == TRIG_COUNT) {
2317 unsigned int max_count = 0x01000000;
2319 if (devpriv->is_611x)
2320 max_count -= num_adc_stages_611x;
2321 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2322 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2325 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2331 /* step 4: fix up any arguments */
2333 if (cmd->scan_begin_src == TRIG_TIMER) {
2334 tmp = cmd->scan_begin_arg;
2335 cmd->scan_begin_arg =
2336 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2337 cmd->scan_begin_arg,
2339 if (tmp != cmd->scan_begin_arg)
2342 if (cmd->convert_src == TRIG_TIMER) {
2343 if (!devpriv->is_611x && !devpriv->is_6143) {
2344 tmp = cmd->convert_arg;
2346 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2349 if (tmp != cmd->convert_arg)
2351 if (cmd->scan_begin_src == TRIG_TIMER &&
2352 cmd->scan_begin_arg <
2353 cmd->convert_arg * cmd->scan_end_arg) {
2354 cmd->scan_begin_arg =
2355 cmd->convert_arg * cmd->scan_end_arg;
2367 static int ni_ai_inttrig(struct comedi_device *dev,
2368 struct comedi_subdevice *s,
2369 unsigned int trig_num)
2371 struct ni_private *devpriv = dev->private;
2372 struct comedi_cmd *cmd = &s->async->cmd;
2374 if (trig_num != cmd->start_arg)
2377 ni_stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2378 AI_Command_2_Register);
2379 s->async->inttrig = NULL;
2384 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2386 struct ni_private *devpriv = dev->private;
2387 const struct comedi_cmd *cmd = &s->async->cmd;
2389 int mode1 = 0; /* mode1 is needed for both stop and convert */
2391 int start_stop_select = 0;
2392 unsigned int stop_count;
2393 int interrupt_a_enable = 0;
2395 if (dev->irq == 0) {
2396 dev_err(dev->class_dev, "cannot run command without an irq\n");
2399 ni_clear_ai_fifo(dev);
2401 ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2403 /* start configuration */
2404 ni_stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2406 /* disable analog triggering for now, since it
2407 * interferes with the use of pfi0 */
2408 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2409 ni_stc_writew(dev, devpriv->an_trig_etc_reg,
2410 Analog_Trigger_Etc_Register);
2412 switch (cmd->start_src) {
2416 AI_START2_Select(0) |
2417 AI_START1_Sync | AI_START1_Edge |
2418 AI_START1_Select(0),
2419 AI_Trigger_Select_Register);
2423 int chan = CR_CHAN(cmd->start_arg);
2424 unsigned int bits = AI_START2_Select(0) |
2425 AI_START1_Sync | AI_START1_Select(chan + 1);
2427 if (cmd->start_arg & CR_INVERT)
2428 bits |= AI_START1_Polarity;
2429 if (cmd->start_arg & CR_EDGE)
2430 bits |= AI_START1_Edge;
2431 ni_stc_writew(dev, bits, AI_Trigger_Select_Register);
2436 mode2 &= ~AI_Pre_Trigger;
2437 mode2 &= ~AI_SC_Initial_Load_Source;
2438 mode2 &= ~AI_SC_Reload_Mode;
2439 ni_stc_writew(dev, mode2, AI_Mode_2_Register);
2441 if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2442 start_stop_select |= AI_STOP_Polarity;
2443 start_stop_select |= AI_STOP_Select(31); /* logic low */
2444 start_stop_select |= AI_STOP_Sync;
2446 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */
2448 ni_stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2450 devpriv->ai_cmd2 = 0;
2451 switch (cmd->stop_src) {
2453 stop_count = cmd->stop_arg - 1;
2455 if (devpriv->is_611x) {
2456 /* have to take 3 stage adc pipeline into account */
2457 stop_count += num_adc_stages_611x;
2459 /* stage number of scans */
2460 ni_stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2462 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2463 ni_stc_writew(dev, mode1, AI_Mode_1_Register);
2464 /* load SC (Scan Count) */
2465 ni_stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2467 if (stop_count == 0) {
2468 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2469 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2470 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2471 if (cmd->chanlist_len > 1)
2472 start_stop_select |=
2473 AI_STOP_Polarity | AI_STOP_Edge;
2477 /* stage number of scans */
2478 ni_stc_writel(dev, 0, AI_SC_Load_A_Registers);
2480 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2481 ni_stc_writew(dev, mode1, AI_Mode_1_Register);
2483 /* load SC (Scan Count) */
2484 ni_stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2488 switch (cmd->scan_begin_src) {
2491 stop bits for non 611x boards
2492 AI_SI_Special_Trigger_Delay=0
2494 AI_START_STOP_Select_Register:
2495 AI_START_Polarity=0 (?) rising edge
2496 AI_START_Edge=1 edge triggered
2498 AI_START_Select=0 SI_TC
2499 AI_STOP_Polarity=0 rising edge
2500 AI_STOP_Edge=0 level
2502 AI_STOP_Select=19 external pin (configuration mem)
2504 start_stop_select |= AI_START_Edge | AI_START_Sync;
2505 ni_stc_writew(dev, start_stop_select,
2506 AI_START_STOP_Select_Register);
2508 mode2 |= AI_SI_Reload_Mode(0);
2509 /* AI_SI_Initial_Load_Source=A */
2510 mode2 &= ~AI_SI_Initial_Load_Source;
2511 /* mode2 |= AI_SC_Reload_Mode; */
2512 ni_stc_writew(dev, mode2, AI_Mode_2_Register);
2515 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2516 CMDF_ROUND_NEAREST);
2517 ni_stc_writel(dev, timer, AI_SI_Load_A_Registers);
2518 ni_stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2521 if (cmd->scan_begin_arg & CR_EDGE)
2522 start_stop_select |= AI_START_Edge;
2523 /* AI_START_Polarity==1 is falling edge */
2524 if (cmd->scan_begin_arg & CR_INVERT)
2525 start_stop_select |= AI_START_Polarity;
2526 if (cmd->scan_begin_src != cmd->convert_src ||
2527 (cmd->scan_begin_arg & ~CR_EDGE) !=
2528 (cmd->convert_arg & ~CR_EDGE))
2529 start_stop_select |= AI_START_Sync;
2530 start_stop_select |=
2531 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2532 ni_stc_writew(dev, start_stop_select,
2533 AI_START_STOP_Select_Register);
2537 switch (cmd->convert_src) {
2540 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2543 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2544 CMDF_ROUND_NEAREST);
2545 /* 0,0 does not work */
2546 ni_stc_writew(dev, 1, AI_SI2_Load_A_Register);
2547 ni_stc_writew(dev, timer, AI_SI2_Load_B_Register);
2549 /* AI_SI2_Reload_Mode = alternate */
2550 /* AI_SI2_Initial_Load_Source = A */
2551 mode2 &= ~AI_SI2_Initial_Load_Source;
2552 mode2 |= AI_SI2_Reload_Mode;
2553 ni_stc_writew(dev, mode2, AI_Mode_2_Register);
2556 ni_stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2558 mode2 |= AI_SI2_Reload_Mode; /* alternate */
2559 mode2 |= AI_SI2_Initial_Load_Source; /* B */
2561 ni_stc_writew(dev, mode2, AI_Mode_2_Register);
2564 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2565 if ((cmd->convert_arg & CR_INVERT) == 0)
2566 mode1 |= AI_CONVERT_Source_Polarity;
2567 ni_stc_writew(dev, mode1, AI_Mode_1_Register);
2569 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2570 ni_stc_writew(dev, mode2, AI_Mode_2_Register);
2576 /* interrupt on FIFO, errors, SC_TC */
2577 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2578 AI_SC_TC_Interrupt_Enable;
2581 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2584 if (cmd->flags & CMDF_WAKE_EOS
2585 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2586 /* wake on end-of-scan */
2587 devpriv->aimode = AIMODE_SCAN;
2589 devpriv->aimode = AIMODE_HALF_FULL;
2592 switch (devpriv->aimode) {
2593 case AIMODE_HALF_FULL:
2594 /*generate FIFO interrupts and DMA requests on half-full */
2596 ni_stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2597 AI_Mode_3_Register);
2599 ni_stc_writew(dev, AI_FIFO_Mode_HF,
2600 AI_Mode_3_Register);
2604 /*generate FIFO interrupts on non-empty */
2605 ni_stc_writew(dev, AI_FIFO_Mode_NE,
2606 AI_Mode_3_Register);
2610 ni_stc_writew(dev, AI_FIFO_Mode_NE,
2611 AI_Mode_3_Register);
2613 ni_stc_writew(dev, AI_FIFO_Mode_HF,
2614 AI_Mode_3_Register);
2616 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2622 /* clear interrupts */
2624 AI_Error_Interrupt_Ack |
2625 AI_STOP_Interrupt_Ack |
2626 AI_START_Interrupt_Ack |
2627 AI_START2_Interrupt_Ack |
2628 AI_START1_Interrupt_Ack |
2629 AI_SC_TC_Interrupt_Ack |
2630 AI_SC_TC_Error_Confirm,
2631 Interrupt_A_Ack_Register);
2633 ni_set_bits(dev, Interrupt_A_Enable_Register,
2634 interrupt_a_enable, 1);
2636 /* interrupt on nothing */
2637 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2639 /* XXX start polling if necessary */
2642 /* end configuration */
2643 ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2645 switch (cmd->scan_begin_src) {
2648 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2649 AI_Command_1_Register);
2652 /* XXX AI_SI_Arm? */
2654 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2655 AI_Command_1_Register);
2661 int retval = ni_ai_setup_MITE_dma(dev);
2668 if (cmd->start_src == TRIG_NOW) {
2669 /* AI_START1_Pulse */
2670 ni_stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2671 AI_Command_2_Register);
2672 s->async->inttrig = NULL;
2673 } else if (cmd->start_src == TRIG_EXT) {
2674 s->async->inttrig = NULL;
2675 } else { /* TRIG_INT */
2676 s->async->inttrig = ni_ai_inttrig;
2682 static int ni_ai_insn_config(struct comedi_device *dev,
2683 struct comedi_subdevice *s,
2684 struct comedi_insn *insn, unsigned int *data)
2686 struct ni_private *devpriv = dev->private;
2692 case INSN_CONFIG_ALT_SOURCE:
2693 if (devpriv->is_m_series) {
2694 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2695 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2696 MSeries_AI_Bypass_Mode_Mux_Mask |
2697 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2700 devpriv->ai_calib_source = data[1];
2701 } else if (devpriv->is_6143) {
2702 unsigned int calib_source;
2704 calib_source = data[1] & 0xf;
2706 devpriv->ai_calib_source = calib_source;
2707 ni_writew(dev, calib_source, Calibration_Channel_6143);
2709 unsigned int calib_source;
2710 unsigned int calib_source_adjust;
2712 calib_source = data[1] & 0xf;
2713 calib_source_adjust = (data[1] >> 4) & 0xff;
2715 if (calib_source >= 8)
2717 devpriv->ai_calib_source = calib_source;
2718 if (devpriv->is_611x) {
2719 ni_writeb(dev, calib_source_adjust,
2720 Cal_Gain_Select_611x);
2731 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2732 void *data, unsigned int num_bytes,
2733 unsigned int chan_index)
2735 struct comedi_cmd *cmd = &s->async->cmd;
2736 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2737 unsigned short *array = data;
2740 for (i = 0; i < nsamples; i++) {
2741 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2742 unsigned short val = array[i];
2745 * Munge data from unsigned to two's complement for
2748 if (comedi_range_is_bipolar(s, range))
2749 val = comedi_offset_munge(s, val);
2751 val = cpu_to_le16(val);
2756 chan_index %= cmd->chanlist_len;
2760 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2761 struct comedi_subdevice *s,
2762 unsigned int chanspec[],
2763 unsigned int n_chans, int timed)
2765 struct ni_private *devpriv = dev->private;
2773 for (i = 0; i < s->n_chan; ++i) {
2774 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2775 ni_writeb(dev, devpriv->ao_conf[i],
2776 M_Offset_AO_Config_Bank(i));
2777 ni_writeb(dev, 0xf, M_Offset_AO_Waveform_Order(i));
2780 for (i = 0; i < n_chans; i++) {
2781 const struct comedi_krange *krange;
2783 chan = CR_CHAN(chanspec[i]);
2784 range = CR_RANGE(chanspec[i]);
2785 krange = s->range_table->range + range;
2788 switch (krange->max - krange->min) {
2790 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2792 M_Offset_AO_Reference_Attenuation(chan));
2795 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2797 M_Offset_AO_Reference_Attenuation(chan));
2800 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2801 ni_writeb(dev, MSeries_Attenuate_x5_Bit,
2802 M_Offset_AO_Reference_Attenuation(chan));
2805 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2806 ni_writeb(dev, MSeries_Attenuate_x5_Bit,
2807 M_Offset_AO_Reference_Attenuation(chan));
2810 dev_err(dev->class_dev,
2811 "bug! unhandled ao reference voltage\n");
2814 switch (krange->max + krange->min) {
2816 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2819 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2822 dev_err(dev->class_dev,
2823 "bug! unhandled ao offset voltage\n");
2827 conf |= MSeries_AO_Update_Timed_Bit;
2828 ni_writeb(dev, conf, M_Offset_AO_Config_Bank(chan));
2829 devpriv->ao_conf[chan] = conf;
2830 ni_writeb(dev, i, M_Offset_AO_Waveform_Order(chan));
2835 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2836 struct comedi_subdevice *s,
2837 unsigned int chanspec[],
2838 unsigned int n_chans)
2840 struct ni_private *devpriv = dev->private;
2847 for (i = 0; i < n_chans; i++) {
2848 chan = CR_CHAN(chanspec[i]);
2849 range = CR_RANGE(chanspec[i]);
2850 conf = AO_Channel(chan);
2852 if (comedi_range_is_bipolar(s, range)) {
2854 invert = (s->maxdata + 1) >> 1;
2858 if (comedi_range_is_external(s, range))
2861 /* not all boards can deglitch, but this shouldn't hurt */
2862 if (chanspec[i] & CR_DEGLITCH)
2863 conf |= AO_Deglitch;
2865 /* analog reference */
2866 /* AREF_OTHER connects AO ground to AI ground, i think */
2867 conf |= (CR_AREF(chanspec[i]) ==
2868 AREF_OTHER) ? AO_Ground_Ref : 0;
2870 ni_writew(dev, conf, AO_Configuration);
2871 devpriv->ao_conf[chan] = conf;
2876 static int ni_ao_config_chanlist(struct comedi_device *dev,
2877 struct comedi_subdevice *s,
2878 unsigned int chanspec[], unsigned int n_chans,
2881 struct ni_private *devpriv = dev->private;
2883 if (devpriv->is_m_series)
2884 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2887 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2890 static int ni_ao_insn_write(struct comedi_device *dev,
2891 struct comedi_subdevice *s,
2892 struct comedi_insn *insn,
2895 struct ni_private *devpriv = dev->private;
2896 unsigned int chan = CR_CHAN(insn->chanspec);
2897 unsigned int range = CR_RANGE(insn->chanspec);
2901 if (devpriv->is_6xxx) {
2902 ni_ao_win_outw(dev, 1 << chan, AO_Immediate_671x);
2904 reg = DACx_Direct_Data_671x(chan);
2905 } else if (devpriv->is_m_series) {
2906 reg = M_Offset_DAC_Direct_Data(chan);
2908 reg = (chan) ? DAC1_Direct_Data : DAC0_Direct_Data;
2911 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2913 for (i = 0; i < insn->n; i++) {
2914 unsigned int val = data[i];
2916 s->readback[chan] = val;
2918 if (devpriv->is_6xxx) {
2920 * 6xxx boards have bipolar outputs, munge the
2921 * unsigned comedi values to 2's complement
2923 val = comedi_offset_munge(s, val);
2925 ni_ao_win_outw(dev, val, reg);
2926 } else if (devpriv->is_m_series) {
2928 * M-series boards use offset binary values for
2929 * bipolar and uinpolar outputs
2931 ni_writew(dev, val, reg);
2934 * Non-M series boards need two's complement values
2935 * for bipolar ranges.
2937 if (comedi_range_is_bipolar(s, range))
2938 val = comedi_offset_munge(s, val);
2940 ni_writew(dev, val, reg);
2947 static int ni_ao_insn_config(struct comedi_device *dev,
2948 struct comedi_subdevice *s,
2949 struct comedi_insn *insn, unsigned int *data)
2951 const struct ni_board_struct *board = dev->board_ptr;
2952 struct ni_private *devpriv = dev->private;
2953 unsigned int nbytes;
2956 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2959 nbytes = comedi_samples_to_bytes(s,
2960 board->ao_fifo_depth);
2961 data[2] = 1 + nbytes;
2963 data[2] += devpriv->mite->fifo_size;
2979 static int ni_ao_inttrig(struct comedi_device *dev,
2980 struct comedi_subdevice *s,
2981 unsigned int trig_num)
2983 struct ni_private *devpriv = dev->private;
2984 struct comedi_cmd *cmd = &s->async->cmd;
2986 int interrupt_b_bits;
2988 static const int timeout = 1000;
2990 if (trig_num != cmd->start_arg)
2993 /* Null trig at beginning prevent ao start trigger from executing more than
2994 once per command (and doing things like trying to allocate the ao dma channel
2996 s->async->inttrig = NULL;
2998 ni_set_bits(dev, Interrupt_B_Enable_Register,
2999 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3000 interrupt_b_bits = AO_Error_Interrupt_Enable;
3002 ni_stc_writew(dev, 1, DAC_FIFO_Clear);
3003 if (devpriv->is_6xxx)
3004 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3005 ret = ni_ao_setup_MITE_dma(dev);
3008 ret = ni_ao_wait_for_dma_load(dev);
3012 ret = ni_ao_prep_fifo(dev, s);
3016 interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3019 ni_stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3020 AO_Mode_3_Register);
3021 ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3022 /* wait for DACs to be loaded */
3023 for (i = 0; i < timeout; i++) {
3025 if ((ni_stc_readw(dev, Joint_Status_2_Register) &
3026 AO_TMRDACWRs_In_Progress_St) == 0)
3030 dev_err(dev->class_dev,
3031 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
3035 * stc manual says we are need to clear error interrupt after
3036 * AO_TMRDACWRs_In_Progress_St clears
3038 ni_stc_writew(dev, AO_Error_Interrupt_Ack, Interrupt_B_Ack_Register);
3040 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3042 ni_stc_writew(dev, devpriv->ao_cmd1 |
3043 AO_UI_Arm | AO_UC_Arm | AO_BC_Arm |
3044 AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3045 AO_Command_1_Register);
3047 ni_stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3048 AO_Command_2_Register);
3053 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3055 const struct ni_board_struct *board = dev->board_ptr;
3056 struct ni_private *devpriv = dev->private;
3057 const struct comedi_cmd *cmd = &s->async->cmd;
3062 if (dev->irq == 0) {
3063 dev_err(dev->class_dev, "cannot run command without an irq\n");
3067 ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3069 ni_stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3071 if (devpriv->is_6xxx) {
3072 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
3075 for (i = 0; i < cmd->chanlist_len; i++) {
3078 chan = CR_CHAN(cmd->chanlist[i]);
3080 ni_ao_win_outw(dev, chan, AO_Waveform_Generation_611x);
3082 ni_ao_win_outw(dev, bits, AO_Timed_611x);
3085 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3087 if (cmd->stop_src == TRIG_NONE) {
3088 devpriv->ao_mode1 |= AO_Continuous;
3089 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3091 devpriv->ao_mode1 &= ~AO_Continuous;
3092 devpriv->ao_mode1 |= AO_Trigger_Once;
3094 ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3095 switch (cmd->start_src) {
3098 devpriv->ao_trigger_select &=
3099 ~(AO_START1_Polarity | AO_START1_Select(-1));
3100 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3101 ni_stc_writew(dev, devpriv->ao_trigger_select,
3102 AO_Trigger_Select_Register);
3105 devpriv->ao_trigger_select =
3106 AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3107 if (cmd->start_arg & CR_INVERT)
3108 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
3109 if (cmd->start_arg & CR_EDGE)
3110 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */
3111 ni_stc_writew(dev, devpriv->ao_trigger_select,
3112 AO_Trigger_Select_Register);
3118 devpriv->ao_mode3 &= ~AO_Trigger_Length;
3119 ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3121 ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3122 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3123 ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3124 if (cmd->stop_src == TRIG_NONE)
3125 ni_stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3127 ni_stc_writel(dev, 0, AO_BC_Load_A_Register);
3128 ni_stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3129 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3130 ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3131 switch (cmd->stop_src) {
3133 if (devpriv->is_m_series) {
3134 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
3135 ni_stc_writel(dev, cmd->stop_arg - 1,
3136 AO_UC_Load_A_Register);
3137 ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3139 ni_stc_writel(dev, cmd->stop_arg,
3140 AO_UC_Load_A_Register);
3141 ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3142 ni_stc_writel(dev, cmd->stop_arg - 1,
3143 AO_UC_Load_A_Register);
3147 ni_stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3148 ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3149 ni_stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3152 ni_stc_writel(dev, 0, AO_UC_Load_A_Register);
3153 ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3154 ni_stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3157 devpriv->ao_mode1 &=
3158 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3159 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3160 switch (cmd->scan_begin_src) {
3162 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3164 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3165 CMDF_ROUND_NEAREST);
3166 ni_stc_writel(dev, 1, AO_UI_Load_A_Register);
3167 ni_stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3168 ni_stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3171 devpriv->ao_mode1 |=
3172 AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3173 if (cmd->scan_begin_arg & CR_INVERT)
3174 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3175 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3181 ni_stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3182 ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3183 devpriv->ao_mode2 &=
3184 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3185 ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3187 if (cmd->scan_end_arg > 1) {
3188 devpriv->ao_mode1 |= AO_Multiple_Channels;
3190 AO_Number_Of_Channels(cmd->scan_end_arg - 1) |
3191 AO_UPDATE_Output_Select(AO_Update_Output_High_Z),
3192 AO_Output_Control_Register);
3196 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3197 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3198 if (devpriv->is_m_series || devpriv->is_6xxx) {
3199 bits |= AO_Number_Of_Channels(0);
3202 AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3204 ni_stc_writew(dev, bits, AO_Output_Control_Register);
3206 ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3208 ni_stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3209 AO_Command_1_Register);
3211 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3212 ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3214 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3216 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3218 devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3220 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3221 ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3223 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3224 AO_TMRDACWR_Pulse_Width;
3225 if (board->ao_fifo_depth)
3226 bits |= AO_FIFO_Enable;
3228 bits |= AO_DMA_PIO_Control;
3230 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3231 verified with bus analyzer. */
3232 if (devpriv->is_m_series)
3233 bits |= AO_Number_Of_DAC_Packages;
3235 ni_stc_writew(dev, bits, AO_Personal_Register);
3236 /* enable sending of ao dma requests */
3237 ni_stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3239 ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3241 if (cmd->stop_src == TRIG_COUNT) {
3242 ni_stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3243 Interrupt_B_Ack_Register);
3244 ni_set_bits(dev, Interrupt_B_Enable_Register,
3245 AO_BC_TC_Interrupt_Enable, 1);
3248 s->async->inttrig = ni_ao_inttrig;
3253 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3254 struct comedi_cmd *cmd)
3256 const struct ni_board_struct *board = dev->board_ptr;
3257 struct ni_private *devpriv = dev->private;
3261 /* Step 1 : check if triggers are trivially valid */
3263 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3264 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3265 TRIG_TIMER | TRIG_EXT);
3266 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3267 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3268 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3273 /* Step 2a : make sure trigger sources are unique */
3275 err |= comedi_check_trigger_is_unique(cmd->start_src);
3276 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3277 err |= comedi_check_trigger_is_unique(cmd->stop_src);
3279 /* Step 2b : and mutually compatible */
3284 /* Step 3: check if arguments are trivially valid */
3286 switch (cmd->start_src) {
3288 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3291 tmp = CR_CHAN(cmd->start_arg);
3295 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3296 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3300 if (cmd->scan_begin_src == TRIG_TIMER) {
3301 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3303 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3308 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3309 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3312 if (cmd->stop_src == TRIG_COUNT)
3313 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3314 else /* TRIG_NONE */
3315 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3320 /* step 4: fix up any arguments */
3321 if (cmd->scan_begin_src == TRIG_TIMER) {
3322 tmp = cmd->scan_begin_arg;
3323 cmd->scan_begin_arg =
3324 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3325 cmd->scan_begin_arg,
3327 if (tmp != cmd->scan_begin_arg)
3336 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3338 struct ni_private *devpriv = dev->private;
3340 ni_release_ao_mite_channel(dev);
3342 ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3343 ni_stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3344 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3345 ni_stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3346 ni_stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3347 ni_stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3348 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3349 ni_stc_writew(dev, 0, AO_Output_Control_Register);
3350 ni_stc_writew(dev, 0, AO_Start_Select_Register);
3351 devpriv->ao_cmd1 = 0;
3352 ni_stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3353 devpriv->ao_cmd2 = 0;
3354 ni_stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3355 devpriv->ao_mode1 = 0;
3356 ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3357 devpriv->ao_mode2 = 0;
3358 ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3359 if (devpriv->is_m_series)
3360 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3362 devpriv->ao_mode3 = 0;
3363 ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3364 devpriv->ao_trigger_select = 0;
3365 ni_stc_writew(dev, devpriv->ao_trigger_select,
3366 AO_Trigger_Select_Register);
3367 if (devpriv->is_6xxx) {
3368 unsigned immediate_bits = 0;
3371 for (i = 0; i < s->n_chan; ++i)
3372 immediate_bits |= 1 << i;
3373 ni_ao_win_outw(dev, immediate_bits, AO_Immediate_671x);
3374 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
3376 ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3383 static int ni_dio_insn_config(struct comedi_device *dev,
3384 struct comedi_subdevice *s,
3385 struct comedi_insn *insn,
3388 struct ni_private *devpriv = dev->private;
3391 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3395 devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3396 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3397 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3402 static int ni_dio_insn_bits(struct comedi_device *dev,
3403 struct comedi_subdevice *s,
3404 struct comedi_insn *insn,
3407 struct ni_private *devpriv = dev->private;
3409 /* Make sure we're not using the serial part of the dio */
3410 if ((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
3413 if (comedi_dio_update_state(s, data)) {
3414 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3415 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3416 ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3419 data[1] = ni_stc_readw(dev, DIO_Parallel_Input_Register);
3424 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3425 struct comedi_subdevice *s,
3426 struct comedi_insn *insn,
3431 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3435 ni_writel(dev, s->io_bits, M_Offset_DIO_Direction);
3440 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3441 struct comedi_subdevice *s,
3442 struct comedi_insn *insn,
3445 if (comedi_dio_update_state(s, data))
3446 ni_writel(dev, s->state, M_Offset_Static_Digital_Output);
3448 data[1] = ni_readl(dev, M_Offset_Static_Digital_Input);
3453 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3454 struct comedi_subdevice *s,
3455 struct comedi_cmd *cmd)
3459 for (i = 0; i < cmd->chanlist_len; ++i) {
3460 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3469 static int ni_cdio_cmdtest(struct comedi_device *dev,
3470 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3475 /* Step 1 : check if triggers are trivially valid */
3477 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3478 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3479 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3480 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3481 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3486 /* Step 2a : make sure trigger sources are unique */
3487 /* Step 2b : and mutually compatible */
3489 /* Step 3: check if arguments are trivially valid */
3491 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3493 tmp = cmd->scan_begin_arg;
3494 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3495 if (tmp != cmd->scan_begin_arg)
3498 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3499 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3501 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3506 /* Step 4: fix up any arguments */
3508 /* Step 5: check channel list if it exists */
3510 if (cmd->chanlist && cmd->chanlist_len > 0)
3511 err |= ni_cdio_check_chanlist(dev, s, cmd);
3519 static int ni_cdo_inttrig(struct comedi_device *dev,
3520 struct comedi_subdevice *s,
3521 unsigned int trig_num)
3523 struct comedi_cmd *cmd = &s->async->cmd;
3524 const unsigned timeout = 1000;
3528 struct ni_private *devpriv = dev->private;
3529 unsigned long flags;
3532 if (trig_num != cmd->start_arg)
3535 s->async->inttrig = NULL;
3537 /* read alloc the entire buffer */
3538 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3541 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3542 if (devpriv->cdo_mite_chan) {
3543 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3544 mite_dma_arm(devpriv->cdo_mite_chan);
3546 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3549 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3554 * XXX not sure what interrupt C group does
3555 * ni_writeb(dev, Interrupt_Group_C_Enable_Bit,
3556 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3558 for (i = 0; i < timeout; ++i) {
3559 if (ni_readl(dev, M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3564 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3568 ni_writel(dev, CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3569 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3570 M_Offset_CDIO_Command);
3574 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3576 const struct comedi_cmd *cmd = &s->async->cmd;
3577 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3580 ni_writel(dev, CDO_Reset_Bit, M_Offset_CDIO_Command);
3581 switch (cmd->scan_begin_src) {
3584 CR_CHAN(cmd->scan_begin_arg) &
3585 CDO_Sample_Source_Select_Mask;
3591 if (cmd->scan_begin_arg & CR_INVERT)
3592 cdo_mode_bits |= CDO_Polarity_Bit;
3593 ni_writel(dev, cdo_mode_bits, M_Offset_CDO_Mode);
3595 ni_writel(dev, s->state, M_Offset_CDO_FIFO_Data);
3596 ni_writel(dev, CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3597 ni_writel(dev, s->io_bits, M_Offset_CDO_Mask_Enable);
3599 dev_err(dev->class_dev,
3600 "attempted to run digital output command with no lines configured as outputs\n");
3603 retval = ni_request_cdo_mite_channel(dev);
3607 s->async->inttrig = ni_cdo_inttrig;
3612 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3614 ni_writel(dev, CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3615 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3616 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3617 M_Offset_CDIO_Command);
3619 * XXX not sure what interrupt C group does ni_writeb(dev, 0,
3620 * M_Offset_Interrupt_C_Enable);
3622 ni_writel(dev, 0, M_Offset_CDO_Mask_Enable);
3623 ni_release_cdo_mite_channel(dev);
3627 static void handle_cdio_interrupt(struct comedi_device *dev)
3629 struct ni_private *devpriv = dev->private;
3630 unsigned cdio_status;
3631 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3633 unsigned long flags;
3636 if (!devpriv->is_m_series)
3639 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3640 if (devpriv->cdo_mite_chan) {
3641 unsigned cdo_mite_status =
3642 mite_get_status(devpriv->cdo_mite_chan);
3643 if (cdo_mite_status & CHSR_LINKC) {
3645 devpriv->mite->mite_io_addr +
3646 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3648 mite_sync_output_dma(devpriv->cdo_mite_chan, s);
3650 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3653 cdio_status = ni_readl(dev, M_Offset_CDIO_Status);
3654 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3655 /* XXX just guessing this is needed and does something useful */
3656 ni_writel(dev, CDO_Error_Interrupt_Confirm_Bit,
3657 M_Offset_CDIO_Command);
3658 s->async->events |= COMEDI_CB_OVERFLOW;
3660 if (cdio_status & CDO_FIFO_Empty_Bit) {
3661 ni_writel(dev, CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3662 M_Offset_CDIO_Command);
3663 /* s->async->events |= COMEDI_CB_EOA; */
3665 comedi_handle_events(dev, s);
3668 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3669 struct comedi_subdevice *s,
3670 unsigned char data_out,
3671 unsigned char *data_in)
3673 struct ni_private *devpriv = dev->private;
3674 unsigned int status1;
3675 int err = 0, count = 20;
3677 devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3678 devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3679 ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3681 status1 = ni_stc_readw(dev, Joint_Status_1_Register);
3682 if (status1 & DIO_Serial_IO_In_Progress_St) {
3687 devpriv->dio_control |= DIO_HW_Serial_Start;
3688 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3689 devpriv->dio_control &= ~DIO_HW_Serial_Start;
3691 /* Wait until STC says we're done, but don't loop infinitely. */
3692 while ((status1 = ni_stc_readw(dev, Joint_Status_1_Register)) &
3693 DIO_Serial_IO_In_Progress_St) {
3694 /* Delay one bit per loop */
3695 udelay((devpriv->serial_interval_ns + 999) / 1000);
3697 dev_err(dev->class_dev,
3698 "SPI serial I/O didn't finish in time!\n");
3704 /* Delay for last bit. This delay is absolutely necessary, because
3705 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3706 udelay((devpriv->serial_interval_ns + 999) / 1000);
3709 *data_in = ni_stc_readw(dev, DIO_Serial_Input_Register);
3712 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3717 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3718 struct comedi_subdevice *s,
3719 unsigned char data_out,
3720 unsigned char *data_in)
3722 struct ni_private *devpriv = dev->private;
3723 unsigned char mask, input = 0;
3725 /* Wait for one bit before transfer */
3726 udelay((devpriv->serial_interval_ns + 999) / 1000);
3728 for (mask = 0x80; mask; mask >>= 1) {
3729 /* Output current bit; note that we cannot touch s->state
3730 because it is a per-subdevice field, and serial is
3731 a separate subdevice from DIO. */
3732 devpriv->dio_output &= ~DIO_SDOUT;
3733 if (data_out & mask)
3734 devpriv->dio_output |= DIO_SDOUT;
3735 ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3737 /* Assert SDCLK (active low, inverted), wait for half of
3738 the delay, deassert SDCLK, and wait for the other half. */
3739 devpriv->dio_control |= DIO_Software_Serial_Control;
3740 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3742 udelay((devpriv->serial_interval_ns + 999) / 2000);
3744 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3745 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3747 udelay((devpriv->serial_interval_ns + 999) / 2000);
3749 /* Input current bit */
3750 if (ni_stc_readw(dev, DIO_Parallel_Input_Register) & DIO_SDIN)
3760 static int ni_serial_insn_config(struct comedi_device *dev,
3761 struct comedi_subdevice *s,
3762 struct comedi_insn *insn,
3765 struct ni_private *devpriv = dev->private;
3767 unsigned char byte_out, byte_in = 0;
3773 case INSN_CONFIG_SERIAL_CLOCK:
3774 devpriv->serial_hw_mode = 1;
3775 devpriv->dio_control |= DIO_HW_Serial_Enable;
3777 if (data[1] == SERIAL_DISABLED) {
3778 devpriv->serial_hw_mode = 0;
3779 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3780 DIO_Software_Serial_Control);
3781 data[1] = SERIAL_DISABLED;
3782 devpriv->serial_interval_ns = data[1];
3783 } else if (data[1] <= SERIAL_600NS) {
3784 /* Warning: this clock speed is too fast to reliably
3786 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3787 devpriv->clock_and_fout |= Slow_Internal_Timebase;
3788 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3789 data[1] = SERIAL_600NS;
3790 devpriv->serial_interval_ns = data[1];
3791 } else if (data[1] <= SERIAL_1_2US) {
3792 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3793 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3794 DIO_Serial_Out_Divide_By_2;
3795 data[1] = SERIAL_1_2US;
3796 devpriv->serial_interval_ns = data[1];
3797 } else if (data[1] <= SERIAL_10US) {
3798 devpriv->dio_control |= DIO_HW_Serial_Timebase;
3799 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3800 DIO_Serial_Out_Divide_By_2;
3801 /* Note: DIO_Serial_Out_Divide_By_2 only affects
3802 600ns/1.2us. If you turn divide_by_2 off with the
3803 slow clock, you will still get 10us, except then
3804 all your delays are wrong. */
3805 data[1] = SERIAL_10US;
3806 devpriv->serial_interval_ns = data[1];
3808 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3809 DIO_Software_Serial_Control);
3810 devpriv->serial_hw_mode = 0;
3811 data[1] = (data[1] / 1000) * 1000;
3812 devpriv->serial_interval_ns = data[1];
3815 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3816 ni_stc_writew(dev, devpriv->clock_and_fout,
3817 Clock_and_FOUT_Register);
3820 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3822 if (devpriv->serial_interval_ns == 0)
3825 byte_out = data[1] & 0xFF;
3827 if (devpriv->serial_hw_mode) {
3828 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3830 } else if (devpriv->serial_interval_ns > 0) {
3831 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3834 dev_err(dev->class_dev, "serial disabled!\n");
3839 data[1] = byte_in & 0xFF;
3848 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3852 for (i = 0; i < s->n_chan; i++) {
3853 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
3854 AO_Configuration_2_67xx);
3856 ni_ao_win_outw(dev, 0x0, AO_Later_Single_Point_Updates);
3859 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
3861 unsigned stc_register;
3864 case NITIO_G0_AUTO_INC:
3865 stc_register = G_Autoincrement_Register(0);
3867 case NITIO_G1_AUTO_INC:
3868 stc_register = G_Autoincrement_Register(1);
3871 stc_register = G_Command_Register(0);
3874 stc_register = G_Command_Register(1);
3876 case NITIO_G0_HW_SAVE:
3877 stc_register = G_HW_Save_Register(0);
3879 case NITIO_G1_HW_SAVE:
3880 stc_register = G_HW_Save_Register(1);
3882 case NITIO_G0_SW_SAVE:
3883 stc_register = G_Save_Register(0);
3885 case NITIO_G1_SW_SAVE:
3886 stc_register = G_Save_Register(1);
3889 stc_register = G_Mode_Register(0);
3892 stc_register = G_Mode_Register(1);
3894 case NITIO_G0_LOADA:
3895 stc_register = G_Load_A_Register(0);
3897 case NITIO_G1_LOADA:
3898 stc_register = G_Load_A_Register(1);
3900 case NITIO_G0_LOADB:
3901 stc_register = G_Load_B_Register(0);
3903 case NITIO_G1_LOADB:
3904 stc_register = G_Load_B_Register(1);
3906 case NITIO_G0_INPUT_SEL:
3907 stc_register = G_Input_Select_Register(0);
3909 case NITIO_G1_INPUT_SEL:
3910 stc_register = G_Input_Select_Register(1);
3912 case NITIO_G01_STATUS:
3913 stc_register = G_Status_Register;
3915 case NITIO_G01_RESET:
3916 stc_register = Joint_Reset_Register;
3918 case NITIO_G01_STATUS1:
3919 stc_register = Joint_Status_1_Register;
3921 case NITIO_G01_STATUS2:
3922 stc_register = Joint_Status_2_Register;
3924 case NITIO_G0_INT_ACK:
3925 stc_register = Interrupt_A_Ack_Register;
3927 case NITIO_G1_INT_ACK:
3928 stc_register = Interrupt_B_Ack_Register;
3930 case NITIO_G0_STATUS:
3931 stc_register = AI_Status_1_Register;
3933 case NITIO_G1_STATUS:
3934 stc_register = AO_Status_1_Register;
3936 case NITIO_G0_INT_ENA:
3937 stc_register = Interrupt_A_Enable_Register;
3939 case NITIO_G1_INT_ENA:
3940 stc_register = Interrupt_B_Enable_Register;
3943 pr_err("%s: unhandled register 0x%x in switch.\n",
3948 return stc_register;
3951 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
3952 enum ni_gpct_register reg)
3954 struct comedi_device *dev = counter->counter_dev->dev;
3955 unsigned stc_register;
3956 /* bits in the join reset register which are relevant to counters */
3957 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
3958 static const unsigned gpct_interrupt_a_enable_mask =
3959 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
3960 static const unsigned gpct_interrupt_b_enable_mask =
3961 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
3964 /* m-series-only registers */
3965 case NITIO_G0_CNT_MODE:
3966 ni_writew(dev, bits, M_Offset_G0_Counting_Mode);
3968 case NITIO_G1_CNT_MODE:
3969 ni_writew(dev, bits, M_Offset_G1_Counting_Mode);
3971 case NITIO_G0_GATE2:
3972 ni_writew(dev, bits, M_Offset_G0_Second_Gate);
3974 case NITIO_G1_GATE2:
3975 ni_writew(dev, bits, M_Offset_G1_Second_Gate);
3977 case NITIO_G0_DMA_CFG:
3978 ni_writew(dev, bits, M_Offset_G0_DMA_Config);
3980 case NITIO_G1_DMA_CFG:
3981 ni_writew(dev, bits, M_Offset_G1_DMA_Config);
3984 ni_writew(dev, bits, M_Offset_G0_MSeries_ABZ);
3987 ni_writew(dev, bits, M_Offset_G1_MSeries_ABZ);
3990 /* 32 bit registers */
3991 case NITIO_G0_LOADA:
3992 case NITIO_G1_LOADA:
3993 case NITIO_G0_LOADB:
3994 case NITIO_G1_LOADB:
3995 stc_register = ni_gpct_to_stc_register(reg);
3996 ni_stc_writel(dev, bits, stc_register);
3999 /* 16 bit registers */
4000 case NITIO_G0_INT_ENA:
4001 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4002 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4003 gpct_interrupt_a_enable_mask, bits);
4005 case NITIO_G1_INT_ENA:
4006 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4007 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4008 gpct_interrupt_b_enable_mask, bits);
4010 case NITIO_G01_RESET:
4011 BUG_ON(bits & ~gpct_joint_reset_mask);
4014 stc_register = ni_gpct_to_stc_register(reg);
4015 ni_stc_writew(dev, bits, stc_register);
4019 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4020 enum ni_gpct_register reg)
4022 struct comedi_device *dev = counter->counter_dev->dev;
4023 unsigned stc_register;
4026 /* m-series only registers */
4027 case NITIO_G0_DMA_STATUS:
4028 return ni_readw(dev, M_Offset_G0_DMA_Status);
4029 case NITIO_G1_DMA_STATUS:
4030 return ni_readw(dev, M_Offset_G1_DMA_Status);
4032 /* 32 bit registers */
4033 case NITIO_G0_HW_SAVE:
4034 case NITIO_G1_HW_SAVE:
4035 case NITIO_G0_SW_SAVE:
4036 case NITIO_G1_SW_SAVE:
4037 stc_register = ni_gpct_to_stc_register(reg);
4038 return ni_stc_readl(dev, stc_register);
4040 /* 16 bit registers */
4042 stc_register = ni_gpct_to_stc_register(reg);
4043 return ni_stc_readw(dev, stc_register);
4048 static int ni_freq_out_insn_read(struct comedi_device *dev,
4049 struct comedi_subdevice *s,
4050 struct comedi_insn *insn,
4053 struct ni_private *devpriv = dev->private;
4054 unsigned int val = devpriv->clock_and_fout & FOUT_Divider_mask;
4057 for (i = 0; i < insn->n; i++)
4063 static int ni_freq_out_insn_write(struct comedi_device *dev,
4064 struct comedi_subdevice *s,
4065 struct comedi_insn *insn,
4068 struct ni_private *devpriv = dev->private;
4071 devpriv->clock_and_fout &= ~FOUT_Enable;
4072 ni_stc_writew(dev, devpriv->clock_and_fout,
4073 Clock_and_FOUT_Register);
4074 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4076 /* use the last data value to set the fout divider */
4077 devpriv->clock_and_fout |= FOUT_Divider(data[insn->n - 1]);
4079 devpriv->clock_and_fout |= FOUT_Enable;
4080 ni_stc_writew(dev, devpriv->clock_and_fout,
4081 Clock_and_FOUT_Register);
4086 static int ni_freq_out_insn_config(struct comedi_device *dev,
4087 struct comedi_subdevice *s,
4088 struct comedi_insn *insn,
4091 struct ni_private *devpriv = dev->private;
4094 case INSN_CONFIG_SET_CLOCK_SRC:
4096 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4097 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4099 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4100 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4105 ni_stc_writew(dev, devpriv->clock_and_fout,
4106 Clock_and_FOUT_Register);
4108 case INSN_CONFIG_GET_CLOCK_SRC:
4109 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4110 data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4111 data[2] = TIMEBASE_2_NS;
4113 data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4114 data[2] = TIMEBASE_1_NS * 2;
4123 static int ni_8255_callback(struct comedi_device *dev,
4124 int dir, int port, int data, unsigned long iobase)
4127 ni_writeb(dev, data, iobase + 2 * port);
4131 return ni_readb(dev, iobase + 2 * port);
4134 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4136 struct ni_private *devpriv = dev->private;
4138 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4139 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4143 static int ni_m_series_pwm_config(struct comedi_device *dev,
4144 struct comedi_subdevice *s,
4145 struct comedi_insn *insn,
4148 struct ni_private *devpriv = dev->private;
4149 unsigned up_count, down_count;
4152 case INSN_CONFIG_PWM_OUTPUT:
4154 case CMDF_ROUND_NEAREST:
4157 devpriv->clock_ns / 2) / devpriv->clock_ns;
4159 case CMDF_ROUND_DOWN:
4160 up_count = data[2] / devpriv->clock_ns;
4164 (data[2] + devpriv->clock_ns -
4165 1) / devpriv->clock_ns;
4171 case CMDF_ROUND_NEAREST:
4174 devpriv->clock_ns / 2) / devpriv->clock_ns;
4176 case CMDF_ROUND_DOWN:
4177 down_count = data[4] / devpriv->clock_ns;
4181 (data[4] + devpriv->clock_ns -
4182 1) / devpriv->clock_ns;
4187 if (up_count * devpriv->clock_ns != data[2] ||
4188 down_count * devpriv->clock_ns != data[4]) {
4189 data[2] = up_count * devpriv->clock_ns;
4190 data[4] = down_count * devpriv->clock_ns;
4193 ni_writel(dev, MSeries_Cal_PWM_High_Time_Bits(up_count) |
4194 MSeries_Cal_PWM_Low_Time_Bits(down_count),
4196 devpriv->pwm_up_count = up_count;
4197 devpriv->pwm_down_count = down_count;
4199 case INSN_CONFIG_GET_PWM_OUTPUT:
4200 return ni_get_pwm_config(dev, data);
4207 static int ni_6143_pwm_config(struct comedi_device *dev,
4208 struct comedi_subdevice *s,
4209 struct comedi_insn *insn,
4212 struct ni_private *devpriv = dev->private;
4213 unsigned up_count, down_count;
4216 case INSN_CONFIG_PWM_OUTPUT:
4218 case CMDF_ROUND_NEAREST:
4221 devpriv->clock_ns / 2) / devpriv->clock_ns;
4223 case CMDF_ROUND_DOWN:
4224 up_count = data[2] / devpriv->clock_ns;
4228 (data[2] + devpriv->clock_ns -
4229 1) / devpriv->clock_ns;
4235 case CMDF_ROUND_NEAREST:
4238 devpriv->clock_ns / 2) / devpriv->clock_ns;
4240 case CMDF_ROUND_DOWN:
4241 down_count = data[4] / devpriv->clock_ns;
4245 (data[4] + devpriv->clock_ns -
4246 1) / devpriv->clock_ns;
4251 if (up_count * devpriv->clock_ns != data[2] ||
4252 down_count * devpriv->clock_ns != data[4]) {
4253 data[2] = up_count * devpriv->clock_ns;
4254 data[4] = down_count * devpriv->clock_ns;
4257 ni_writel(dev, up_count, Calibration_HighTime_6143);
4258 devpriv->pwm_up_count = up_count;
4259 ni_writel(dev, down_count, Calibration_LowTime_6143);
4260 devpriv->pwm_down_count = down_count;
4262 case INSN_CONFIG_GET_PWM_OUTPUT:
4263 return ni_get_pwm_config(dev, data);
4270 static int pack_mb88341(int addr, int val, int *bitstring)
4274 Note that address bits are reversed. Thanks to
4275 Ingo Keen for noticing this.
4277 Note also that the 88341 expects address values from
4278 1-12, whereas we use channel numbers 0-11. The NI
4279 docs use 1-12, also, so be careful here.
4282 *bitstring = ((addr & 0x1) << 11) |
4283 ((addr & 0x2) << 9) |
4284 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4288 static int pack_dac8800(int addr, int val, int *bitstring)
4290 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4294 static int pack_dac8043(int addr, int val, int *bitstring)
4296 *bitstring = val & 0xfff;
4300 static int pack_ad8522(int addr, int val, int *bitstring)
4302 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4306 static int pack_ad8804(int addr, int val, int *bitstring)
4308 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4312 static int pack_ad8842(int addr, int val, int *bitstring)
4314 *bitstring = ((addr + 1) << 8) | (val & 0xff);
4318 struct caldac_struct {
4321 int (*packbits)(int, int, int *);
4324 static struct caldac_struct caldacs[] = {
4325 [mb88341] = {12, 8, pack_mb88341},
4326 [dac8800] = {8, 8, pack_dac8800},
4327 [dac8043] = {1, 12, pack_dac8043},
4328 [ad8522] = {2, 12, pack_ad8522},
4329 [ad8804] = {12, 8, pack_ad8804},
4330 [ad8842] = {8, 8, pack_ad8842},
4331 [ad8804_debug] = {16, 8, pack_ad8804},
4334 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4336 const struct ni_board_struct *board = dev->board_ptr;
4337 struct ni_private *devpriv = dev->private;
4338 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4342 if (devpriv->caldacs[addr] == val)
4344 devpriv->caldacs[addr] = val;
4346 for (i = 0; i < 3; i++) {
4347 type = board->caldac[i];
4348 if (type == caldac_none)
4350 if (addr < caldacs[type].n_chans) {
4351 bits = caldacs[type].packbits(addr, val, &bitstring);
4352 loadbit = SerDacLd(i);
4355 addr -= caldacs[type].n_chans;
4358 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4359 ni_writeb(dev, ((bit & bitstring) ? 0x02 : 0), Serial_Command);
4361 ni_writeb(dev, 1 | ((bit & bitstring) ? 0x02 : 0),
4365 ni_writeb(dev, loadbit, Serial_Command);
4367 ni_writeb(dev, 0, Serial_Command);
4370 static int ni_calib_insn_write(struct comedi_device *dev,
4371 struct comedi_subdevice *s,
4372 struct comedi_insn *insn,
4375 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4380 static int ni_calib_insn_read(struct comedi_device *dev,
4381 struct comedi_subdevice *s,
4382 struct comedi_insn *insn,
4385 struct ni_private *devpriv = dev->private;
4387 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4392 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4394 const struct ni_board_struct *board = dev->board_ptr;
4395 struct ni_private *devpriv = dev->private;
4404 type = board->caldac[0];
4405 if (type == caldac_none)
4407 n_bits = caldacs[type].n_bits;
4408 for (i = 0; i < 3; i++) {
4409 type = board->caldac[i];
4410 if (type == caldac_none)
4412 if (caldacs[type].n_bits != n_bits)
4414 n_chans += caldacs[type].n_chans;
4417 s->n_chan = n_chans;
4420 unsigned int *maxdata_list;
4422 if (n_chans > MAX_N_CALDACS)
4423 dev_err(dev->class_dev,
4424 "BUG! MAX_N_CALDACS too small\n");
4425 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4427 for (i = 0; i < n_dacs; i++) {
4428 type = board->caldac[i];
4429 for (j = 0; j < caldacs[type].n_chans; j++) {
4430 maxdata_list[chan] =
4431 (1 << caldacs[type].n_bits) - 1;
4436 for (chan = 0; chan < s->n_chan; chan++)
4437 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4439 type = board->caldac[0];
4440 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4442 for (chan = 0; chan < s->n_chan; chan++)
4443 ni_write_caldac(dev, i, s->maxdata / 2);
4447 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4452 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4453 ni_writeb(dev, 0x04, Serial_Command);
4454 for (bit = 0x8000; bit; bit >>= 1) {
4455 ni_writeb(dev, 0x04 | ((bit & bitstring) ? 0x02 : 0),
4457 ni_writeb(dev, 0x05 | ((bit & bitstring) ? 0x02 : 0),
4461 for (bit = 0x80; bit; bit >>= 1) {
4462 ni_writeb(dev, 0x04, Serial_Command);
4463 ni_writeb(dev, 0x05, Serial_Command);
4464 bitstring |= ((ni_readb(dev, XXX_Status) & PROMOUT) ? bit : 0);
4466 ni_writeb(dev, 0x00, Serial_Command);
4471 static int ni_eeprom_insn_read(struct comedi_device *dev,
4472 struct comedi_subdevice *s,
4473 struct comedi_insn *insn,
4476 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4481 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4482 struct comedi_subdevice *s,
4483 struct comedi_insn *insn,
4486 struct ni_private *devpriv = dev->private;
4488 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4493 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
4496 /* pre-m-series boards have fixed signals on pfi pins */
4499 return NI_PFI_OUTPUT_AI_START1;
4501 return NI_PFI_OUTPUT_AI_START2;
4503 return NI_PFI_OUTPUT_AI_CONVERT;
4505 return NI_PFI_OUTPUT_G_SRC1;
4507 return NI_PFI_OUTPUT_G_GATE1;
4509 return NI_PFI_OUTPUT_AO_UPDATE_N;
4511 return NI_PFI_OUTPUT_AO_START1;
4513 return NI_PFI_OUTPUT_AI_START_PULSE;
4515 return NI_PFI_OUTPUT_G_SRC0;
4517 return NI_PFI_OUTPUT_G_GATE0;
4519 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4525 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4526 unsigned chan, unsigned source)
4528 /* pre-m-series boards have fixed signals on pfi pins */
4529 if (source != ni_old_get_pfi_routing(dev, chan))
4534 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
4537 struct ni_private *devpriv = dev->private;
4538 const unsigned array_offset = chan / 3;
4540 return MSeries_PFI_Output_Select_Source(chan,
4541 devpriv->pfi_output_select_reg[array_offset]);
4544 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4545 unsigned chan, unsigned source)
4547 struct ni_private *devpriv = dev->private;
4548 unsigned pfi_reg_index;
4549 unsigned array_offset;
4551 if ((source & 0x1f) != source)
4553 pfi_reg_index = 1 + chan / 3;
4554 array_offset = pfi_reg_index - 1;
4555 devpriv->pfi_output_select_reg[array_offset] &=
4556 ~MSeries_PFI_Output_Select_Mask(chan);
4557 devpriv->pfi_output_select_reg[array_offset] |=
4558 MSeries_PFI_Output_Select_Bits(chan, source);
4559 ni_writew(dev, devpriv->pfi_output_select_reg[array_offset],
4560 M_Offset_PFI_Output_Select(pfi_reg_index));
4564 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
4566 struct ni_private *devpriv = dev->private;
4568 return (devpriv->is_m_series)
4569 ? ni_m_series_get_pfi_routing(dev, chan)
4570 : ni_old_get_pfi_routing(dev, chan);
4573 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
4576 struct ni_private *devpriv = dev->private;
4578 return (devpriv->is_m_series)
4579 ? ni_m_series_set_pfi_routing(dev, chan, source)
4580 : ni_old_set_pfi_routing(dev, chan, source);
4583 static int ni_config_filter(struct comedi_device *dev,
4584 unsigned pfi_channel,
4585 enum ni_pfi_filter_select filter)
4587 struct ni_private *devpriv = dev->private;
4590 if (!devpriv->is_m_series)
4593 bits = ni_readl(dev, M_Offset_PFI_Filter);
4594 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
4595 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
4596 ni_writel(dev, bits, M_Offset_PFI_Filter);
4600 static int ni_pfi_insn_config(struct comedi_device *dev,
4601 struct comedi_subdevice *s,
4602 struct comedi_insn *insn,
4605 struct ni_private *devpriv = dev->private;
4611 chan = CR_CHAN(insn->chanspec);
4615 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
4618 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
4620 case INSN_CONFIG_DIO_QUERY:
4622 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4623 COMEDI_OUTPUT : COMEDI_INPUT;
4625 case INSN_CONFIG_SET_ROUTING:
4626 return ni_set_pfi_routing(dev, chan, data[1]);
4627 case INSN_CONFIG_GET_ROUTING:
4628 data[1] = ni_get_pfi_routing(dev, chan);
4630 case INSN_CONFIG_FILTER:
4631 return ni_config_filter(dev, chan, data[1]);
4638 static int ni_pfi_insn_bits(struct comedi_device *dev,
4639 struct comedi_subdevice *s,
4640 struct comedi_insn *insn,
4643 struct ni_private *devpriv = dev->private;
4645 if (!devpriv->is_m_series)
4648 if (comedi_dio_update_state(s, data))
4649 ni_writew(dev, s->state, M_Offset_PFI_DO);
4651 data[1] = ni_readw(dev, M_Offset_PFI_DI);
4656 static int cs5529_wait_for_idle(struct comedi_device *dev)
4658 unsigned short status;
4659 const int timeout = HZ;
4662 for (i = 0; i < timeout; i++) {
4663 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4664 if ((status & CSS_ADC_BUSY) == 0)
4666 set_current_state(TASK_INTERRUPTIBLE);
4667 if (schedule_timeout(1))
4671 dev_err(dev->class_dev, "timeout\n");
4677 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4679 static const int timeout = 100;
4682 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
4683 /* give time for command to start being serially clocked into cs5529.
4684 * this insures that the CSS_ADC_BUSY bit will get properly
4685 * set before we exit this function.
4687 for (i = 0; i < timeout; i++) {
4688 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
4693 dev_err(dev->class_dev,
4694 "possible problem - never saw adc go busy?\n");
4697 static int cs5529_do_conversion(struct comedi_device *dev,
4698 unsigned short *data)
4701 unsigned short status;
4703 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
4704 retval = cs5529_wait_for_idle(dev);
4706 dev_err(dev->class_dev,
4707 "timeout or signal in cs5529_do_conversion()\n");
4710 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4711 if (status & CSS_OSC_DETECT) {
4712 dev_err(dev->class_dev,
4713 "cs5529 conversion error, status CSS_OSC_DETECT\n");
4716 if (status & CSS_OVERRANGE) {
4717 dev_err(dev->class_dev,
4718 "cs5529 conversion error, overrange (ignoring)\n");
4721 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
4722 /* cs5529 returns 16 bit signed data in bipolar mode */
4728 static int cs5529_ai_insn_read(struct comedi_device *dev,
4729 struct comedi_subdevice *s,
4730 struct comedi_insn *insn,
4734 unsigned short sample;
4735 unsigned int channel_select;
4736 const unsigned int INTERNAL_REF = 0x1000;
4738 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
4739 * do nothing. bit 12 seems to chooses internal reference voltage, bit
4740 * 13 causes the adc input to go overrange (maybe reads external reference?) */
4741 if (insn->chanspec & CR_ALT_SOURCE)
4742 channel_select = INTERNAL_REF;
4744 channel_select = CR_CHAN(insn->chanspec);
4745 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
4747 for (n = 0; n < insn->n; n++) {
4748 retval = cs5529_do_conversion(dev, &sample);
4756 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4757 unsigned int reg_select_bits)
4759 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
4760 CAL_ADC_Config_Data_High_Word_67xx);
4761 ni_ao_win_outw(dev, (value & 0xffff),
4762 CAL_ADC_Config_Data_Low_Word_67xx);
4763 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4764 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
4765 if (cs5529_wait_for_idle(dev))
4766 dev_err(dev->class_dev,
4767 "timeout or signal in %s\n", __func__);
4770 static int init_cs5529(struct comedi_device *dev)
4772 unsigned int config_bits =
4773 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
4776 /* do self-calibration */
4777 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
4778 CSCMD_CONFIG_REGISTER);
4779 /* need to force a conversion for calibration to run */
4780 cs5529_do_conversion(dev, NULL);
4782 /* force gain calibration to 1 */
4783 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
4784 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
4785 CSCMD_CONFIG_REGISTER);
4786 if (cs5529_wait_for_idle(dev))
4787 dev_err(dev->class_dev,
4788 "timeout or signal in %s\n", __func__);
4794 * Find best multiplier/divider to try and get the PLL running at 80 MHz
4795 * given an arbitrary frequency input clock.
4797 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4798 unsigned *freq_divider,
4799 unsigned *freq_multiplier,
4800 unsigned *actual_period_ns)
4803 unsigned best_div = 1;
4804 static const unsigned max_div = 0x10;
4806 unsigned best_mult = 1;
4807 static const unsigned max_mult = 0x100;
4808 static const unsigned pico_per_nano = 1000;
4810 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4811 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4812 * 20 MHz for most timing clocks */
4813 static const unsigned target_picosec = 12500;
4814 static const unsigned fudge_factor_80_to_20Mhz = 4;
4815 int best_period_picosec = 0;
4817 for (div = 1; div <= max_div; ++div) {
4818 for (mult = 1; mult <= max_mult; ++mult) {
4819 unsigned new_period_ps =
4820 (reference_picosec * div) / mult;
4821 if (abs(new_period_ps - target_picosec) <
4822 abs(best_period_picosec - target_picosec)) {
4823 best_period_picosec = new_period_ps;
4829 if (best_period_picosec == 0)
4832 *freq_divider = best_div;
4833 *freq_multiplier = best_mult;
4835 (best_period_picosec * fudge_factor_80_to_20Mhz +
4836 (pico_per_nano / 2)) / pico_per_nano;
4840 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4841 unsigned source, unsigned period_ns)
4843 struct ni_private *devpriv = dev->private;
4844 static const unsigned min_period_ns = 50;
4845 static const unsigned max_period_ns = 1000;
4846 static const unsigned timeout = 1000;
4847 unsigned pll_control_bits;
4848 unsigned freq_divider;
4849 unsigned freq_multiplier;
4853 if (source == NI_MIO_PLL_PXI10_CLOCK)
4855 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
4856 if (period_ns < min_period_ns || period_ns > max_period_ns) {
4857 dev_err(dev->class_dev,
4858 "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4859 __func__, min_period_ns, max_period_ns);
4862 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4863 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4864 RTSI_Trig_Direction_Register);
4866 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
4867 devpriv->clock_and_fout2 |=
4868 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
4869 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
4871 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4872 devpriv->clock_and_fout2 |=
4873 MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
4875 case NI_MIO_PLL_PXI10_CLOCK:
4876 /* pxi clock is 10MHz */
4877 devpriv->clock_and_fout2 |=
4878 MSeries_PLL_In_Source_Select_PXI_Clock10;
4882 unsigned rtsi_channel;
4883 static const unsigned max_rtsi_channel = 7;
4885 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
4888 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
4889 devpriv->clock_and_fout2 |=
4890 MSeries_PLL_In_Source_Select_RTSI_Bits
4895 if (rtsi_channel > max_rtsi_channel)
4900 retval = ni_mseries_get_pll_parameters(period_ns,
4903 &devpriv->clock_ns);
4905 dev_err(dev->class_dev,
4906 "bug, failed to find pll parameters\n");
4910 ni_writew(dev, devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
4912 MSeries_PLL_Divisor_Bits(freq_divider) |
4913 MSeries_PLL_Multiplier_Bits(freq_multiplier);
4915 ni_writew(dev, pll_control_bits, M_Offset_PLL_Control);
4916 devpriv->clock_source = source;
4917 /* it seems to typically take a few hundred microseconds for PLL to lock */
4918 for (i = 0; i < timeout; ++i) {
4919 if (ni_readw(dev, M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
4924 dev_err(dev->class_dev,
4925 "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4926 __func__, source, period_ns);
4932 static int ni_set_master_clock(struct comedi_device *dev,
4933 unsigned source, unsigned period_ns)
4935 struct ni_private *devpriv = dev->private;
4937 if (source == NI_MIO_INTERNAL_CLOCK) {
4938 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4939 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4940 RTSI_Trig_Direction_Register);
4941 devpriv->clock_ns = TIMEBASE_1_NS;
4942 if (devpriv->is_m_series) {
4943 devpriv->clock_and_fout2 &=
4944 ~(MSeries_Timebase1_Select_Bit |
4945 MSeries_Timebase3_Select_Bit);
4946 ni_writew(dev, devpriv->clock_and_fout2,
4947 M_Offset_Clock_and_Fout2);
4948 ni_writew(dev, 0, M_Offset_PLL_Control);
4950 devpriv->clock_source = source;
4952 if (devpriv->is_m_series) {
4953 return ni_mseries_set_pll_master_clock(dev, source,
4956 if (source == NI_MIO_RTSI_CLOCK) {
4957 devpriv->rtsi_trig_direction_reg |=
4960 devpriv->rtsi_trig_direction_reg,
4961 RTSI_Trig_Direction_Register);
4962 if (period_ns == 0) {
4963 dev_err(dev->class_dev,
4964 "we don't handle an unspecified clock period correctly yet, returning error\n");
4967 devpriv->clock_ns = period_ns;
4968 devpriv->clock_source = source;
4977 static unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
4979 struct ni_private *devpriv = dev->private;
4981 return (devpriv->is_m_series) ? 8 : 7;
4984 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4985 unsigned chan, unsigned source)
4987 struct ni_private *devpriv = dev->private;
4989 if (chan >= num_configurable_rtsi_channels(dev)) {
4990 if (chan == old_RTSI_clock_channel) {
4991 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4994 dev_err(dev->class_dev,
4995 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
4996 __func__, chan, old_RTSI_clock_channel);
5002 case NI_RTSI_OUTPUT_ADR_START1:
5003 case NI_RTSI_OUTPUT_ADR_START2:
5004 case NI_RTSI_OUTPUT_SCLKG:
5005 case NI_RTSI_OUTPUT_DACUPDN:
5006 case NI_RTSI_OUTPUT_DA_START1:
5007 case NI_RTSI_OUTPUT_G_SRC0:
5008 case NI_RTSI_OUTPUT_G_GATE0:
5009 case NI_RTSI_OUTPUT_RGOUT0:
5010 case NI_RTSI_OUTPUT_RTSI_BRD_0:
5012 case NI_RTSI_OUTPUT_RTSI_OSC:
5013 return (devpriv->is_m_series) ? 1 : 0;
5019 static int ni_set_rtsi_routing(struct comedi_device *dev,
5020 unsigned chan, unsigned source)
5022 struct ni_private *devpriv = dev->private;
5024 if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5027 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5028 devpriv->rtsi_trig_a_output_reg |=
5029 RTSI_Trig_Output_Bits(chan, source);
5030 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5031 RTSI_Trig_A_Output_Register);
5032 } else if (chan < 8) {
5033 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5034 devpriv->rtsi_trig_b_output_reg |=
5035 RTSI_Trig_Output_Bits(chan, source);
5036 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5037 RTSI_Trig_B_Output_Register);
5042 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5044 struct ni_private *devpriv = dev->private;
5047 return RTSI_Trig_Output_Source(chan,
5048 devpriv->rtsi_trig_a_output_reg);
5049 } else if (chan < num_configurable_rtsi_channels(dev)) {
5050 return RTSI_Trig_Output_Source(chan,
5051 devpriv->rtsi_trig_b_output_reg);
5053 if (chan == old_RTSI_clock_channel)
5054 return NI_RTSI_OUTPUT_RTSI_OSC;
5055 dev_err(dev->class_dev, "bug! should never get here?\n");
5060 static int ni_rtsi_insn_config(struct comedi_device *dev,
5061 struct comedi_subdevice *s,
5062 struct comedi_insn *insn,
5065 struct ni_private *devpriv = dev->private;
5066 unsigned int chan = CR_CHAN(insn->chanspec);
5069 case INSN_CONFIG_DIO_OUTPUT:
5070 if (chan < num_configurable_rtsi_channels(dev)) {
5071 devpriv->rtsi_trig_direction_reg |=
5072 RTSI_Output_Bit(chan, devpriv->is_m_series);
5073 } else if (chan == old_RTSI_clock_channel) {
5074 devpriv->rtsi_trig_direction_reg |=
5075 Drive_RTSI_Clock_Bit;
5077 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5078 RTSI_Trig_Direction_Register);
5080 case INSN_CONFIG_DIO_INPUT:
5081 if (chan < num_configurable_rtsi_channels(dev)) {
5082 devpriv->rtsi_trig_direction_reg &=
5083 ~RTSI_Output_Bit(chan, devpriv->is_m_series);
5084 } else if (chan == old_RTSI_clock_channel) {
5085 devpriv->rtsi_trig_direction_reg &=
5086 ~Drive_RTSI_Clock_Bit;
5088 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5089 RTSI_Trig_Direction_Register);
5091 case INSN_CONFIG_DIO_QUERY:
5092 if (chan < num_configurable_rtsi_channels(dev)) {
5094 (devpriv->rtsi_trig_direction_reg &
5095 RTSI_Output_Bit(chan, devpriv->is_m_series))
5096 ? INSN_CONFIG_DIO_OUTPUT
5097 : INSN_CONFIG_DIO_INPUT;
5098 } else if (chan == old_RTSI_clock_channel) {
5100 (devpriv->rtsi_trig_direction_reg &
5101 Drive_RTSI_Clock_Bit)
5102 ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5105 case INSN_CONFIG_SET_CLOCK_SRC:
5106 return ni_set_master_clock(dev, data[1], data[2]);
5107 case INSN_CONFIG_GET_CLOCK_SRC:
5108 data[1] = devpriv->clock_source;
5109 data[2] = devpriv->clock_ns;
5111 case INSN_CONFIG_SET_ROUTING:
5112 return ni_set_rtsi_routing(dev, chan, data[1]);
5113 case INSN_CONFIG_GET_ROUTING:
5114 data[1] = ni_get_rtsi_routing(dev, chan);
5122 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5123 struct comedi_subdevice *s,
5124 struct comedi_insn *insn,
5132 static void ni_rtsi_init(struct comedi_device *dev)
5134 struct ni_private *devpriv = dev->private;
5136 /* Initialises the RTSI bus signal switch to a default state */
5138 /* Set clock mode to internal */
5139 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5140 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5141 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
5142 /* default internal lines routing to RTSI bus lines */
5143 devpriv->rtsi_trig_a_output_reg =
5144 RTSI_Trig_Output_Bits(0,
5145 NI_RTSI_OUTPUT_ADR_START1) |
5146 RTSI_Trig_Output_Bits(1,
5147 NI_RTSI_OUTPUT_ADR_START2) |
5148 RTSI_Trig_Output_Bits(2,
5149 NI_RTSI_OUTPUT_SCLKG) |
5150 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5151 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5152 RTSI_Trig_A_Output_Register);
5153 devpriv->rtsi_trig_b_output_reg =
5154 RTSI_Trig_Output_Bits(4,
5155 NI_RTSI_OUTPUT_DA_START1) |
5156 RTSI_Trig_Output_Bits(5,
5157 NI_RTSI_OUTPUT_G_SRC0) |
5158 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5159 if (devpriv->is_m_series)
5160 devpriv->rtsi_trig_b_output_reg |=
5161 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5162 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5163 RTSI_Trig_B_Output_Register);
5166 * Sets the source and direction of the 4 on board lines
5167 * ni_stc_writew(dev, 0x0000, RTSI_Board_Register);
5172 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5174 struct ni_gpct *counter = s->private;
5177 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5180 dev_err(dev->class_dev,
5181 "no dma channel available for use by counter\n");
5184 ni_tio_acknowledge(counter);
5185 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5187 return ni_tio_cmd(dev, s);
5190 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5192 struct ni_gpct *counter = s->private;
5195 retval = ni_tio_cancel(counter);
5196 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5197 ni_release_gpct_mite_channel(dev, counter->counter_index);
5204 * Read the GPCTs current value.
5206 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5208 unsigned int hi1, hi2, lo;
5210 devpriv->gpct_command[chan] &= ~G_Save_Trace;
5211 ni_stc_writew(dev, devpriv->gpct_command[chan],
5212 G_Command_Register(chan));
5214 devpriv->gpct_command[chan] |= G_Save_Trace;
5215 ni_stc_writew(dev, devpriv->gpct_command[chan],
5216 G_Command_Register(chan));
5218 /* This procedure is used because the two registers cannot
5219 * be read atomically. */
5221 hi1 = ni_stc_readw(dev, G_Save_Register_High(chan));
5222 lo = ni_stc_readw(dev, G_Save_Register_Low(chan));
5223 hi2 = ni_stc_readw(dev, G_Save_Register_High(chan));
5224 } while (hi1 != hi2);
5226 return (hi1 << 16) | lo;
5229 static void GPCT_Reset(struct comedi_device *dev, int chan)
5231 int temp_ack_reg = 0;
5233 devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5237 ni_stc_writew(dev, G0_Reset, Joint_Reset_Register);
5238 ni_set_bits(dev, Interrupt_A_Enable_Register,
5239 G0_TC_Interrupt_Enable, 0);
5240 ni_set_bits(dev, Interrupt_A_Enable_Register,
5241 G0_Gate_Interrupt_Enable, 0);
5242 temp_ack_reg |= G0_Gate_Error_Confirm;
5243 temp_ack_reg |= G0_TC_Error_Confirm;
5244 temp_ack_reg |= G0_TC_Interrupt_Ack;
5245 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5246 ni_stc_writew(dev, temp_ack_reg, Interrupt_A_Ack_Register);
5248 /* problem...this interferes with the other ctr... */
5249 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5250 ni_stc_writew(dev, devpriv->an_trig_etc_reg,
5251 Analog_Trigger_Etc_Register);
5254 ni_stc_writew(dev, G1_Reset, Joint_Reset_Register);
5255 ni_set_bits(dev, Interrupt_B_Enable_Register,
5256 G1_TC_Interrupt_Enable, 0);
5257 ni_set_bits(dev, Interrupt_B_Enable_Register,
5258 G0_Gate_Interrupt_Enable, 0);
5259 temp_ack_reg |= G1_Gate_Error_Confirm;
5260 temp_ack_reg |= G1_TC_Error_Confirm;
5261 temp_ack_reg |= G1_TC_Interrupt_Ack;
5262 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5263 ni_stc_writew(dev, temp_ack_reg, Interrupt_B_Ack_Register);
5265 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5266 ni_stc_writew(dev, devpriv->an_trig_etc_reg,
5267 Analog_Trigger_Etc_Register);
5271 devpriv->gpct_mode[chan] = 0;
5272 devpriv->gpct_input_select[chan] = 0;
5273 devpriv->gpct_command[chan] = 0;
5275 devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5277 ni_stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan));
5278 ni_stc_writew(dev, devpriv->gpct_input_select[chan],
5279 G_Input_Select_Register(chan));
5280 ni_stc_writew(dev, 0, G_Autoincrement_Register(chan));
5284 static irqreturn_t ni_E_interrupt(int irq, void *d)
5286 struct comedi_device *dev = d;
5287 unsigned short a_status;
5288 unsigned short b_status;
5289 unsigned int ai_mite_status = 0;
5290 unsigned int ao_mite_status = 0;
5291 unsigned long flags;
5293 struct ni_private *devpriv = dev->private;
5294 struct mite_struct *mite = devpriv->mite;
5299 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
5301 /* lock to avoid race with comedi_poll */
5302 spin_lock_irqsave(&dev->spinlock, flags);
5303 a_status = ni_stc_readw(dev, AI_Status_1_Register);
5304 b_status = ni_stc_readw(dev, AO_Status_1_Register);
5307 struct ni_private *devpriv = dev->private;
5308 unsigned long flags_too;
5310 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5311 if (devpriv->ai_mite_chan) {
5312 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
5313 if (ai_mite_status & CHSR_LINKC)
5315 devpriv->mite->mite_io_addr +
5317 ai_mite_chan->channel));
5319 if (devpriv->ao_mite_chan) {
5320 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
5321 if (ao_mite_status & CHSR_LINKC)
5323 mite->mite_io_addr +
5325 ao_mite_chan->channel));
5327 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5330 ack_a_interrupt(dev, a_status);
5331 ack_b_interrupt(dev, b_status);
5332 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
5333 handle_a_interrupt(dev, a_status, ai_mite_status);
5334 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
5335 handle_b_interrupt(dev, b_status, ao_mite_status);
5336 handle_gpct_interrupt(dev, 0);
5337 handle_gpct_interrupt(dev, 1);
5338 handle_cdio_interrupt(dev);
5340 spin_unlock_irqrestore(&dev->spinlock, flags);
5344 static int ni_alloc_private(struct comedi_device *dev)
5346 struct ni_private *devpriv;
5348 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5352 spin_lock_init(&devpriv->window_lock);
5353 spin_lock_init(&devpriv->soft_reg_copy_lock);
5354 spin_lock_init(&devpriv->mite_channel_lock);
5359 static int ni_E_init(struct comedi_device *dev,
5360 unsigned interrupt_pin, unsigned irq_polarity)
5362 const struct ni_board_struct *board = dev->board_ptr;
5363 struct ni_private *devpriv = dev->private;
5364 struct comedi_subdevice *s;
5368 if (board->n_aochan > MAX_N_AO_CHAN) {
5369 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5373 /* initialize clock dividers */
5374 devpriv->clock_and_fout = Slow_Internal_Time_Divide_By_2 |
5375 Slow_Internal_Timebase |
5376 Clock_To_Board_Divide_By_2 |
5378 if (!devpriv->is_6xxx) {
5379 /* BEAM is this needed for PCI-6143 ?? */
5380 devpriv->clock_and_fout |= (AI_Output_Divide_By_2 |
5381 AO_Output_Divide_By_2);
5383 ni_stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register);
5385 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5389 /* Analog Input subdevice */
5390 s = &dev->subdevices[NI_AI_SUBDEV];
5391 if (board->n_adchan) {
5392 s->type = COMEDI_SUBD_AI;
5393 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5394 if (!devpriv->is_611x)
5395 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5396 if (board->ai_maxdata > 0xffff)
5397 s->subdev_flags |= SDF_LSAMPL;
5398 if (devpriv->is_m_series)
5399 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5400 s->n_chan = board->n_adchan;
5401 s->maxdata = board->ai_maxdata;
5402 s->range_table = ni_range_lkup[board->gainlkup];
5403 s->insn_read = ni_ai_insn_read;
5404 s->insn_config = ni_ai_insn_config;
5406 dev->read_subdev = s;
5407 s->subdev_flags |= SDF_CMD_READ;
5408 s->len_chanlist = 512;
5409 s->do_cmdtest = ni_ai_cmdtest;
5410 s->do_cmd = ni_ai_cmd;
5411 s->cancel = ni_ai_reset;
5412 s->poll = ni_ai_poll;
5413 s->munge = ni_ai_munge;
5416 s->async_dma_dir = DMA_FROM_DEVICE;
5419 /* reset the analog input configuration */
5420 ni_ai_reset(dev, s);
5422 s->type = COMEDI_SUBD_UNUSED;
5425 /* Analog Output subdevice */
5426 s = &dev->subdevices[NI_AO_SUBDEV];
5427 if (board->n_aochan) {
5428 s->type = COMEDI_SUBD_AO;
5429 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5430 if (devpriv->is_m_series)
5431 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5432 s->n_chan = board->n_aochan;
5433 s->maxdata = board->ao_maxdata;
5434 s->range_table = board->ao_range_table;
5435 s->insn_config = ni_ao_insn_config;
5436 s->insn_write = ni_ao_insn_write;
5438 ret = comedi_alloc_subdev_readback(s);
5443 * Along with the IRQ we need either a FIFO or DMA for
5444 * async command support.
5446 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5447 dev->write_subdev = s;
5448 s->subdev_flags |= SDF_CMD_WRITE;
5449 s->len_chanlist = s->n_chan;
5450 s->do_cmdtest = ni_ao_cmdtest;
5451 s->do_cmd = ni_ao_cmd;
5452 s->cancel = ni_ao_reset;
5453 if (!devpriv->is_m_series)
5454 s->munge = ni_ao_munge;
5457 s->async_dma_dir = DMA_TO_DEVICE;
5460 if (devpriv->is_67xx)
5461 init_ao_67xx(dev, s);
5463 /* reset the analog output configuration */
5464 ni_ao_reset(dev, s);
5466 s->type = COMEDI_SUBD_UNUSED;
5469 /* Digital I/O subdevice */
5470 s = &dev->subdevices[NI_DIO_SUBDEV];
5471 s->type = COMEDI_SUBD_DIO;
5472 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5473 s->n_chan = board->has_32dio_chan ? 32 : 8;
5475 s->range_table = &range_digital;
5476 if (devpriv->is_m_series) {
5477 s->subdev_flags |= SDF_LSAMPL;
5478 s->insn_bits = ni_m_series_dio_insn_bits;
5479 s->insn_config = ni_m_series_dio_insn_config;
5481 s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5482 s->len_chanlist = s->n_chan;
5483 s->do_cmdtest = ni_cdio_cmdtest;
5484 s->do_cmd = ni_cdio_cmd;
5485 s->cancel = ni_cdio_cancel;
5487 /* M-series boards use DMA */
5488 s->async_dma_dir = DMA_BIDIRECTIONAL;
5491 /* reset DIO and set all channels to inputs */
5492 ni_writel(dev, CDO_Reset_Bit | CDI_Reset_Bit,
5493 M_Offset_CDIO_Command);
5494 ni_writel(dev, s->io_bits, M_Offset_DIO_Direction);
5496 s->insn_bits = ni_dio_insn_bits;
5497 s->insn_config = ni_dio_insn_config;
5499 /* set all channels to inputs */
5500 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
5501 ni_writew(dev, devpriv->dio_control, DIO_Control_Register);
5505 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5506 if (board->has_8255) {
5507 ret = subdev_8255_init(dev, s, ni_8255_callback, Port_A);
5511 s->type = COMEDI_SUBD_UNUSED;
5514 /* formerly general purpose counter/timer device, but no longer used */
5515 s = &dev->subdevices[NI_UNUSED_SUBDEV];
5516 s->type = COMEDI_SUBD_UNUSED;
5518 /* Calibration subdevice */
5519 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5520 s->type = COMEDI_SUBD_CALIB;
5521 s->subdev_flags = SDF_INTERNAL;
5524 if (devpriv->is_m_series) {
5525 /* internal PWM output used for AI nonlinearity calibration */
5526 s->insn_config = ni_m_series_pwm_config;
5528 ni_writel(dev, 0x0, M_Offset_Cal_PWM);
5529 } else if (devpriv->is_6143) {
5530 /* internal PWM output used for AI nonlinearity calibration */
5531 s->insn_config = ni_6143_pwm_config;
5533 s->subdev_flags |= SDF_WRITABLE;
5534 s->insn_read = ni_calib_insn_read;
5535 s->insn_write = ni_calib_insn_write;
5537 /* setup the caldacs and find the real n_chan and maxdata */
5538 caldac_setup(dev, s);
5541 /* EEPROM subdevice */
5542 s = &dev->subdevices[NI_EEPROM_SUBDEV];
5543 s->type = COMEDI_SUBD_MEMORY;
5544 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5546 if (devpriv->is_m_series) {
5547 s->n_chan = M_SERIES_EEPROM_SIZE;
5548 s->insn_read = ni_m_series_eeprom_insn_read;
5551 s->insn_read = ni_eeprom_insn_read;
5554 /* Digital I/O (PFI) subdevice */
5555 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5556 s->type = COMEDI_SUBD_DIO;
5557 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5559 if (devpriv->is_m_series) {
5561 s->insn_bits = ni_pfi_insn_bits;
5563 ni_writew(dev, s->state, M_Offset_PFI_DO);
5564 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5565 ni_writew(dev, devpriv->pfi_output_select_reg[i],
5566 M_Offset_PFI_Output_Select(i + 1));
5571 s->insn_config = ni_pfi_insn_config;
5573 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
5575 /* cs5529 calibration adc */
5576 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5577 if (devpriv->is_67xx) {
5578 s->type = COMEDI_SUBD_AI;
5579 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5580 /* one channel for each analog output channel */
5581 s->n_chan = board->n_aochan;
5582 s->maxdata = (1 << 16) - 1;
5583 s->range_table = &range_unknown; /* XXX */
5584 s->insn_read = cs5529_ai_insn_read;
5585 s->insn_config = NULL;
5588 s->type = COMEDI_SUBD_UNUSED;
5592 s = &dev->subdevices[NI_SERIAL_SUBDEV];
5593 s->type = COMEDI_SUBD_SERIAL;
5594 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5597 s->insn_config = ni_serial_insn_config;
5598 devpriv->serial_interval_ns = 0;
5599 devpriv->serial_hw_mode = 0;
5602 s = &dev->subdevices[NI_RTSI_SUBDEV];
5603 s->type = COMEDI_SUBD_DIO;
5604 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5607 s->insn_bits = ni_rtsi_insn_bits;
5608 s->insn_config = ni_rtsi_insn_config;
5611 /* allocate and initialize the gpct counter device */
5612 devpriv->counter_dev = ni_gpct_device_construct(dev,
5613 ni_gpct_write_register,
5614 ni_gpct_read_register,
5615 (devpriv->is_m_series)
5616 ? ni_gpct_variant_m_series
5617 : ni_gpct_variant_e_series,
5619 if (!devpriv->counter_dev)
5622 /* Counter (gpct) subdevices */
5623 for (i = 0; i < NUM_GPCT; ++i) {
5624 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5626 /* setup and initialize the counter */
5627 gpct->chip_index = 0;
5628 gpct->counter_index = i;
5629 ni_tio_init_counter(gpct);
5631 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5632 s->type = COMEDI_SUBD_COUNTER;
5633 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5635 s->maxdata = (devpriv->is_m_series) ? 0xffffffff
5637 s->insn_read = ni_tio_insn_read;
5638 s->insn_write = ni_tio_insn_read;
5639 s->insn_config = ni_tio_insn_config;
5641 if (dev->irq && devpriv->mite) {
5642 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5643 s->len_chanlist = 1;
5644 s->do_cmdtest = ni_tio_cmdtest;
5645 s->do_cmd = ni_gpct_cmd;
5646 s->cancel = ni_gpct_cancel;
5648 s->async_dma_dir = DMA_BIDIRECTIONAL;
5654 /* Frequency output subdevice */
5655 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5656 s->type = COMEDI_SUBD_COUNTER;
5657 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5660 s->insn_read = ni_freq_out_insn_read;
5661 s->insn_write = ni_freq_out_insn_write;
5662 s->insn_config = ni_freq_out_insn_config;
5666 (irq_polarity ? Interrupt_Output_Polarity : 0) |
5667 (Interrupt_Output_On_3_Pins & 0) |
5668 Interrupt_A_Enable | Interrupt_B_Enable |
5669 Interrupt_A_Output_Select(interrupt_pin) |
5670 Interrupt_B_Output_Select(interrupt_pin),
5671 Interrupt_Control_Register);
5675 ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select);
5676 ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select);
5678 if (devpriv->is_6xxx) {
5679 ni_writeb(dev, 0, Magic_611x);
5680 } else if (devpriv->is_m_series) {
5683 for (channel = 0; channel < board->n_aochan; ++channel) {
5685 M_Offset_AO_Waveform_Order(channel));
5687 M_Offset_AO_Reference_Attenuation(channel));
5689 ni_writeb(dev, 0x0, M_Offset_AO_Calibration);
5695 static void mio_common_detach(struct comedi_device *dev)
5697 struct ni_private *devpriv = dev->private;
5700 if (devpriv->counter_dev)
5701 ni_gpct_device_destroy(devpriv->counter_dev);