kernel/include/linux/mfd/tps65912.h

   1 /*
   2  * tps65912.h  --  TI TPS6591x
   3  *
   4  * Copyright 2011 Texas Instruments Inc.
   5  *
   6  * Author: Margarita Olaya <magi@slimlogic.co.uk>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under  the terms of the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the License, or (at your
  11  *  option) any later version.
  12  *
  13  */
  14
  15 #ifndef __LINUX_MFD_TPS65912_H
  16 #define __LINUX_MFD_TPS65912_H
  17
  18 /* TPS regulator type list */
  19 #define REGULATOR_LDO           0
  20 #define REGULATOR_DCDC          1
  21
  22 /*
  23  * List of registers for TPS65912
  24  */
  25
  26 #define TPS65912_DCDC1_CTRL             0x00
  27 #define TPS65912_DCDC2_CTRL             0x01
  28 #define TPS65912_DCDC3_CTRL             0x02
  29 #define TPS65912_DCDC4_CTRL             0x03
  30 #define TPS65912_DCDC1_OP               0x04
  31 #define TPS65912_DCDC1_AVS              0x05
  32 #define TPS65912_DCDC1_LIMIT            0x06
  33 #define TPS65912_DCDC2_OP               0x07
  34 #define TPS65912_DCDC2_AVS              0x08
  35 #define TPS65912_DCDC2_LIMIT            0x09
  36 #define TPS65912_DCDC3_OP               0x0A
  37 #define TPS65912_DCDC3_AVS              0x0B
  38 #define TPS65912_DCDC3_LIMIT            0x0C
  39 #define TPS65912_DCDC4_OP               0x0D
  40 #define TPS65912_DCDC4_AVS              0x0E
  41 #define TPS65912_DCDC4_LIMIT            0x0F
  42 #define TPS65912_LDO1_OP                0x10
  43 #define TPS65912_LDO1_AVS               0x11
  44 #define TPS65912_LDO1_LIMIT             0x12
  45 #define TPS65912_LDO2_OP                0x13
  46 #define TPS65912_LDO2_AVS               0x14
  47 #define TPS65912_LDO2_LIMIT             0x15
  48 #define TPS65912_LDO3_OP                0x16
  49 #define TPS65912_LDO3_AVS               0x17
  50 #define TPS65912_LDO3_LIMIT             0x18
  51 #define TPS65912_LDO4_OP                0x19
  52 #define TPS65912_LDO4_AVS               0x1A
  53 #define TPS65912_LDO4_LIMIT             0x1B
  54 #define TPS65912_LDO5                   0x1C
  55 #define TPS65912_LDO6                   0x1D
  56 #define TPS65912_LDO7                   0x1E
  57 #define TPS65912_LDO8                   0x1F
  58 #define TPS65912_LDO9                   0x20
  59 #define TPS65912_LDO10                  0x21
  60 #define TPS65912_THRM                   0x22
  61 #define TPS65912_CLK32OUT               0x23
  62 #define TPS65912_DEVCTRL                0x24
  63 #define TPS65912_DEVCTRL2               0x25
  64 #define TPS65912_I2C_SPI_CFG            0x26
  65 #define TPS65912_KEEP_ON                0x27
  66 #define TPS65912_KEEP_ON2               0x28
  67 #define TPS65912_SET_OFF1               0x29
  68 #define TPS65912_SET_OFF2               0x2A
  69 #define TPS65912_DEF_VOLT               0x2B
  70 #define TPS65912_DEF_VOLT_MAPPING       0x2C
  71 #define TPS65912_DISCHARGE              0x2D
  72 #define TPS65912_DISCHARGE2             0x2E
  73 #define TPS65912_EN1_SET1               0x2F
  74 #define TPS65912_EN1_SET2               0x30
  75 #define TPS65912_EN2_SET1               0x31
  76 #define TPS65912_EN2_SET2               0x32
  77 #define TPS65912_EN3_SET1               0x33
  78 #define TPS65912_EN3_SET2               0x34
  79 #define TPS65912_EN4_SET1               0x35
  80 #define TPS65912_EN4_SET2               0x36
  81 #define TPS65912_PGOOD                  0x37
  82 #define TPS65912_PGOOD2                 0x38
  83 #define TPS65912_INT_STS                0x39
  84 #define TPS65912_INT_MSK                0x3A
  85 #define TPS65912_INT_STS2               0x3B
  86 #define TPS65912_INT_MSK2               0x3C
  87 #define TPS65912_INT_STS3               0x3D
  88 #define TPS65912_INT_MSK3               0x3E
  89 #define TPS65912_INT_STS4               0x3F
  90 #define TPS65912_INT_MSK4               0x40
  91 #define TPS65912_GPIO1                  0x41
  92 #define TPS65912_GPIO2                  0x42
  93 #define TPS65912_GPIO3                  0x43
  94 #define TPS65912_GPIO4                  0x44
  95 #define TPS65912_GPIO5                  0x45
  96 #define TPS65912_VMON                   0x46
  97 #define TPS65912_LEDA_CTRL1             0x47
  98 #define TPS65912_LEDA_CTRL2             0x48
  99 #define TPS65912_LEDA_CTRL3             0x49
 100 #define TPS65912_LEDA_CTRL4             0x4A
 101 #define TPS65912_LEDA_CTRL5             0x4B
 102 #define TPS65912_LEDA_CTRL6             0x4C
 103 #define TPS65912_LEDA_CTRL7             0x4D
 104 #define TPS65912_LEDA_CTRL8             0x4E
 105 #define TPS65912_LEDB_CTRL1             0x4F
 106 #define TPS65912_LEDB_CTRL2             0x50
 107 #define TPS65912_LEDB_CTRL3             0x51
 108 #define TPS65912_LEDB_CTRL4             0x52
 109 #define TPS65912_LEDB_CTRL5             0x53
 110 #define TPS65912_LEDB_CTRL6             0x54
 111 #define TPS65912_LEDB_CTRL7             0x55
 112 #define TPS65912_LEDB_CTRL8             0x56
 113 #define TPS65912_LEDC_CTRL1             0x57
 114 #define TPS65912_LEDC_CTRL2             0x58
 115 #define TPS65912_LEDC_CTRL3             0x59
 116 #define TPS65912_LEDC_CTRL4             0x5A
 117 #define TPS65912_LEDC_CTRL5             0x5B
 118 #define TPS65912_LEDC_CTRL6             0x5C
 119 #define TPS65912_LEDC_CTRL7             0x5D
 120 #define TPS65912_LEDC_CTRL8             0x5E
 121 #define TPS65912_LED_RAMP_UP_TIME       0x5F
 122 #define TPS65912_LED_RAMP_DOWN_TIME     0x60
 123 #define TPS65912_LED_SEQ_EN             0x61
 124 #define TPS65912_LOADSWITCH             0x62
 125 #define TPS65912_SPARE                  0x63
 126 #define TPS65912_VERNUM                 0x64
 127 #define TPS6591X_MAX_REGISTER           0x64
 128
 129 /* IRQ Definitions */
 130 #define TPS65912_IRQ_PWRHOLD_F          0
 131 #define TPS65912_IRQ_VMON               1
 132 #define TPS65912_IRQ_PWRON              2
 133 #define TPS65912_IRQ_PWRON_LP           3
 134 #define TPS65912_IRQ_PWRHOLD_R          4
 135 #define TPS65912_IRQ_HOTDIE             5
 136 #define TPS65912_IRQ_GPIO1_R            6
 137 #define TPS65912_IRQ_GPIO1_F            7
 138 #define TPS65912_IRQ_GPIO2_R            8
 139 #define TPS65912_IRQ_GPIO2_F            9
 140 #define TPS65912_IRQ_GPIO3_R            10
 141 #define TPS65912_IRQ_GPIO3_F            11
 142 #define TPS65912_IRQ_GPIO4_R            12
 143 #define TPS65912_IRQ_GPIO4_F            13
 144 #define TPS65912_IRQ_GPIO5_R            14
 145 #define TPS65912_IRQ_GPIO5_F            15
 146 #define TPS65912_IRQ_PGOOD_DCDC1        16
 147 #define TPS65912_IRQ_PGOOD_DCDC2        17
 148 #define TPS65912_IRQ_PGOOD_DCDC3        18
 149 #define TPS65912_IRQ_PGOOD_DCDC4        19
 150 #define TPS65912_IRQ_PGOOD_LDO1         20
 151 #define TPS65912_IRQ_PGOOD_LDO2         21
 152 #define TPS65912_IRQ_PGOOD_LDO3         22
 153 #define TPS65912_IRQ_PGOOD_LDO4         23
 154 #define TPS65912_IRQ_PGOOD_LDO5         24
 155 #define TPS65912_IRQ_PGOOD_LDO6         25
 156 #define TPS65912_IRQ_PGOOD_LDO7         26
 157 #define TPS65912_IRQ_PGOOD_LD08         27
 158 #define TPS65912_IRQ_PGOOD_LDO9         28
 159 #define TPS65912_IRQ_PGOOD_LDO10        29
 160
 161 #define TPS65912_NUM_IRQ                30
 162
 163 /* GPIO 1 and 2 Register Definitions */
 164 #define GPIO_SLEEP_MASK                 0x80
 165 #define GPIO_SLEEP_SHIFT                7
 166 #define GPIO_DEB_MASK                   0x10
 167 #define GPIO_DEB_SHIFT                  4
 168 #define GPIO_CFG_MASK                   0x04
 169 #define GPIO_CFG_SHIFT                  2
 170 #define GPIO_STS_MASK                   0x02
 171 #define GPIO_STS_SHIFT                  1
 172 #define GPIO_SET_MASK                   0x01
 173 #define GPIO_SET_SHIFT                  0
 174
 175 /* GPIO 3 Register Definitions */
 176 #define GPIO3_SLEEP_MASK                0x80
 177 #define GPIO3_SLEEP_SHIFT               7
 178 #define GPIO3_SEL_MASK                  0x40
 179 #define GPIO3_SEL_SHIFT                 6
 180 #define GPIO3_ODEN_MASK                 0x20
 181 #define GPIO3_ODEN_SHIFT                5
 182 #define GPIO3_DEB_MASK                  0x10
 183 #define GPIO3_DEB_SHIFT                 4
 184 #define GPIO3_PDEN_MASK                 0x08
 185 #define GPIO3_PDEN_SHIFT                3
 186 #define GPIO3_CFG_MASK                  0x04
 187 #define GPIO3_CFG_SHIFT                 2
 188 #define GPIO3_STS_MASK                  0x02
 189 #define GPIO3_STS_SHIFT                 1
 190 #define GPIO3_SET_MASK                  0x01
 191 #define GPIO3_SET_SHIFT                 0
 192
 193 /* GPIO 4 Register Definitions */
 194 #define GPIO4_SLEEP_MASK                0x80
 195 #define GPIO4_SLEEP_SHIFT               7
 196 #define GPIO4_SEL_MASK                  0x40
 197 #define GPIO4_SEL_SHIFT                 6
 198 #define GPIO4_ODEN_MASK                 0x20
 199 #define GPIO4_ODEN_SHIFT                5
 200 #define GPIO4_DEB_MASK                  0x10
 201 #define GPIO4_DEB_SHIFT                 4
 202 #define GPIO4_PDEN_MASK                 0x08
 203 #define GPIO4_PDEN_SHIFT                3
 204 #define GPIO4_CFG_MASK                  0x04
 205 #define GPIO4_CFG_SHIFT                 2
 206 #define GPIO4_STS_MASK                  0x02
 207 #define GPIO4_STS_SHIFT                 1
 208 #define GPIO4_SET_MASK                  0x01
 209 #define GPIO4_SET_SHIFT                 0
 210
 211 /* Register THERM  (0x80) register.RegisterDescription */
 212 #define THERM_THERM_HD_MASK             0x20
 213 #define THERM_THERM_HD_SHIFT            5
 214 #define THERM_THERM_TS_MASK             0x10
 215 #define THERM_THERM_TS_SHIFT            4
 216 #define THERM_THERM_HDSEL_MASK          0x0C
 217 #define THERM_THERM_HDSEL_SHIFT         2
 218 #define THERM_RSVD1_MASK                0x02
 219 #define THERM_RSVD1_SHIFT               1
 220 #define THERM_THERM_STATE_MASK          0x01
 221 #define THERM_THERM_STATE_SHIFT         0
 222
 223 /* Register DCDCCTRL1 register.RegisterDescription */
 224 #define DCDCCTRL_VCON_ENABLE_MASK       0x80
 225 #define DCDCCTRL_VCON_ENABLE_SHIFT      7
 226 #define DCDCCTRL_VCON_RANGE1_MASK       0x40
 227 #define DCDCCTRL_VCON_RANGE1_SHIFT      6
 228 #define DCDCCTRL_VCON_RANGE0_MASK       0x20
 229 #define DCDCCTRL_VCON_RANGE0_SHIFT      5
 230 #define DCDCCTRL_TSTEP2_MASK            0x10
 231 #define DCDCCTRL_TSTEP2_SHIFT           4
 232 #define DCDCCTRL_TSTEP1_MASK            0x08
 233 #define DCDCCTRL_TSTEP1_SHIFT           3
 234 #define DCDCCTRL_TSTEP0_MASK            0x04
 235 #define DCDCCTRL_TSTEP0_SHIFT           2
 236 #define DCDCCTRL_DCDC1_MODE_MASK        0x02
 237 #define DCDCCTRL_DCDC1_MODE_SHIFT       1
 238
 239 /* Register DCDCCTRL2 and DCDCCTRL3 register.RegisterDescription */
 240 #define DCDCCTRL_TSTEP2_MASK            0x10
 241 #define DCDCCTRL_TSTEP2_SHIFT           4
 242 #define DCDCCTRL_TSTEP1_MASK            0x08
 243 #define DCDCCTRL_TSTEP1_SHIFT           3
 244 #define DCDCCTRL_TSTEP0_MASK            0x04
 245 #define DCDCCTRL_TSTEP0_SHIFT           2
 246 #define DCDCCTRL_DCDC_MODE_MASK         0x02
 247 #define DCDCCTRL_DCDC_MODE_SHIFT        1
 248 #define DCDCCTRL_RSVD0_MASK             0x01
 249 #define DCDCCTRL_RSVD0_SHIFT            0
 250
 251 /* Register DCDCCTRL4 register.RegisterDescription */
 252 #define DCDCCTRL_RAMP_TIME_MASK         0x01
 253 #define DCDCCTRL_RAMP_TIME_SHIFT        0
 254
 255 /* Register DCDCx_AVS */
 256 #define DCDC_AVS_ENABLE_MASK            0x80
 257 #define DCDC_AVS_ENABLE_SHIFT           7
 258 #define DCDC_AVS_ECO_MASK               0x40
 259 #define DCDC_AVS_ECO_SHIFT              6
 260
 261 /* Register DCDCx_LIMIT */
 262 #define DCDC_LIMIT_RANGE_MASK           0xC0
 263 #define DCDC_LIMIT_RANGE_SHIFT          6
 264 #define DCDC_LIMIT_MAX_SEL_MASK         0x3F
 265 #define DCDC_LIMIT_MAX_SEL_SHIFT        0
 266
 267 /**
 268  * struct tps65912_board
 269  * Board platform dat may be used to initialize regulators.
 270  */
 271 struct tps65912_board {
 272         int is_dcdc1_avs;
 273         int is_dcdc2_avs;
 274         int is_dcdc3_avs;
 275         int is_dcdc4_avs;
 276         int irq;
 277         int irq_base;
 278         int gpio_base;
 279         struct regulator_init_data *tps65912_pmic_init_data;
 280 };
 281
 282 /**
 283  * struct tps65912 - tps65912 sub-driver chip access routines
 284  */
 285
 286 struct tps65912 {
 287         struct device *dev;
 288         /* for read/write acces */
 289         struct mutex io_mutex;
 290
 291         /* For device IO interfaces: I2C or SPI */
 292         void *control_data;
 293
 294         int (*read)(struct tps65912 *tps65912, u8 reg, int size, void *dest);
 295         int (*write)(struct tps65912 *tps65912, u8 reg, int size, void *src);
 296
 297         /* Client devices */
 298         struct tps65912_pmic *pmic;
 299
 300         /* GPIO Handling */
 301         struct gpio_chip gpio;
 302
 303         /* IRQ Handling */
 304         struct mutex irq_lock;
 305         int chip_irq;
 306         int irq_base;
 307         int irq_num;
 308         u32 irq_mask;
 309 };
 310
 311 struct tps65912_platform_data {
 312         int irq;
 313         int irq_base;
 314 };
 315
 316 unsigned int tps_chip(void);
 317
 318 int tps65912_set_bits(struct tps65912 *tps65912, u8 reg, u8 mask);
 319 int tps65912_clear_bits(struct tps65912 *tps65912, u8 reg, u8 mask);
 320 int tps65912_reg_read(struct tps65912 *tps65912, u8 reg);
 321 int tps65912_reg_write(struct tps65912 *tps65912, u8 reg, u8 val);
 322 int tps65912_device_init(struct tps65912 *tps65912);
 323 void tps65912_device_exit(struct tps65912 *tps65912);
 324 int tps65912_irq_init(struct tps65912 *tps65912, int irq,
 325                         struct tps65912_platform_data *pdata);
 326 int tps65912_irq_exit(struct tps65912 *tps65912);
 327
 328 #endif /*  __LINUX_MFD_TPS65912_H */