5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
12 #include <linux/smp.h>
13 #include <linux/linkage.h>
14 #include <linux/cache.h>
15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h>
17 #include <linux/gfp.h>
18 #include <linux/irqhandler.h>
19 #include <linux/irqreturn.h>
20 #include <linux/irqnr.h>
21 #include <linux/errno.h>
22 #include <linux/topology.h>
23 #include <linux/wait.h>
27 #include <asm/ptrace.h>
28 #include <asm/irq_regs.h>
33 enum irqchip_irq_state;
38 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
40 * IRQ_TYPE_NONE - default, unspecified type
41 * IRQ_TYPE_EDGE_RISING - rising edge triggered
42 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
43 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
44 * IRQ_TYPE_LEVEL_HIGH - high level triggered
45 * IRQ_TYPE_LEVEL_LOW - low level triggered
46 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
47 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
48 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
49 * to setup the HW to a sane default (used
50 * by irqdomain map() callbacks to synchronize
51 * the HW state and SW flags for a newly
52 * allocated descriptor).
54 * IRQ_TYPE_PROBE - Special flag for probing in progress
56 * Bits which can be modified via irq_set/clear/modify_status_flags()
57 * IRQ_LEVEL - Interrupt is level type. Will be also
58 * updated in the code when the above trigger
59 * bits are modified via irq_set_irq_type()
60 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
61 * it from affinity setting
62 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
63 * IRQ_NOREQUEST - Interrupt cannot be requested via
65 * IRQ_NOTHREAD - Interrupt cannot be threaded
66 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
68 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
69 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
70 * IRQ_NESTED_THREAD - Interrupt nests into another thread
71 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
72 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
73 * it from the spurious interrupt detection
74 * mechanism and from core side polling.
75 * IRQ_NO_SOFTIRQ_CALL - No softirq processing in the irq thread context (RT)
76 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
79 IRQ_TYPE_NONE = 0x00000000,
80 IRQ_TYPE_EDGE_RISING = 0x00000001,
81 IRQ_TYPE_EDGE_FALLING = 0x00000002,
82 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
83 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
84 IRQ_TYPE_LEVEL_LOW = 0x00000008,
85 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
86 IRQ_TYPE_SENSE_MASK = 0x0000000f,
87 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
89 IRQ_TYPE_PROBE = 0x00000010,
92 IRQ_PER_CPU = (1 << 9),
93 IRQ_NOPROBE = (1 << 10),
94 IRQ_NOREQUEST = (1 << 11),
95 IRQ_NOAUTOEN = (1 << 12),
96 IRQ_NO_BALANCING = (1 << 13),
97 IRQ_MOVE_PCNTXT = (1 << 14),
98 IRQ_NESTED_THREAD = (1 << 15),
99 IRQ_NOTHREAD = (1 << 16),
100 IRQ_PER_CPU_DEVID = (1 << 17),
101 IRQ_IS_POLLED = (1 << 18),
102 IRQ_DISABLE_UNLAZY = (1 << 19),
103 IRQ_NO_SOFTIRQ_CALL = (1 << 20),
106 #define IRQF_MODIFY_MASK \
107 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
108 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
109 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
110 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_NO_SOFTIRQ_CALL)
112 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
115 * Return value for chip->irq_set_affinity()
117 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
118 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
119 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
120 * support stacked irqchips, which indicates skipping
121 * all descendent irqchips.
125 IRQ_SET_MASK_OK_NOCOPY,
126 IRQ_SET_MASK_OK_DONE,
133 * struct irq_common_data - per irq data shared by all irqchips
134 * @state_use_accessors: status information for irq chip functions.
135 * Use accessor functions to deal with it
136 * @node: node index useful for balancing
137 * @handler_data: per-IRQ data for the irq_chip methods
138 * @affinity: IRQ affinity on SMP
139 * @msi_desc: MSI descriptor
141 struct irq_common_data {
142 unsigned int state_use_accessors;
147 struct msi_desc *msi_desc;
148 cpumask_var_t affinity;
152 * struct irq_data - per irq chip data passed down to chip functions
153 * @mask: precomputed bitmask for accessing the chip registers
154 * @irq: interrupt number
155 * @hwirq: hardware interrupt number, local to the interrupt domain
156 * @common: point to data shared by all irqchips
157 * @chip: low level interrupt hardware access
158 * @domain: Interrupt translation domain; responsible for mapping
159 * between hwirq number and linux irq number.
160 * @parent_data: pointer to parent struct irq_data to support hierarchy
162 * @chip_data: platform-specific per-chip private data for the chip
163 * methods, to allow shared chip implementations
169 struct irq_common_data *common;
170 struct irq_chip *chip;
171 struct irq_domain *domain;
172 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
173 struct irq_data *parent_data;
179 * Bit masks for irq_common_data.state_use_accessors
181 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
182 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
183 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
184 * IRQD_PER_CPU - Interrupt is per cpu
185 * IRQD_AFFINITY_SET - Interrupt affinity was set
186 * IRQD_LEVEL - Interrupt is level triggered
187 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
189 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
191 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
192 * IRQD_IRQ_MASKED - Masked state of the interrupt
193 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
194 * IRQD_WAKEUP_ARMED - Wakeup mode armed
195 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
198 IRQD_TRIGGER_MASK = 0xf,
199 IRQD_SETAFFINITY_PENDING = (1 << 8),
200 IRQD_NO_BALANCING = (1 << 10),
201 IRQD_PER_CPU = (1 << 11),
202 IRQD_AFFINITY_SET = (1 << 12),
203 IRQD_LEVEL = (1 << 13),
204 IRQD_WAKEUP_STATE = (1 << 14),
205 IRQD_MOVE_PCNTXT = (1 << 15),
206 IRQD_IRQ_DISABLED = (1 << 16),
207 IRQD_IRQ_MASKED = (1 << 17),
208 IRQD_IRQ_INPROGRESS = (1 << 18),
209 IRQD_WAKEUP_ARMED = (1 << 19),
210 IRQD_FORWARDED_TO_VCPU = (1 << 20),
213 #define __irqd_to_state(d) ((d)->common->state_use_accessors)
215 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
217 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
220 static inline bool irqd_is_per_cpu(struct irq_data *d)
222 return __irqd_to_state(d) & IRQD_PER_CPU;
225 static inline bool irqd_can_balance(struct irq_data *d)
227 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
230 static inline bool irqd_affinity_was_set(struct irq_data *d)
232 return __irqd_to_state(d) & IRQD_AFFINITY_SET;
235 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
237 __irqd_to_state(d) |= IRQD_AFFINITY_SET;
240 static inline u32 irqd_get_trigger_type(struct irq_data *d)
242 return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
246 * Must only be called inside irq_chip.irq_set_type() functions.
248 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
250 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
251 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
254 static inline bool irqd_is_level_type(struct irq_data *d)
256 return __irqd_to_state(d) & IRQD_LEVEL;
259 static inline bool irqd_is_wakeup_set(struct irq_data *d)
261 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
264 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
266 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
269 static inline bool irqd_irq_disabled(struct irq_data *d)
271 return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
274 static inline bool irqd_irq_masked(struct irq_data *d)
276 return __irqd_to_state(d) & IRQD_IRQ_MASKED;
279 static inline bool irqd_irq_inprogress(struct irq_data *d)
281 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
284 static inline bool irqd_is_wakeup_armed(struct irq_data *d)
286 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
289 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
291 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
294 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
296 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
299 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
301 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
304 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
310 * struct irq_chip - hardware interrupt chip descriptor
312 * @name: name for /proc/interrupts
313 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
314 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
315 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
316 * @irq_disable: disable the interrupt
317 * @irq_ack: start of a new interrupt
318 * @irq_mask: mask an interrupt source
319 * @irq_mask_ack: ack and mask an interrupt source
320 * @irq_unmask: unmask an interrupt source
321 * @irq_eoi: end of interrupt
322 * @irq_set_affinity: set the CPU affinity on SMP machines
323 * @irq_retrigger: resend an IRQ to the CPU
324 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
325 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
326 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
327 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
328 * @irq_cpu_online: configure an interrupt source for a secondary CPU
329 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
330 * @irq_suspend: function called from core code on suspend once per
331 * chip, when one or more interrupts are installed
332 * @irq_resume: function called from core code on resume once per chip,
333 * when one ore more interrupts are installed
334 * @irq_pm_shutdown: function called from core code on shutdown once per chip
335 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
336 * @irq_print_chip: optional to print special chip info in show_interrupts
337 * @irq_request_resources: optional to request resources before calling
338 * any other callback related to this irq
339 * @irq_release_resources: optional to release resources acquired with
340 * irq_request_resources
341 * @irq_compose_msi_msg: optional to compose message content for MSI
342 * @irq_write_msi_msg: optional to write message content for MSI
343 * @irq_get_irqchip_state: return the internal state of an interrupt
344 * @irq_set_irqchip_state: set the internal state of a interrupt
345 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
346 * @flags: chip specific flags
350 unsigned int (*irq_startup)(struct irq_data *data);
351 void (*irq_shutdown)(struct irq_data *data);
352 void (*irq_enable)(struct irq_data *data);
353 void (*irq_disable)(struct irq_data *data);
355 void (*irq_ack)(struct irq_data *data);
356 void (*irq_mask)(struct irq_data *data);
357 void (*irq_mask_ack)(struct irq_data *data);
358 void (*irq_unmask)(struct irq_data *data);
359 void (*irq_eoi)(struct irq_data *data);
361 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
362 int (*irq_retrigger)(struct irq_data *data);
363 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
364 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
366 void (*irq_bus_lock)(struct irq_data *data);
367 void (*irq_bus_sync_unlock)(struct irq_data *data);
369 void (*irq_cpu_online)(struct irq_data *data);
370 void (*irq_cpu_offline)(struct irq_data *data);
372 void (*irq_suspend)(struct irq_data *data);
373 void (*irq_resume)(struct irq_data *data);
374 void (*irq_pm_shutdown)(struct irq_data *data);
376 void (*irq_calc_mask)(struct irq_data *data);
378 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
379 int (*irq_request_resources)(struct irq_data *data);
380 void (*irq_release_resources)(struct irq_data *data);
382 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
383 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
385 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
386 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
388 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
394 * irq_chip specific flags
396 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
397 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
398 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
399 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
401 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
402 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
403 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
406 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
407 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
408 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
409 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
410 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
411 IRQCHIP_ONESHOT_SAFE = (1 << 5),
412 IRQCHIP_EOI_THREADED = (1 << 6),
415 #include <linux/irqdesc.h>
418 * Pick up the arch-dependent methods:
420 #include <asm/hw_irq.h>
422 #ifndef NR_IRQS_LEGACY
423 # define NR_IRQS_LEGACY 0
426 #ifndef ARCH_IRQ_INIT_FLAGS
427 # define ARCH_IRQ_INIT_FLAGS 0
430 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
433 extern int setup_irq(unsigned int irq, struct irqaction *new);
434 extern void remove_irq(unsigned int irq, struct irqaction *act);
435 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
436 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
438 extern void irq_cpu_online(void);
439 extern void irq_cpu_offline(void);
440 extern int irq_set_affinity_locked(struct irq_data *data,
441 const struct cpumask *cpumask, bool force);
442 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
444 extern void irq_migrate_all_off_this_cpu(void);
446 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
447 void irq_move_irq(struct irq_data *data);
448 void irq_move_masked_irq(struct irq_data *data);
450 static inline void irq_move_irq(struct irq_data *data) { }
451 static inline void irq_move_masked_irq(struct irq_data *data) { }
454 extern int no_irq_affinity;
456 #ifdef CONFIG_HARDIRQS_SW_RESEND
457 int irq_set_parent(int irq, int parent_irq);
459 static inline int irq_set_parent(int irq, int parent_irq)
466 * Built-in IRQ handlers for various IRQ types,
467 * callable via desc->handle_irq()
469 extern void handle_level_irq(struct irq_desc *desc);
470 extern void handle_fasteoi_irq(struct irq_desc *desc);
471 extern void handle_edge_irq(struct irq_desc *desc);
472 extern void handle_edge_eoi_irq(struct irq_desc *desc);
473 extern void handle_simple_irq(struct irq_desc *desc);
474 extern void handle_percpu_irq(struct irq_desc *desc);
475 extern void handle_percpu_devid_irq(struct irq_desc *desc);
476 extern void handle_bad_irq(struct irq_desc *desc);
477 extern void handle_nested_irq(unsigned int irq);
479 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
480 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
481 extern void irq_chip_enable_parent(struct irq_data *data);
482 extern void irq_chip_disable_parent(struct irq_data *data);
483 extern void irq_chip_ack_parent(struct irq_data *data);
484 extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
485 extern void irq_chip_mask_parent(struct irq_data *data);
486 extern void irq_chip_unmask_parent(struct irq_data *data);
487 extern void irq_chip_eoi_parent(struct irq_data *data);
488 extern int irq_chip_set_affinity_parent(struct irq_data *data,
489 const struct cpumask *dest,
491 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
492 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
494 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
497 /* Handling of unhandled and spurious interrupts: */
498 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
501 /* Enable/disable irq debugging output: */
502 extern int noirqdebug_setup(char *str);
504 /* Checks whether the interrupt can be requested by request_irq(): */
505 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
507 /* Dummy irq-chip implementations: */
508 extern struct irq_chip no_irq_chip;
509 extern struct irq_chip dummy_irq_chip;
512 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
513 irq_flow_handler_t handle, const char *name);
515 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
516 irq_flow_handler_t handle)
518 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
521 extern int irq_set_percpu_devid(unsigned int irq);
524 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
528 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
530 __irq_set_handler(irq, handle, 0, NULL);
534 * Set a highlevel chained flow handler for a given IRQ.
535 * (a chained handler is automatically enabled and set to
536 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
539 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
541 __irq_set_handler(irq, handle, 1, NULL);
545 * Set a highlevel chained flow handler and its data for a given IRQ.
546 * (a chained handler is automatically enabled and set to
547 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
550 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
553 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
555 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
557 irq_modify_status(irq, 0, set);
560 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
562 irq_modify_status(irq, clr, 0);
565 static inline void irq_set_noprobe(unsigned int irq)
567 irq_modify_status(irq, 0, IRQ_NOPROBE);
570 static inline void irq_set_probe(unsigned int irq)
572 irq_modify_status(irq, IRQ_NOPROBE, 0);
575 static inline void irq_set_nothread(unsigned int irq)
577 irq_modify_status(irq, 0, IRQ_NOTHREAD);
580 static inline void irq_set_thread(unsigned int irq)
582 irq_modify_status(irq, IRQ_NOTHREAD, 0);
585 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
588 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
590 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
593 static inline void irq_set_percpu_devid_flags(unsigned int irq)
595 irq_set_status_flags(irq,
596 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
597 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
600 /* Set/get chip/data for an IRQ: */
601 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
602 extern int irq_set_handler_data(unsigned int irq, void *data);
603 extern int irq_set_chip_data(unsigned int irq, void *data);
604 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
605 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
606 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
607 struct msi_desc *entry);
608 extern struct irq_data *irq_get_irq_data(unsigned int irq);
610 static inline struct irq_chip *irq_get_chip(unsigned int irq)
612 struct irq_data *d = irq_get_irq_data(irq);
613 return d ? d->chip : NULL;
616 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
621 static inline void *irq_get_chip_data(unsigned int irq)
623 struct irq_data *d = irq_get_irq_data(irq);
624 return d ? d->chip_data : NULL;
627 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
632 static inline void *irq_get_handler_data(unsigned int irq)
634 struct irq_data *d = irq_get_irq_data(irq);
635 return d ? d->common->handler_data : NULL;
638 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
640 return d->common->handler_data;
643 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
645 struct irq_data *d = irq_get_irq_data(irq);
646 return d ? d->common->msi_desc : NULL;
649 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
651 return d->common->msi_desc;
654 static inline u32 irq_get_trigger_type(unsigned int irq)
656 struct irq_data *d = irq_get_irq_data(irq);
657 return d ? irqd_get_trigger_type(d) : 0;
660 static inline int irq_common_data_get_node(struct irq_common_data *d)
669 static inline int irq_data_get_node(struct irq_data *d)
671 return irq_common_data_get_node(d->common);
674 static inline struct cpumask *irq_get_affinity_mask(int irq)
676 struct irq_data *d = irq_get_irq_data(irq);
678 return d ? d->common->affinity : NULL;
681 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
683 return d->common->affinity;
686 unsigned int arch_dynirq_lower_bound(unsigned int from);
688 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
689 struct module *owner);
691 /* use macros to avoid needing export.h for THIS_MODULE */
692 #define irq_alloc_descs(irq, from, cnt, node) \
693 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
695 #define irq_alloc_desc(node) \
696 irq_alloc_descs(-1, 0, 1, node)
698 #define irq_alloc_desc_at(at, node) \
699 irq_alloc_descs(at, at, 1, node)
701 #define irq_alloc_desc_from(from, node) \
702 irq_alloc_descs(-1, from, 1, node)
704 #define irq_alloc_descs_from(from, cnt, node) \
705 irq_alloc_descs(-1, from, cnt, node)
707 void irq_free_descs(unsigned int irq, unsigned int cnt);
708 static inline void irq_free_desc(unsigned int irq)
710 irq_free_descs(irq, 1);
713 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
714 unsigned int irq_alloc_hwirqs(int cnt, int node);
715 static inline unsigned int irq_alloc_hwirq(int node)
717 return irq_alloc_hwirqs(1, node);
719 void irq_free_hwirqs(unsigned int from, int cnt);
720 static inline void irq_free_hwirq(unsigned int irq)
722 return irq_free_hwirqs(irq, 1);
724 int arch_setup_hwirq(unsigned int irq, int node);
725 void arch_teardown_hwirq(unsigned int irq);
728 #ifdef CONFIG_GENERIC_IRQ_LEGACY
729 void irq_init_desc(unsigned int irq);
733 * struct irq_chip_regs - register offsets for struct irq_gci
734 * @enable: Enable register offset to reg_base
735 * @disable: Disable register offset to reg_base
736 * @mask: Mask register offset to reg_base
737 * @ack: Ack register offset to reg_base
738 * @eoi: Eoi register offset to reg_base
739 * @type: Type configuration register offset to reg_base
740 * @polarity: Polarity configuration register offset to reg_base
742 struct irq_chip_regs {
743 unsigned long enable;
744 unsigned long disable;
749 unsigned long polarity;
753 * struct irq_chip_type - Generic interrupt chip instance for a flow type
754 * @chip: The real interrupt chip which provides the callbacks
755 * @regs: Register offsets for this chip
756 * @handler: Flow handler associated with this chip
757 * @type: Chip can handle these flow types
758 * @mask_cache_priv: Cached mask register private to the chip type
759 * @mask_cache: Pointer to cached mask register
761 * A irq_generic_chip can have several instances of irq_chip_type when
762 * it requires different functions and register offsets for different
765 struct irq_chip_type {
766 struct irq_chip chip;
767 struct irq_chip_regs regs;
768 irq_flow_handler_t handler;
775 * struct irq_chip_generic - Generic irq chip data structure
776 * @lock: Lock to protect register and cache data access
777 * @reg_base: Register base address (virtual)
778 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
779 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
780 * @suspend: Function called from core code on suspend once per
781 * chip; can be useful instead of irq_chip::suspend to
782 * handle chip details even when no interrupts are in use
783 * @resume: Function called from core code on resume once per chip;
784 * can be useful instead of irq_chip::suspend to handle
785 * chip details even when no interrupts are in use
786 * @irq_base: Interrupt base nr for this chip
787 * @irq_cnt: Number of interrupts handled by this chip
788 * @mask_cache: Cached mask register shared between all chip types
789 * @type_cache: Cached type register
790 * @polarity_cache: Cached polarity register
791 * @wake_enabled: Interrupt can wakeup from suspend
792 * @wake_active: Interrupt is marked as an wakeup from suspend source
793 * @num_ct: Number of available irq_chip_type instances (usually 1)
794 * @private: Private data for non generic chip callbacks
795 * @installed: bitfield to denote installed interrupts
796 * @unused: bitfield to denote unused interrupts
797 * @domain: irq domain pointer
798 * @list: List head for keeping track of instances
799 * @chip_types: Array of interrupt irq_chip_types
801 * Note, that irq_chip_generic can have multiple irq_chip_type
802 * implementations which can be associated to a particular irq line of
803 * an irq_chip_generic instance. That allows to share and protect
804 * state in an irq_chip_generic instance when we need to implement
805 * different flow mechanisms (level/edge) for it.
807 struct irq_chip_generic {
809 void __iomem *reg_base;
810 u32 (*reg_readl)(void __iomem *addr);
811 void (*reg_writel)(u32 val, void __iomem *addr);
812 void (*suspend)(struct irq_chip_generic *gc);
813 void (*resume)(struct irq_chip_generic *gc);
814 unsigned int irq_base;
815 unsigned int irq_cnt;
823 unsigned long installed;
824 unsigned long unused;
825 struct irq_domain *domain;
826 struct list_head list;
827 struct irq_chip_type chip_types[0];
831 * enum irq_gc_flags - Initialization flags for generic irq chips
832 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
833 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
834 * irq chips which need to call irq_set_wake() on
835 * the parent irq. Usually GPIO implementations
836 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
837 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
838 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
841 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
842 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
843 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
844 IRQ_GC_NO_MASK = 1 << 3,
845 IRQ_GC_BE_IO = 1 << 4,
849 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
850 * @irqs_per_chip: Number of interrupts per chip
851 * @num_chips: Number of chips
852 * @irq_flags_to_set: IRQ* flags to set on irq setup
853 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
854 * @gc_flags: Generic chip specific setup flags
855 * @gc: Array of pointers to generic interrupt chips
857 struct irq_domain_chip_generic {
858 unsigned int irqs_per_chip;
859 unsigned int num_chips;
860 unsigned int irq_flags_to_clear;
861 unsigned int irq_flags_to_set;
862 enum irq_gc_flags gc_flags;
863 struct irq_chip_generic *gc[0];
866 /* Generic chip callback functions */
867 void irq_gc_noop(struct irq_data *d);
868 void irq_gc_mask_disable_reg(struct irq_data *d);
869 void irq_gc_mask_set_bit(struct irq_data *d);
870 void irq_gc_mask_clr_bit(struct irq_data *d);
871 void irq_gc_unmask_enable_reg(struct irq_data *d);
872 void irq_gc_ack_set_bit(struct irq_data *d);
873 void irq_gc_ack_clr_bit(struct irq_data *d);
874 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
875 void irq_gc_eoi(struct irq_data *d);
876 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
878 /* Setup functions for irq_chip_generic */
879 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
880 irq_hw_number_t hw_irq);
881 struct irq_chip_generic *
882 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
883 void __iomem *reg_base, irq_flow_handler_t handler);
884 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
885 enum irq_gc_flags flags, unsigned int clr,
887 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
888 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
889 unsigned int clr, unsigned int set);
891 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
892 int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
893 int num_ct, const char *name,
894 irq_flow_handler_t handler,
895 unsigned int clr, unsigned int set,
896 enum irq_gc_flags flags);
899 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
901 return container_of(d->chip, struct irq_chip_type, chip);
904 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
907 static inline void irq_gc_lock(struct irq_chip_generic *gc)
909 raw_spin_lock(&gc->lock);
912 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
914 raw_spin_unlock(&gc->lock);
917 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
918 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
922 * The irqsave variants are for usage in non interrupt code. Do not use
923 * them in irq_chip callbacks. Use irq_gc_lock() instead.
925 #define irq_gc_lock_irqsave(gc, flags) \
926 raw_spin_lock_irqsave(&(gc)->lock, flags)
928 #define irq_gc_unlock_irqrestore(gc, flags) \
929 raw_spin_unlock_irqrestore(&(gc)->lock, flags)
931 static inline void irq_reg_writel(struct irq_chip_generic *gc,
932 u32 val, int reg_offset)
935 gc->reg_writel(val, gc->reg_base + reg_offset);
937 writel(val, gc->reg_base + reg_offset);
940 static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
944 return gc->reg_readl(gc->reg_base + reg_offset);
946 return readl(gc->reg_base + reg_offset);
949 #endif /* _LINUX_IRQ_H */