kernel/drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/version.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/io.h>
  32 #include <linux/list.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/of.h>
  36 #include <linux/acpi.h>
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include <linux/usb/ch9.h>
  40 #include <linux/usb/gadget.h>
  41 #include <linux/usb/of.h>
  42 #include <linux/usb/otg.h>
  43
  44 #include "platform_data.h"
  45 #include "core.h"
  46 #include "gadget.h"
  47 #include "io.h"
  48
  49 #include "debug.h"
  50
  51 /* -------------------------------------------------------------------------- */
  52
  53 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  54 {
  55         u32 reg;
  56
  57         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  58         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  59         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  60         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  61 }
  62
  63 /**
  64  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  65  * @dwc: pointer to our context structure
  66  */
  67 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  68 {
  69         u32             reg;
  70         int             ret;
  71
  72         /* Before Resetting PHY, put Core in Reset */
  73         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  74         reg |= DWC3_GCTL_CORESOFTRESET;
  75         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  76
  77         /* Assert USB3 PHY reset */
  78         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  79         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  80         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  81
  82         /* Assert USB2 PHY reset */
  83         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  84         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  85         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  86
  87         usb_phy_init(dwc->usb2_phy);
  88         usb_phy_init(dwc->usb3_phy);
  89         ret = phy_init(dwc->usb2_generic_phy);
  90         if (ret < 0)
  91                 return ret;
  92
  93         ret = phy_init(dwc->usb3_generic_phy);
  94         if (ret < 0) {
  95                 phy_exit(dwc->usb2_generic_phy);
  96                 return ret;
  97         }
  98         mdelay(100);
  99
 100         /* Clear USB3 PHY reset */
 101         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 102         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
 103         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 104
 105         /* Clear USB2 PHY reset */
 106         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 107         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
 108         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 109
 110         mdelay(100);
 111
 112         /* After PHYs are stable we can take Core out of reset state */
 113         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 114         reg &= ~DWC3_GCTL_CORESOFTRESET;
 115         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 116
 117         return 0;
 118 }
 119
 120 /**
 121  * dwc3_soft_reset - Issue soft reset
 122  * @dwc: Pointer to our controller context structure
 123  */
 124 static int dwc3_soft_reset(struct dwc3 *dwc)
 125 {
 126         unsigned long timeout;
 127         u32 reg;
 128
 129         timeout = jiffies + msecs_to_jiffies(500);
 130         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 131         do {
 132                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 133                 if (!(reg & DWC3_DCTL_CSFTRST))
 134                         break;
 135
 136                 if (time_after(jiffies, timeout)) {
 137                         dev_err(dwc->dev, "Reset Timed Out\n");
 138                         return -ETIMEDOUT;
 139                 }
 140
 141                 cpu_relax();
 142         } while (true);
 143
 144         return 0;
 145 }
 146
 147 /*
 148  * dwc3_frame_length_adjustment - Adjusts frame length if required
 149  * @dwc3: Pointer to our controller context structure
 150  * @fladj: Value of GFLADJ_30MHZ to adjust frame length
 151  */
 152 static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
 153 {
 154         u32 reg;
 155         u32 dft;
 156
 157         if (dwc->revision < DWC3_REVISION_250A)
 158                 return;
 159
 160         if (fladj == 0)
 161                 return;
 162
 163         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 164         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 165         if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
 166             "request value same as default, ignoring\n")) {
 167                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 168                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
 169                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 170         }
 171 }
 172
 173 /**
 174  * dwc3_free_one_event_buffer - Frees one event buffer
 175  * @dwc: Pointer to our controller context structure
 176  * @evt: Pointer to event buffer to be freed
 177  */
 178 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 179                 struct dwc3_event_buffer *evt)
 180 {
 181         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 182 }
 183
 184 /**
 185  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 186  * @dwc: Pointer to our controller context structure
 187  * @length: size of the event buffer
 188  *
 189  * Returns a pointer to the allocated event buffer structure on success
 190  * otherwise ERR_PTR(errno).
 191  */
 192 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 193                 unsigned length)
 194 {
 195         struct dwc3_event_buffer        *evt;
 196
 197         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 198         if (!evt)
 199                 return ERR_PTR(-ENOMEM);
 200
 201         evt->dwc        = dwc;
 202         evt->length     = length;
 203         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 204                         &evt->dma, GFP_KERNEL);
 205         if (!evt->buf)
 206                 return ERR_PTR(-ENOMEM);
 207
 208         return evt;
 209 }
 210
 211 /**
 212  * dwc3_free_event_buffers - frees all allocated event buffers
 213  * @dwc: Pointer to our controller context structure
 214  */
 215 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 216 {
 217         struct dwc3_event_buffer        *evt;
 218         int i;
 219
 220         for (i = 0; i < dwc->num_event_buffers; i++) {
 221                 evt = dwc->ev_buffs[i];
 222                 if (evt)
 223                         dwc3_free_one_event_buffer(dwc, evt);
 224         }
 225 }
 226
 227 /**
 228  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 229  * @dwc: pointer to our controller context structure
 230  * @length: size of event buffer
 231  *
 232  * Returns 0 on success otherwise negative errno. In the error case, dwc
 233  * may contain some buffers allocated but not all which were requested.
 234  */
 235 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 236 {
 237         int                     num;
 238         int                     i;
 239
 240         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 241         dwc->num_event_buffers = num;
 242
 243         dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
 244                         GFP_KERNEL);
 245         if (!dwc->ev_buffs)
 246                 return -ENOMEM;
 247
 248         for (i = 0; i < num; i++) {
 249                 struct dwc3_event_buffer        *evt;
 250
 251                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 252                 if (IS_ERR(evt)) {
 253                         dev_err(dwc->dev, "can't allocate event buffer\n");
 254                         return PTR_ERR(evt);
 255                 }
 256                 dwc->ev_buffs[i] = evt;
 257         }
 258
 259         return 0;
 260 }
 261
 262 /**
 263  * dwc3_event_buffers_setup - setup our allocated event buffers
 264  * @dwc: pointer to our controller context structure
 265  *
 266  * Returns 0 on success otherwise negative errno.
 267  */
 268 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 269 {
 270         struct dwc3_event_buffer        *evt;
 271         int                             n;
 272
 273         for (n = 0; n < dwc->num_event_buffers; n++) {
 274                 evt = dwc->ev_buffs[n];
 275                 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
 276                                 evt->buf, (unsigned long long) evt->dma,
 277                                 evt->length);
 278
 279                 evt->lpos = 0;
 280
 281                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 282                                 lower_32_bits(evt->dma));
 283                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 284                                 upper_32_bits(evt->dma));
 285                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 286                                 DWC3_GEVNTSIZ_SIZE(evt->length));
 287                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 288         }
 289
 290         return 0;
 291 }
 292
 293 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 294 {
 295         struct dwc3_event_buffer        *evt;
 296         int                             n;
 297
 298         for (n = 0; n < dwc->num_event_buffers; n++) {
 299                 evt = dwc->ev_buffs[n];
 300
 301                 evt->lpos = 0;
 302
 303                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 304                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 305                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
 306                                 | DWC3_GEVNTSIZ_SIZE(0));
 307                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 308         }
 309 }
 310
 311 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 312 {
 313         if (!dwc->has_hibernation)
 314                 return 0;
 315
 316         if (!dwc->nr_scratch)
 317                 return 0;
 318
 319         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 320                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 321         if (!dwc->scratchbuf)
 322                 return -ENOMEM;
 323
 324         return 0;
 325 }
 326
 327 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 328 {
 329         dma_addr_t scratch_addr;
 330         u32 param;
 331         int ret;
 332
 333         if (!dwc->has_hibernation)
 334                 return 0;
 335
 336         if (!dwc->nr_scratch)
 337                 return 0;
 338
 339          /* should never fall here */
 340         if (!WARN_ON(dwc->scratchbuf))
 341                 return 0;
 342
 343         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
 344                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 345                         DMA_BIDIRECTIONAL);
 346         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 347                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 348                 ret = -EFAULT;
 349                 goto err0;
 350         }
 351
 352         dwc->scratch_addr = scratch_addr;
 353
 354         param = lower_32_bits(scratch_addr);
 355
 356         ret = dwc3_send_gadget_generic_command(dwc,
 357                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 358         if (ret < 0)
 359                 goto err1;
 360
 361         param = upper_32_bits(scratch_addr);
 362
 363         ret = dwc3_send_gadget_generic_command(dwc,
 364                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 365         if (ret < 0)
 366                 goto err1;
 367
 368         return 0;
 369
 370 err1:
 371         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 372                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 373
 374 err0:
 375         return ret;
 376 }
 377
 378 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 379 {
 380         if (!dwc->has_hibernation)
 381                 return;
 382
 383         if (!dwc->nr_scratch)
 384                 return;
 385
 386          /* should never fall here */
 387         if (!WARN_ON(dwc->scratchbuf))
 388                 return;
 389
 390         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 391                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 392         kfree(dwc->scratchbuf);
 393 }
 394
 395 static void dwc3_core_num_eps(struct dwc3 *dwc)
 396 {
 397         struct dwc3_hwparams    *parms = &dwc->hwparams;
 398
 399         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 400         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 401
 402         dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
 403                         dwc->num_in_eps, dwc->num_out_eps);
 404 }
 405
 406 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 407 {
 408         struct dwc3_hwparams    *parms = &dwc->hwparams;
 409
 410         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 411         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 412         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 413         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 414         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 415         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 416         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 417         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 418         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 419 }
 420
 421 /**
 422  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 423  * @dwc: Pointer to our controller context structure
 424  *
 425  * Returns 0 on success. The USB PHY interfaces are configured but not
 426  * initialized. The PHY interfaces and the PHYs get initialized together with
 427  * the core in dwc3_core_init.
 428  */
 429 static int dwc3_phy_setup(struct dwc3 *dwc)
 430 {
 431         u32 reg;
 432         int ret;
 433
 434         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 435
 436         /*
 437          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 438          * to '0' during coreConsultant configuration. So default value
 439          * will be '0' when the core is reset. Application needs to set it
 440          * to '1' after the core initialization is completed.
 441          */
 442         if (dwc->revision > DWC3_REVISION_194A)
 443                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 444
 445         if (dwc->u2ss_inp3_quirk)
 446                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 447
 448         if (dwc->req_p1p2p3_quirk)
 449                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 450
 451         if (dwc->del_p1p2p3_quirk)
 452                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 453
 454         if (dwc->del_phy_power_chg_quirk)
 455                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 456
 457         if (dwc->lfps_filter_quirk)
 458                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 459
 460         if (dwc->rx_detect_poll_quirk)
 461                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 462
 463         if (dwc->tx_de_emphasis_quirk)
 464                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 465
 466         if (dwc->dis_u3_susphy_quirk)
 467                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 468
 469         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 470
 471         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 472
 473         /* Select the HS PHY interface */
 474         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 475         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 476                 if (dwc->hsphy_interface &&
 477                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 478                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 479                         break;
 480                 } else if (dwc->hsphy_interface &&
 481                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 482                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 483                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 484                 } else {
 485                         /* Relying on default value. */
 486                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 487                                 break;
 488                 }
 489                 /* FALLTHROUGH */
 490         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 491                 /* Making sure the interface and PHY are operational */
 492                 ret = dwc3_soft_reset(dwc);
 493                 if (ret)
 494                         return ret;
 495
 496                 udelay(1);
 497
 498                 ret = dwc3_ulpi_init(dwc);
 499                 if (ret)
 500                         return ret;
 501                 /* FALLTHROUGH */
 502         default:
 503                 break;
 504         }
 505
 506         /*
 507          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 508          * '0' during coreConsultant configuration. So default value will
 509          * be '0' when the core is reset. Application needs to set it to
 510          * '1' after the core initialization is completed.
 511          */
 512         if (dwc->revision > DWC3_REVISION_194A)
 513                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 514
 515         if (dwc->dis_u2_susphy_quirk)
 516                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 517
 518         if (dwc->dis_enblslpm_quirk)
 519                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 520
 521         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 522
 523         return 0;
 524 }
 525
 526 /**
 527  * dwc3_core_init - Low-level initialization of DWC3 Core
 528  * @dwc: Pointer to our controller context structure
 529  *
 530  * Returns 0 on success otherwise negative errno.
 531  */
 532 static int dwc3_core_init(struct dwc3 *dwc)
 533 {
 534         u32                     hwparams4 = dwc->hwparams.hwparams4;
 535         u32                     reg;
 536         int                     ret;
 537
 538         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 539         /* This should read as U3 followed by revision number */
 540         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 541                 /* Detected DWC_usb3 IP */
 542                 dwc->revision = reg;
 543         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 544                 /* Detected DWC_usb31 IP */
 545                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 546                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 547         } else {
 548                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 549                 ret = -ENODEV;
 550                 goto err0;
 551         }
 552
 553         /*
 554          * Write Linux Version Code to our GUID register so it's easy to figure
 555          * out which kernel version a bug was found.
 556          */
 557         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 558
 559         /* Handle USB2.0-only core configuration */
 560         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 561                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 562                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 563                         dwc->maximum_speed = USB_SPEED_HIGH;
 564         }
 565
 566         /* issue device SoftReset too */
 567         ret = dwc3_soft_reset(dwc);
 568         if (ret)
 569                 goto err0;
 570
 571         ret = dwc3_core_soft_reset(dwc);
 572         if (ret)
 573                 goto err0;
 574
 575         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 576         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 577
 578         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 579         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 580                 /**
 581                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 582                  * issue which would cause xHCI compliance tests to fail.
 583                  *
 584                  * Because of that we cannot enable clock gating on such
 585                  * configurations.
 586                  *
 587                  * Refers to:
 588                  *
 589                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 590                  * SOF/ITP Mode Used
 591                  */
 592                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 593                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 594                                 (dwc->revision >= DWC3_REVISION_210A &&
 595                                 dwc->revision <= DWC3_REVISION_250A))
 596                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 597                 else
 598                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 599                 break;
 600         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 601                 /* enable hibernation here */
 602                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 603
 604                 /*
 605                  * REVISIT Enabling this bit so that host-mode hibernation
 606                  * will work. Device-mode hibernation is not yet implemented.
 607                  */
 608                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 609                 break;
 610         default:
 611                 dev_dbg(dwc->dev, "No power optimization available\n");
 612         }
 613
 614         /* check if current dwc3 is on simulation board */
 615         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 616                 dev_dbg(dwc->dev, "it is on FPGA board\n");
 617                 dwc->is_fpga = true;
 618         }
 619
 620         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 621                         "disable_scramble cannot be used on non-FPGA builds\n");
 622
 623         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 624                 reg |= DWC3_GCTL_DISSCRAMBLE;
 625         else
 626                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 627
 628         if (dwc->u2exit_lfps_quirk)
 629                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 630
 631         /*
 632          * WORKAROUND: DWC3 revisions <1.90a have a bug
 633          * where the device can fail to connect at SuperSpeed
 634          * and falls back to high-speed mode which causes
 635          * the device to enter a Connect/Disconnect loop
 636          */
 637         if (dwc->revision < DWC3_REVISION_190A)
 638                 reg |= DWC3_GCTL_U2RSTECN;
 639
 640         dwc3_core_num_eps(dwc);
 641
 642         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 643
 644         ret = dwc3_alloc_scratch_buffers(dwc);
 645         if (ret)
 646                 goto err1;
 647
 648         ret = dwc3_setup_scratch_buffers(dwc);
 649         if (ret)
 650                 goto err2;
 651
 652         return 0;
 653
 654 err2:
 655         dwc3_free_scratch_buffers(dwc);
 656
 657 err1:
 658         usb_phy_shutdown(dwc->usb2_phy);
 659         usb_phy_shutdown(dwc->usb3_phy);
 660         phy_exit(dwc->usb2_generic_phy);
 661         phy_exit(dwc->usb3_generic_phy);
 662
 663 err0:
 664         return ret;
 665 }
 666
 667 static void dwc3_core_exit(struct dwc3 *dwc)
 668 {
 669         dwc3_free_scratch_buffers(dwc);
 670         usb_phy_shutdown(dwc->usb2_phy);
 671         usb_phy_shutdown(dwc->usb3_phy);
 672         phy_exit(dwc->usb2_generic_phy);
 673         phy_exit(dwc->usb3_generic_phy);
 674 }
 675
 676 static int dwc3_core_get_phy(struct dwc3 *dwc)
 677 {
 678         struct device           *dev = dwc->dev;
 679         struct device_node      *node = dev->of_node;
 680         int ret;
 681
 682         if (node) {
 683                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 684                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 685         } else {
 686                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 687                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 688         }
 689
 690         if (IS_ERR(dwc->usb2_phy)) {
 691                 ret = PTR_ERR(dwc->usb2_phy);
 692                 if (ret == -ENXIO || ret == -ENODEV) {
 693                         dwc->usb2_phy = NULL;
 694                 } else if (ret == -EPROBE_DEFER) {
 695                         return ret;
 696                 } else {
 697                         dev_err(dev, "no usb2 phy configured\n");
 698                         return ret;
 699                 }
 700         }
 701
 702         if (IS_ERR(dwc->usb3_phy)) {
 703                 ret = PTR_ERR(dwc->usb3_phy);
 704                 if (ret == -ENXIO || ret == -ENODEV) {
 705                         dwc->usb3_phy = NULL;
 706                 } else if (ret == -EPROBE_DEFER) {
 707                         return ret;
 708                 } else {
 709                         dev_err(dev, "no usb3 phy configured\n");
 710                         return ret;
 711                 }
 712         }
 713
 714         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 715         if (IS_ERR(dwc->usb2_generic_phy)) {
 716                 ret = PTR_ERR(dwc->usb2_generic_phy);
 717                 if (ret == -ENOSYS || ret == -ENODEV) {
 718                         dwc->usb2_generic_phy = NULL;
 719                 } else if (ret == -EPROBE_DEFER) {
 720                         return ret;
 721                 } else {
 722                         dev_err(dev, "no usb2 phy configured\n");
 723                         return ret;
 724                 }
 725         }
 726
 727         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
 728         if (IS_ERR(dwc->usb3_generic_phy)) {
 729                 ret = PTR_ERR(dwc->usb3_generic_phy);
 730                 if (ret == -ENOSYS || ret == -ENODEV) {
 731                         dwc->usb3_generic_phy = NULL;
 732                 } else if (ret == -EPROBE_DEFER) {
 733                         return ret;
 734                 } else {
 735                         dev_err(dev, "no usb3 phy configured\n");
 736                         return ret;
 737                 }
 738         }
 739
 740         return 0;
 741 }
 742
 743 static int dwc3_core_init_mode(struct dwc3 *dwc)
 744 {
 745         struct device *dev = dwc->dev;
 746         int ret;
 747
 748         switch (dwc->dr_mode) {
 749         case USB_DR_MODE_PERIPHERAL:
 750                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 751                 ret = dwc3_gadget_init(dwc);
 752                 if (ret) {
 753                         dev_err(dev, "failed to initialize gadget\n");
 754                         return ret;
 755                 }
 756                 break;
 757         case USB_DR_MODE_HOST:
 758                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 759                 ret = dwc3_host_init(dwc);
 760                 if (ret) {
 761                         dev_err(dev, "failed to initialize host\n");
 762                         return ret;
 763                 }
 764                 break;
 765         case USB_DR_MODE_OTG:
 766                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 767                 ret = dwc3_host_init(dwc);
 768                 if (ret) {
 769                         dev_err(dev, "failed to initialize host\n");
 770                         return ret;
 771                 }
 772
 773                 ret = dwc3_gadget_init(dwc);
 774                 if (ret) {
 775                         dev_err(dev, "failed to initialize gadget\n");
 776                         return ret;
 777                 }
 778                 break;
 779         default:
 780                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 781                 return -EINVAL;
 782         }
 783
 784         return 0;
 785 }
 786
 787 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 788 {
 789         switch (dwc->dr_mode) {
 790         case USB_DR_MODE_PERIPHERAL:
 791                 dwc3_gadget_exit(dwc);
 792                 break;
 793         case USB_DR_MODE_HOST:
 794                 dwc3_host_exit(dwc);
 795                 break;
 796         case USB_DR_MODE_OTG:
 797                 dwc3_host_exit(dwc);
 798                 dwc3_gadget_exit(dwc);
 799                 break;
 800         default:
 801                 /* do nothing */
 802                 break;
 803         }
 804 }
 805
 806 #define DWC3_ALIGN_MASK         (16 - 1)
 807
 808 static int dwc3_probe(struct platform_device *pdev)
 809 {
 810         struct device           *dev = &pdev->dev;
 811         struct dwc3_platform_data *pdata = dev_get_platdata(dev);
 812         struct resource         *res;
 813         struct dwc3             *dwc;
 814         u8                      lpm_nyet_threshold;
 815         u8                      tx_de_emphasis;
 816         u8                      hird_threshold;
 817         u32                     fladj = 0;
 818
 819         int                     ret;
 820
 821         void __iomem            *regs;
 822         void                    *mem;
 823
 824         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 825         if (!mem)
 826                 return -ENOMEM;
 827
 828         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 829         dwc->mem = mem;
 830         dwc->dev = dev;
 831
 832         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 833         if (!res) {
 834                 dev_err(dev, "missing IRQ\n");
 835                 return -ENODEV;
 836         }
 837         dwc->xhci_resources[1].start = res->start;
 838         dwc->xhci_resources[1].end = res->end;
 839         dwc->xhci_resources[1].flags = res->flags;
 840         dwc->xhci_resources[1].name = res->name;
 841
 842         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 843         if (!res) {
 844                 dev_err(dev, "missing memory resource\n");
 845                 return -ENODEV;
 846         }
 847
 848         dwc->xhci_resources[0].start = res->start;
 849         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 850                                         DWC3_XHCI_REGS_END;
 851         dwc->xhci_resources[0].flags = res->flags;
 852         dwc->xhci_resources[0].name = res->name;
 853
 854         res->start += DWC3_GLOBALS_REGS_START;
 855
 856         /*
 857          * Request memory region but exclude xHCI regs,
 858          * since it will be requested by the xhci-plat driver.
 859          */
 860         regs = devm_ioremap_resource(dev, res);
 861         if (IS_ERR(regs)) {
 862                 ret = PTR_ERR(regs);
 863                 goto err0;
 864         }
 865
 866         dwc->regs       = regs;
 867         dwc->regs_size  = resource_size(res);
 868
 869         /* default to highest possible threshold */
 870         lpm_nyet_threshold = 0xff;
 871
 872         /* default to -3.5dB de-emphasis */
 873         tx_de_emphasis = 1;
 874
 875         /*
 876          * default to assert utmi_sleep_n and use maximum allowed HIRD
 877          * threshold value of 0b1100
 878          */
 879         hird_threshold = 12;
 880
 881         dwc->maximum_speed = usb_get_maximum_speed(dev);
 882         dwc->dr_mode = usb_get_dr_mode(dev);
 883
 884         dwc->has_lpm_erratum = device_property_read_bool(dev,
 885                                 "snps,has-lpm-erratum");
 886         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
 887                                 &lpm_nyet_threshold);
 888         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
 889                                 "snps,is-utmi-l1-suspend");
 890         device_property_read_u8(dev, "snps,hird-threshold",
 891                                 &hird_threshold);
 892         dwc->usb3_lpm_capable = device_property_read_bool(dev,
 893                                 "snps,usb3_lpm_capable");
 894
 895         dwc->needs_fifo_resize = device_property_read_bool(dev,
 896                                 "tx-fifo-resize");
 897
 898         dwc->disable_scramble_quirk = device_property_read_bool(dev,
 899                                 "snps,disable_scramble_quirk");
 900         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
 901                                 "snps,u2exit_lfps_quirk");
 902         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
 903                                 "snps,u2ss_inp3_quirk");
 904         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
 905                                 "snps,req_p1p2p3_quirk");
 906         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
 907                                 "snps,del_p1p2p3_quirk");
 908         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
 909                                 "snps,del_phy_power_chg_quirk");
 910         dwc->lfps_filter_quirk = device_property_read_bool(dev,
 911                                 "snps,lfps_filter_quirk");
 912         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
 913                                 "snps,rx_detect_poll_quirk");
 914         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
 915                                 "snps,dis_u3_susphy_quirk");
 916         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
 917                                 "snps,dis_u2_susphy_quirk");
 918         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
 919                                 "snps,dis_enblslpm_quirk");
 920
 921         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
 922                                 "snps,tx_de_emphasis_quirk");
 923         device_property_read_u8(dev, "snps,tx_de_emphasis",
 924                                 &tx_de_emphasis);
 925         device_property_read_string(dev, "snps,hsphy_interface",
 926                                     &dwc->hsphy_interface);
 927         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
 928                                  &fladj);
 929
 930         if (pdata) {
 931                 dwc->maximum_speed = pdata->maximum_speed;
 932                 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
 933                 if (pdata->lpm_nyet_threshold)
 934                         lpm_nyet_threshold = pdata->lpm_nyet_threshold;
 935                 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
 936                 if (pdata->hird_threshold)
 937                         hird_threshold = pdata->hird_threshold;
 938
 939                 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
 940                 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
 941                 dwc->dr_mode = pdata->dr_mode;
 942
 943                 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
 944                 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
 945                 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
 946                 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
 947                 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
 948                 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
 949                 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
 950                 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
 951                 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
 952                 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
 953                 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
 954
 955                 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
 956                 if (pdata->tx_de_emphasis)
 957                         tx_de_emphasis = pdata->tx_de_emphasis;
 958
 959                 dwc->hsphy_interface = pdata->hsphy_interface;
 960                 fladj = pdata->fladj_value;
 961         }
 962
 963         /* default to superspeed if no maximum_speed passed */
 964         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 965                 dwc->maximum_speed = USB_SPEED_SUPER;
 966
 967         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 968         dwc->tx_de_emphasis = tx_de_emphasis;
 969
 970         dwc->hird_threshold = hird_threshold
 971                 | (dwc->is_utmi_l1_suspend << 4);
 972
 973         platform_set_drvdata(pdev, dwc);
 974         dwc3_cache_hwparams(dwc);
 975
 976         ret = dwc3_phy_setup(dwc);
 977         if (ret)
 978                 goto err0;
 979
 980         ret = dwc3_core_get_phy(dwc);
 981         if (ret)
 982                 goto err0;
 983
 984         spin_lock_init(&dwc->lock);
 985
 986         if (!dev->dma_mask) {
 987                 dev->dma_mask = dev->parent->dma_mask;
 988                 dev->dma_parms = dev->parent->dma_parms;
 989                 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
 990         }
 991
 992         pm_runtime_enable(dev);
 993         pm_runtime_get_sync(dev);
 994         pm_runtime_forbid(dev);
 995
 996         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 997         if (ret) {
 998                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 999                 ret = -ENOMEM;
1000                 goto err1;
1001         }
1002
1003         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
1004                 dwc->dr_mode = USB_DR_MODE_HOST;
1005         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
1006                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1007
1008         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1009                 dwc->dr_mode = USB_DR_MODE_OTG;
1010
1011         ret = dwc3_core_init(dwc);
1012         if (ret) {
1013                 dev_err(dev, "failed to initialize core\n");
1014                 goto err1;
1015         }
1016
1017         /* Adjust Frame Length */
1018         dwc3_frame_length_adjustment(dwc, fladj);
1019
1020         usb_phy_set_suspend(dwc->usb2_phy, 0);
1021         usb_phy_set_suspend(dwc->usb3_phy, 0);
1022         ret = phy_power_on(dwc->usb2_generic_phy);
1023         if (ret < 0)
1024                 goto err2;
1025
1026         ret = phy_power_on(dwc->usb3_generic_phy);
1027         if (ret < 0)
1028                 goto err3;
1029
1030         ret = dwc3_event_buffers_setup(dwc);
1031         if (ret) {
1032                 dev_err(dwc->dev, "failed to setup event buffers\n");
1033                 goto err4;
1034         }
1035
1036         ret = dwc3_core_init_mode(dwc);
1037         if (ret)
1038                 goto err5;
1039
1040         ret = dwc3_debugfs_init(dwc);
1041         if (ret) {
1042                 dev_err(dev, "failed to initialize debugfs\n");
1043                 goto err6;
1044         }
1045
1046         pm_runtime_allow(dev);
1047
1048         return 0;
1049
1050 err6:
1051         dwc3_core_exit_mode(dwc);
1052
1053 err5:
1054         dwc3_event_buffers_cleanup(dwc);
1055
1056 err4:
1057         phy_power_off(dwc->usb3_generic_phy);
1058
1059 err3:
1060         phy_power_off(dwc->usb2_generic_phy);
1061
1062 err2:
1063         usb_phy_set_suspend(dwc->usb2_phy, 1);
1064         usb_phy_set_suspend(dwc->usb3_phy, 1);
1065         dwc3_core_exit(dwc);
1066
1067 err1:
1068         dwc3_free_event_buffers(dwc);
1069         dwc3_ulpi_exit(dwc);
1070
1071 err0:
1072         /*
1073          * restore res->start back to its original value so that, in case the
1074          * probe is deferred, we don't end up getting error in request the
1075          * memory region the next time probe is called.
1076          */
1077         res->start -= DWC3_GLOBALS_REGS_START;
1078
1079         return ret;
1080 }
1081
1082 static int dwc3_remove(struct platform_device *pdev)
1083 {
1084         struct dwc3     *dwc = platform_get_drvdata(pdev);
1085         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1086
1087         /*
1088          * restore res->start back to its original value so that, in case the
1089          * probe is deferred, we don't end up getting error in request the
1090          * memory region the next time probe is called.
1091          */
1092         res->start -= DWC3_GLOBALS_REGS_START;
1093
1094         dwc3_debugfs_exit(dwc);
1095         dwc3_core_exit_mode(dwc);
1096         dwc3_event_buffers_cleanup(dwc);
1097         dwc3_free_event_buffers(dwc);
1098
1099         usb_phy_set_suspend(dwc->usb2_phy, 1);
1100         usb_phy_set_suspend(dwc->usb3_phy, 1);
1101         phy_power_off(dwc->usb2_generic_phy);
1102         phy_power_off(dwc->usb3_generic_phy);
1103
1104         dwc3_core_exit(dwc);
1105         dwc3_ulpi_exit(dwc);
1106
1107         pm_runtime_put_sync(&pdev->dev);
1108         pm_runtime_disable(&pdev->dev);
1109
1110         return 0;
1111 }
1112
1113 #ifdef CONFIG_PM_SLEEP
1114 static int dwc3_suspend(struct device *dev)
1115 {
1116         struct dwc3     *dwc = dev_get_drvdata(dev);
1117         unsigned long   flags;
1118
1119         spin_lock_irqsave(&dwc->lock, flags);
1120
1121         switch (dwc->dr_mode) {
1122         case USB_DR_MODE_PERIPHERAL:
1123         case USB_DR_MODE_OTG:
1124                 dwc3_gadget_suspend(dwc);
1125                 /* FALLTHROUGH */
1126         case USB_DR_MODE_HOST:
1127         default:
1128                 dwc3_event_buffers_cleanup(dwc);
1129                 break;
1130         }
1131
1132         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1133         spin_unlock_irqrestore(&dwc->lock, flags);
1134
1135         usb_phy_shutdown(dwc->usb3_phy);
1136         usb_phy_shutdown(dwc->usb2_phy);
1137         phy_exit(dwc->usb2_generic_phy);
1138         phy_exit(dwc->usb3_generic_phy);
1139
1140         pinctrl_pm_select_sleep_state(dev);
1141
1142         return 0;
1143 }
1144
1145 static int dwc3_resume(struct device *dev)
1146 {
1147         struct dwc3     *dwc = dev_get_drvdata(dev);
1148         unsigned long   flags;
1149         int             ret;
1150
1151         pinctrl_pm_select_default_state(dev);
1152
1153         usb_phy_init(dwc->usb3_phy);
1154         usb_phy_init(dwc->usb2_phy);
1155         ret = phy_init(dwc->usb2_generic_phy);
1156         if (ret < 0)
1157                 return ret;
1158
1159         ret = phy_init(dwc->usb3_generic_phy);
1160         if (ret < 0)
1161                 goto err_usb2phy_init;
1162
1163         spin_lock_irqsave(&dwc->lock, flags);
1164
1165         dwc3_event_buffers_setup(dwc);
1166         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1167
1168         switch (dwc->dr_mode) {
1169         case USB_DR_MODE_PERIPHERAL:
1170         case USB_DR_MODE_OTG:
1171                 dwc3_gadget_resume(dwc);
1172                 /* FALLTHROUGH */
1173         case USB_DR_MODE_HOST:
1174         default:
1175                 /* do nothing */
1176                 break;
1177         }
1178
1179         spin_unlock_irqrestore(&dwc->lock, flags);
1180
1181         pm_runtime_disable(dev);
1182         pm_runtime_set_active(dev);
1183         pm_runtime_enable(dev);
1184
1185         return 0;
1186
1187 err_usb2phy_init:
1188         phy_exit(dwc->usb2_generic_phy);
1189
1190         return ret;
1191 }
1192
1193 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1194         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1195 };
1196
1197 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
1198 #else
1199 #define DWC3_PM_OPS     NULL
1200 #endif
1201
1202 #ifdef CONFIG_OF
1203 static const struct of_device_id of_dwc3_match[] = {
1204         {
1205                 .compatible = "snps,dwc3"
1206         },
1207         {
1208                 .compatible = "synopsys,dwc3"
1209         },
1210         { },
1211 };
1212 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1213 #endif
1214
1215 #ifdef CONFIG_ACPI
1216
1217 #define ACPI_ID_INTEL_BSW       "808622B7"
1218
1219 static const struct acpi_device_id dwc3_acpi_match[] = {
1220         { ACPI_ID_INTEL_BSW, 0 },
1221         { },
1222 };
1223 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1224 #endif
1225
1226 static struct platform_driver dwc3_driver = {
1227         .probe          = dwc3_probe,
1228         .remove         = dwc3_remove,
1229         .driver         = {
1230                 .name   = "dwc3",
1231                 .of_match_table = of_match_ptr(of_dwc3_match),
1232                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1233                 .pm     = DWC3_PM_OPS,
1234         },
1235 };
1236
1237 module_platform_driver(dwc3_driver);
1238
1239 MODULE_ALIAS("platform:dwc3");
1240 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1241 MODULE_LICENSE("GPL v2");
1242 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");