2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/kdb.h>
39 #include <linux/uaccess.h>
40 #include <linux/pm_runtime.h>
51 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
53 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
56 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
59 * Here we define the default xmit fifo size used for each type of UART.
61 static const struct serial8250_config uart_config[] = {
86 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
87 .rxtrig_bytes = {1, 4, 8, 14},
88 .flags = UART_CAP_FIFO,
99 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
105 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
107 .rxtrig_bytes = {8, 16, 24, 28},
108 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
114 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
116 .rxtrig_bytes = {1, 16, 32, 56},
117 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
125 .name = "16C950/954",
128 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
129 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
130 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
136 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
138 .rxtrig_bytes = {8, 16, 56, 60},
139 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
145 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
146 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
152 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
153 .flags = UART_CAP_FIFO,
159 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
160 .flags = UART_CAP_FIFO | UART_NATSEMI,
166 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
167 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
173 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
174 .flags = UART_CAP_FIFO,
180 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
181 .flags = UART_CAP_FIFO | UART_CAP_AFE,
187 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
188 .flags = UART_CAP_FIFO | UART_CAP_AFE,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
196 .rxtrig_bytes = {1, 4, 8, 14},
197 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
203 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
204 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
211 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
213 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
220 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
221 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
222 .flags = UART_CAP_FIFO,
224 [PORT_BRCM_TRUMANAGE] = {
228 .flags = UART_CAP_HFIFO,
233 [PORT_ALTR_16550_F32] = {
234 .name = "Altera 16550 FIFO32",
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
238 .flags = UART_CAP_FIFO | UART_CAP_AFE,
240 [PORT_ALTR_16550_F64] = {
241 .name = "Altera 16550 FIFO64",
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_CAP_AFE,
247 [PORT_ALTR_16550_F128] = {
248 .name = "Altera 16550 FIFO128",
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_AFE,
254 /* tx_loadsz is set to 63-bytes instead of 64-bytes to implement
255 workaround of errata A-008006 which states that tx_loadsz should be
256 configured less than Maximum supported fifo bytes */
257 [PORT_16550A_FSL64] = {
258 .name = "16550A_FSL64",
261 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
263 .flags = UART_CAP_FIFO,
266 .name = "Palmchip BK-3103",
269 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
270 .rxtrig_bytes = {1, 4, 8, 14},
271 .flags = UART_CAP_FIFO,
275 /* Uart divisor latch read */
276 static int default_serial_dl_read(struct uart_8250_port *up)
278 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
281 /* Uart divisor latch write */
282 static void default_serial_dl_write(struct uart_8250_port *up, int value)
284 serial_out(up, UART_DLL, value & 0xff);
285 serial_out(up, UART_DLM, value >> 8 & 0xff);
288 #ifdef CONFIG_SERIAL_8250_RT288X
290 /* Au1x00/RT288x UART hardware has a weird register layout */
291 static const s8 au_io_in_map[8] = {
299 -1, /* UART_SCR (unmapped) */
302 static const s8 au_io_out_map[8] = {
308 -1, /* UART_LSR (unmapped) */
309 -1, /* UART_MSR (unmapped) */
310 -1, /* UART_SCR (unmapped) */
313 static unsigned int au_serial_in(struct uart_port *p, int offset)
315 if (offset >= ARRAY_SIZE(au_io_in_map))
317 offset = au_io_in_map[offset];
320 return __raw_readl(p->membase + (offset << p->regshift));
323 static void au_serial_out(struct uart_port *p, int offset, int value)
325 if (offset >= ARRAY_SIZE(au_io_out_map))
327 offset = au_io_out_map[offset];
330 __raw_writel(value, p->membase + (offset << p->regshift));
333 /* Au1x00 haven't got a standard divisor latch */
334 static int au_serial_dl_read(struct uart_8250_port *up)
336 return __raw_readl(up->port.membase + 0x28);
339 static void au_serial_dl_write(struct uart_8250_port *up, int value)
341 __raw_writel(value, up->port.membase + 0x28);
346 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
348 offset = offset << p->regshift;
349 outb(p->hub6 - 1 + offset, p->iobase);
350 return inb(p->iobase + 1);
353 static void hub6_serial_out(struct uart_port *p, int offset, int value)
355 offset = offset << p->regshift;
356 outb(p->hub6 - 1 + offset, p->iobase);
357 outb(value, p->iobase + 1);
360 static unsigned int mem_serial_in(struct uart_port *p, int offset)
362 offset = offset << p->regshift;
363 return readb(p->membase + offset);
366 static void mem_serial_out(struct uart_port *p, int offset, int value)
368 offset = offset << p->regshift;
369 writeb(value, p->membase + offset);
372 static void mem32_serial_out(struct uart_port *p, int offset, int value)
374 offset = offset << p->regshift;
375 writel(value, p->membase + offset);
378 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
380 offset = offset << p->regshift;
381 return readl(p->membase + offset);
384 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
386 offset = offset << p->regshift;
387 iowrite32be(value, p->membase + offset);
390 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
392 offset = offset << p->regshift;
393 return ioread32be(p->membase + offset);
396 static unsigned int io_serial_in(struct uart_port *p, int offset)
398 offset = offset << p->regshift;
399 return inb(p->iobase + offset);
402 static void io_serial_out(struct uart_port *p, int offset, int value)
404 offset = offset << p->regshift;
405 outb(value, p->iobase + offset);
408 static int serial8250_default_handle_irq(struct uart_port *port);
409 static int exar_handle_irq(struct uart_port *port);
411 static void set_io_from_upio(struct uart_port *p)
413 struct uart_8250_port *up = up_to_u8250p(p);
415 up->dl_read = default_serial_dl_read;
416 up->dl_write = default_serial_dl_write;
420 p->serial_in = hub6_serial_in;
421 p->serial_out = hub6_serial_out;
425 p->serial_in = mem_serial_in;
426 p->serial_out = mem_serial_out;
430 p->serial_in = mem32_serial_in;
431 p->serial_out = mem32_serial_out;
435 p->serial_in = mem32be_serial_in;
436 p->serial_out = mem32be_serial_out;
439 #ifdef CONFIG_SERIAL_8250_RT288X
441 p->serial_in = au_serial_in;
442 p->serial_out = au_serial_out;
443 up->dl_read = au_serial_dl_read;
444 up->dl_write = au_serial_dl_write;
449 p->serial_in = io_serial_in;
450 p->serial_out = io_serial_out;
453 /* Remember loaded iotype */
454 up->cur_iotype = p->iotype;
455 p->handle_irq = serial8250_default_handle_irq;
459 serial_port_out_sync(struct uart_port *p, int offset, int value)
466 p->serial_out(p, offset, value);
467 p->serial_in(p, UART_LCR); /* safe, no side-effects */
470 p->serial_out(p, offset, value);
477 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
479 serial_out(up, UART_SCR, offset);
480 serial_out(up, UART_ICR, value);
483 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
487 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
488 serial_out(up, UART_SCR, offset);
489 value = serial_in(up, UART_ICR);
490 serial_icr_write(up, UART_ACR, up->acr);
498 static void serial8250_clear_fifos(struct uart_8250_port *p)
500 if (p->capabilities & UART_CAP_FIFO) {
501 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
502 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
503 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
504 serial_out(p, UART_FCR, 0);
508 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
510 serial8250_clear_fifos(p);
511 serial_out(p, UART_FCR, p->fcr);
513 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
515 void serial8250_rpm_get(struct uart_8250_port *p)
517 if (!(p->capabilities & UART_CAP_RPM))
519 pm_runtime_get_sync(p->port.dev);
521 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
523 void serial8250_rpm_put(struct uart_8250_port *p)
525 if (!(p->capabilities & UART_CAP_RPM))
527 pm_runtime_mark_last_busy(p->port.dev);
528 pm_runtime_put_autosuspend(p->port.dev);
530 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
533 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
534 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
535 * empty and the HW can idle again.
537 static void serial8250_rpm_get_tx(struct uart_8250_port *p)
539 unsigned char rpm_active;
541 if (!(p->capabilities & UART_CAP_RPM))
544 rpm_active = xchg(&p->rpm_tx_active, 1);
547 pm_runtime_get_sync(p->port.dev);
550 static void serial8250_rpm_put_tx(struct uart_8250_port *p)
552 unsigned char rpm_active;
554 if (!(p->capabilities & UART_CAP_RPM))
557 rpm_active = xchg(&p->rpm_tx_active, 0);
560 pm_runtime_mark_last_busy(p->port.dev);
561 pm_runtime_put_autosuspend(p->port.dev);
565 * IER sleep support. UARTs which have EFRs need the "extended
566 * capability" bit enabled. Note that on XR16C850s, we need to
567 * reset LCR to write to IER.
569 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
571 unsigned char lcr = 0, efr = 0;
573 * Exar UARTs have a SLEEP register that enables or disables
574 * each UART to enter sleep mode separately. On the XR17V35x the
575 * register is accessible to each UART at the UART_EXAR_SLEEP
576 * offset but the UART channel may only write to the corresponding
579 serial8250_rpm_get(p);
580 if ((p->port.type == PORT_XR17V35X) ||
581 (p->port.type == PORT_XR17D15X)) {
582 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
586 if (p->capabilities & UART_CAP_SLEEP) {
587 if (p->capabilities & UART_CAP_EFR) {
588 lcr = serial_in(p, UART_LCR);
589 efr = serial_in(p, UART_EFR);
590 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
591 serial_out(p, UART_EFR, UART_EFR_ECB);
592 serial_out(p, UART_LCR, 0);
594 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
595 if (p->capabilities & UART_CAP_EFR) {
596 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
597 serial_out(p, UART_EFR, efr);
598 serial_out(p, UART_LCR, lcr);
602 serial8250_rpm_put(p);
605 #ifdef CONFIG_SERIAL_8250_RSA
607 * Attempts to turn on the RSA FIFO. Returns zero on failure.
608 * We set the port uart clock rate if we succeed.
610 static int __enable_rsa(struct uart_8250_port *up)
615 mode = serial_in(up, UART_RSA_MSR);
616 result = mode & UART_RSA_MSR_FIFO;
619 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
620 mode = serial_in(up, UART_RSA_MSR);
621 result = mode & UART_RSA_MSR_FIFO;
625 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
630 static void enable_rsa(struct uart_8250_port *up)
632 if (up->port.type == PORT_RSA) {
633 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
634 spin_lock_irq(&up->port.lock);
636 spin_unlock_irq(&up->port.lock);
638 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
639 serial_out(up, UART_RSA_FRR, 0);
644 * Attempts to turn off the RSA FIFO. Returns zero on failure.
645 * It is unknown why interrupts were disabled in here. However,
646 * the caller is expected to preserve this behaviour by grabbing
647 * the spinlock before calling this function.
649 static void disable_rsa(struct uart_8250_port *up)
654 if (up->port.type == PORT_RSA &&
655 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
656 spin_lock_irq(&up->port.lock);
658 mode = serial_in(up, UART_RSA_MSR);
659 result = !(mode & UART_RSA_MSR_FIFO);
662 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
663 mode = serial_in(up, UART_RSA_MSR);
664 result = !(mode & UART_RSA_MSR_FIFO);
668 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
669 spin_unlock_irq(&up->port.lock);
672 #endif /* CONFIG_SERIAL_8250_RSA */
675 * This is a quickie test to see how big the FIFO is.
676 * It doesn't work at all the time, more's the pity.
678 static int size_fifo(struct uart_8250_port *up)
680 unsigned char old_fcr, old_mcr, old_lcr;
681 unsigned short old_dl;
684 old_lcr = serial_in(up, UART_LCR);
685 serial_out(up, UART_LCR, 0);
686 old_fcr = serial_in(up, UART_FCR);
687 old_mcr = serial_in(up, UART_MCR);
688 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
689 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
690 serial_out(up, UART_MCR, UART_MCR_LOOP);
691 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
692 old_dl = serial_dl_read(up);
693 serial_dl_write(up, 0x0001);
694 serial_out(up, UART_LCR, 0x03);
695 for (count = 0; count < 256; count++)
696 serial_out(up, UART_TX, count);
697 mdelay(20);/* FIXME - schedule_timeout */
698 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
699 (count < 256); count++)
700 serial_in(up, UART_RX);
701 serial_out(up, UART_FCR, old_fcr);
702 serial_out(up, UART_MCR, old_mcr);
703 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
704 serial_dl_write(up, old_dl);
705 serial_out(up, UART_LCR, old_lcr);
711 * Read UART ID using the divisor method - set DLL and DLM to zero
712 * and the revision will be in DLL and device type in DLM. We
713 * preserve the device state across this.
715 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
717 unsigned char old_dll, old_dlm, old_lcr;
720 old_lcr = serial_in(p, UART_LCR);
721 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
723 old_dll = serial_in(p, UART_DLL);
724 old_dlm = serial_in(p, UART_DLM);
726 serial_out(p, UART_DLL, 0);
727 serial_out(p, UART_DLM, 0);
729 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
731 serial_out(p, UART_DLL, old_dll);
732 serial_out(p, UART_DLM, old_dlm);
733 serial_out(p, UART_LCR, old_lcr);
739 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
740 * When this function is called we know it is at least a StarTech
741 * 16650 V2, but it might be one of several StarTech UARTs, or one of
742 * its clones. (We treat the broken original StarTech 16650 V1 as a
743 * 16550, and why not? Startech doesn't seem to even acknowledge its
746 * What evil have men's minds wrought...
748 static void autoconfig_has_efr(struct uart_8250_port *up)
750 unsigned int id1, id2, id3, rev;
753 * Everything with an EFR has SLEEP
755 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
758 * First we check to see if it's an Oxford Semiconductor UART.
760 * If we have to do this here because some non-National
761 * Semiconductor clone chips lock up if you try writing to the
762 * LSR register (which serial_icr_read does)
766 * Check for Oxford Semiconductor 16C950.
768 * EFR [4] must be set else this test fails.
770 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
771 * claims that it's needed for 952 dual UART's (which are not
772 * recommended for new designs).
775 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
776 serial_out(up, UART_EFR, UART_EFR_ECB);
777 serial_out(up, UART_LCR, 0x00);
778 id1 = serial_icr_read(up, UART_ID1);
779 id2 = serial_icr_read(up, UART_ID2);
780 id3 = serial_icr_read(up, UART_ID3);
781 rev = serial_icr_read(up, UART_REV);
783 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
785 if (id1 == 0x16 && id2 == 0xC9 &&
786 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
787 up->port.type = PORT_16C950;
790 * Enable work around for the Oxford Semiconductor 952 rev B
791 * chip which causes it to seriously miscalculate baud rates
794 if (id3 == 0x52 && rev == 0x01)
795 up->bugs |= UART_BUG_QUOT;
800 * We check for a XR16C850 by setting DLL and DLM to 0, and then
801 * reading back DLL and DLM. The chip type depends on the DLM
803 * 0x10 - XR16C850 and the DLL contains the chip revision.
807 id1 = autoconfig_read_divisor_id(up);
808 DEBUG_AUTOCONF("850id=%04x ", id1);
811 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
812 up->port.type = PORT_16850;
817 * It wasn't an XR16C850.
819 * We distinguish between the '654 and the '650 by counting
820 * how many bytes are in the FIFO. I'm using this for now,
821 * since that's the technique that was sent to me in the
822 * serial driver update, but I'm not convinced this works.
823 * I've had problems doing this in the past. -TYT
825 if (size_fifo(up) == 64)
826 up->port.type = PORT_16654;
828 up->port.type = PORT_16650V2;
832 * We detected a chip without a FIFO. Only two fall into
833 * this category - the original 8250 and the 16450. The
834 * 16450 has a scratch register (accessible with LCR=0)
836 static void autoconfig_8250(struct uart_8250_port *up)
838 unsigned char scratch, status1, status2;
840 up->port.type = PORT_8250;
842 scratch = serial_in(up, UART_SCR);
843 serial_out(up, UART_SCR, 0xa5);
844 status1 = serial_in(up, UART_SCR);
845 serial_out(up, UART_SCR, 0x5a);
846 status2 = serial_in(up, UART_SCR);
847 serial_out(up, UART_SCR, scratch);
849 if (status1 == 0xa5 && status2 == 0x5a)
850 up->port.type = PORT_16450;
853 static int broken_efr(struct uart_8250_port *up)
856 * Exar ST16C2550 "A2" devices incorrectly detect as
857 * having an EFR, and report an ID of 0x0201. See
858 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
860 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
867 * We know that the chip has FIFOs. Does it have an EFR? The
868 * EFR is located in the same register position as the IIR and
869 * we know the top two bits of the IIR are currently set. The
870 * EFR should contain zero. Try to read the EFR.
872 static void autoconfig_16550a(struct uart_8250_port *up)
874 unsigned char status1, status2;
875 unsigned int iersave;
877 up->port.type = PORT_16550A;
878 up->capabilities |= UART_CAP_FIFO;
881 * XR17V35x UARTs have an extra divisor register, DLD
882 * that gets enabled with when DLAB is set which will
883 * cause the device to incorrectly match and assign
884 * port type to PORT_16650. The EFR for this UART is
885 * found at offset 0x09. Instead check the Deice ID (DVID)
886 * register for a 2, 4 or 8 port UART.
888 if (up->port.flags & UPF_EXAR_EFR) {
889 status1 = serial_in(up, UART_EXAR_DVID);
890 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
891 DEBUG_AUTOCONF("Exar XR17V35x ");
892 up->port.type = PORT_XR17V35X;
893 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
902 * Check for presence of the EFR when DLAB is set.
903 * Only ST16C650V1 UARTs pass this test.
905 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
906 if (serial_in(up, UART_EFR) == 0) {
907 serial_out(up, UART_EFR, 0xA8);
908 if (serial_in(up, UART_EFR) != 0) {
909 DEBUG_AUTOCONF("EFRv1 ");
910 up->port.type = PORT_16650;
911 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
913 serial_out(up, UART_LCR, 0);
914 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
916 status1 = serial_in(up, UART_IIR) >> 5;
917 serial_out(up, UART_FCR, 0);
918 serial_out(up, UART_LCR, 0);
921 up->port.type = PORT_16550A_FSL64;
923 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
925 serial_out(up, UART_EFR, 0);
930 * Maybe it requires 0xbf to be written to the LCR.
931 * (other ST16C650V2 UARTs, TI16C752A, etc)
933 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
934 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
935 DEBUG_AUTOCONF("EFRv2 ");
936 autoconfig_has_efr(up);
941 * Check for a National Semiconductor SuperIO chip.
942 * Attempt to switch to bank 2, read the value of the LOOP bit
943 * from EXCR1. Switch back to bank 0, change it in MCR. Then
944 * switch back to bank 2, read it from EXCR1 again and check
945 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
947 serial_out(up, UART_LCR, 0);
948 status1 = serial_in(up, UART_MCR);
949 serial_out(up, UART_LCR, 0xE0);
950 status2 = serial_in(up, 0x02); /* EXCR1 */
952 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
953 serial_out(up, UART_LCR, 0);
954 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
955 serial_out(up, UART_LCR, 0xE0);
956 status2 = serial_in(up, 0x02); /* EXCR1 */
957 serial_out(up, UART_LCR, 0);
958 serial_out(up, UART_MCR, status1);
960 if ((status2 ^ status1) & UART_MCR_LOOP) {
963 serial_out(up, UART_LCR, 0xE0);
965 quot = serial_dl_read(up);
968 if (ns16550a_goto_highspeed(up))
969 serial_dl_write(up, quot);
971 serial_out(up, UART_LCR, 0);
973 up->port.uartclk = 921600*16;
974 up->port.type = PORT_NS16550A;
975 up->capabilities |= UART_NATSEMI;
981 * No EFR. Try to detect a TI16750, which only sets bit 5 of
982 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
983 * Try setting it with and without DLAB set. Cheap clones
984 * set bit 5 without DLAB set.
986 serial_out(up, UART_LCR, 0);
987 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
988 status1 = serial_in(up, UART_IIR) >> 5;
989 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
990 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
991 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
992 status2 = serial_in(up, UART_IIR) >> 5;
993 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
994 serial_out(up, UART_LCR, 0);
996 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
998 if (status1 == 6 && status2 == 7) {
999 up->port.type = PORT_16750;
1000 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1005 * Try writing and reading the UART_IER_UUE bit (b6).
1006 * If it works, this is probably one of the Xscale platform's
1008 * We're going to explicitly set the UUE bit to 0 before
1009 * trying to write and read a 1 just to make sure it's not
1010 * already a 1 and maybe locked there before we even start start.
1012 iersave = serial_in(up, UART_IER);
1013 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1014 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1016 * OK it's in a known zero state, try writing and reading
1017 * without disturbing the current state of the other bits.
1019 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1020 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1023 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1025 DEBUG_AUTOCONF("Xscale ");
1026 up->port.type = PORT_XSCALE;
1027 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1032 * If we got here we couldn't force the IER_UUE bit to 0.
1033 * Log it and continue.
1035 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1037 serial_out(up, UART_IER, iersave);
1040 * Exar uarts have EFR in a weird location
1042 if (up->port.flags & UPF_EXAR_EFR) {
1043 DEBUG_AUTOCONF("Exar XR17D15x ");
1044 up->port.type = PORT_XR17D15X;
1045 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1052 * We distinguish between 16550A and U6 16550A by counting
1053 * how many bytes are in the FIFO.
1055 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1056 up->port.type = PORT_U6_16550A;
1057 up->capabilities |= UART_CAP_AFE;
1062 * This routine is called by rs_init() to initialize a specific serial
1063 * port. It determines what type of UART chip this serial port is
1064 * using: 8250, 16450, 16550, 16550A. The important question is
1065 * whether or not this UART is a 16550A or not, since this will
1066 * determine whether or not we can use its FIFO features or not.
1068 static void autoconfig(struct uart_8250_port *up)
1070 unsigned char status1, scratch, scratch2, scratch3;
1071 unsigned char save_lcr, save_mcr;
1072 struct uart_port *port = &up->port;
1073 unsigned long flags;
1074 unsigned int old_capabilities;
1076 if (!port->iobase && !port->mapbase && !port->membase)
1079 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1080 serial_index(port), port->iobase, port->membase);
1083 * We really do need global IRQs disabled here - we're going to
1084 * be frobbing the chips IRQ enable register to see if it exists.
1086 spin_lock_irqsave(&port->lock, flags);
1088 up->capabilities = 0;
1091 if (!(port->flags & UPF_BUGGY_UART)) {
1093 * Do a simple existence test first; if we fail this,
1094 * there's no point trying anything else.
1096 * 0x80 is used as a nonsense port to prevent against
1097 * false positives due to ISA bus float. The
1098 * assumption is that 0x80 is a non-existent port;
1099 * which should be safe since include/asm/io.h also
1100 * makes this assumption.
1102 * Note: this is safe as long as MCR bit 4 is clear
1103 * and the device is in "PC" mode.
1105 scratch = serial_in(up, UART_IER);
1106 serial_out(up, UART_IER, 0);
1111 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1112 * 16C754B) allow only to modify them if an EFR bit is set.
1114 scratch2 = serial_in(up, UART_IER) & 0x0f;
1115 serial_out(up, UART_IER, 0x0F);
1119 scratch3 = serial_in(up, UART_IER) & 0x0f;
1120 serial_out(up, UART_IER, scratch);
1121 if (scratch2 != 0 || scratch3 != 0x0F) {
1123 * We failed; there's nothing here
1125 spin_unlock_irqrestore(&port->lock, flags);
1126 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1127 scratch2, scratch3);
1132 save_mcr = serial_in(up, UART_MCR);
1133 save_lcr = serial_in(up, UART_LCR);
1136 * Check to see if a UART is really there. Certain broken
1137 * internal modems based on the Rockwell chipset fail this
1138 * test, because they apparently don't implement the loopback
1139 * test mode. So this test is skipped on the COM 1 through
1140 * COM 4 ports. This *should* be safe, since no board
1141 * manufacturer would be stupid enough to design a board
1142 * that conflicts with COM 1-4 --- we hope!
1144 if (!(port->flags & UPF_SKIP_TEST)) {
1145 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1146 status1 = serial_in(up, UART_MSR) & 0xF0;
1147 serial_out(up, UART_MCR, save_mcr);
1148 if (status1 != 0x90) {
1149 spin_unlock_irqrestore(&port->lock, flags);
1150 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1157 * We're pretty sure there's a port here. Lets find out what
1158 * type of port it is. The IIR top two bits allows us to find
1159 * out if it's 8250 or 16450, 16550, 16550A or later. This
1160 * determines what we test for next.
1162 * We also initialise the EFR (if any) to zero for later. The
1163 * EFR occupies the same register location as the FCR and IIR.
1165 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1166 serial_out(up, UART_EFR, 0);
1167 serial_out(up, UART_LCR, 0);
1169 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1170 scratch = serial_in(up, UART_IIR) >> 6;
1174 autoconfig_8250(up);
1177 port->type = PORT_UNKNOWN;
1180 port->type = PORT_16550;
1183 autoconfig_16550a(up);
1187 #ifdef CONFIG_SERIAL_8250_RSA
1189 * Only probe for RSA ports if we got the region.
1191 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1193 port->type = PORT_RSA;
1196 serial_out(up, UART_LCR, save_lcr);
1198 port->fifosize = uart_config[up->port.type].fifo_size;
1199 old_capabilities = up->capabilities;
1200 up->capabilities = uart_config[port->type].flags;
1201 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1203 if (port->type == PORT_UNKNOWN)
1209 #ifdef CONFIG_SERIAL_8250_RSA
1210 if (port->type == PORT_RSA)
1211 serial_out(up, UART_RSA_FRR, 0);
1213 serial_out(up, UART_MCR, save_mcr);
1214 serial8250_clear_fifos(up);
1215 serial_in(up, UART_RX);
1216 if (up->capabilities & UART_CAP_UUE)
1217 serial_out(up, UART_IER, UART_IER_UUE);
1219 serial_out(up, UART_IER, 0);
1222 spin_unlock_irqrestore(&port->lock, flags);
1223 if (up->capabilities != old_capabilities) {
1225 "ttyS%d: detected caps %08x should be %08x\n",
1226 serial_index(port), old_capabilities,
1230 DEBUG_AUTOCONF("iir=%d ", scratch);
1231 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1234 static void autoconfig_irq(struct uart_8250_port *up)
1236 struct uart_port *port = &up->port;
1237 unsigned char save_mcr, save_ier;
1238 unsigned char save_ICP = 0;
1239 unsigned int ICP = 0;
1243 if (port->flags & UPF_FOURPORT) {
1244 ICP = (port->iobase & 0xfe0) | 0x1f;
1245 save_ICP = inb_p(ICP);
1250 if (uart_console(port))
1253 /* forget possible initially masked and pending IRQ */
1254 probe_irq_off(probe_irq_on());
1255 save_mcr = serial_in(up, UART_MCR);
1256 save_ier = serial_in(up, UART_IER);
1257 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1259 irqs = probe_irq_on();
1260 serial_out(up, UART_MCR, 0);
1262 if (port->flags & UPF_FOURPORT) {
1263 serial_out(up, UART_MCR,
1264 UART_MCR_DTR | UART_MCR_RTS);
1266 serial_out(up, UART_MCR,
1267 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1269 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1270 serial_in(up, UART_LSR);
1271 serial_in(up, UART_RX);
1272 serial_in(up, UART_IIR);
1273 serial_in(up, UART_MSR);
1274 serial_out(up, UART_TX, 0xFF);
1276 irq = probe_irq_off(irqs);
1278 serial_out(up, UART_MCR, save_mcr);
1279 serial_out(up, UART_IER, save_ier);
1281 if (port->flags & UPF_FOURPORT)
1282 outb_p(save_ICP, ICP);
1284 if (uart_console(port))
1287 port->irq = (irq > 0) ? irq : 0;
1290 static inline void __stop_tx(struct uart_8250_port *p)
1292 if (p->ier & UART_IER_THRI) {
1293 p->ier &= ~UART_IER_THRI;
1294 serial_out(p, UART_IER, p->ier);
1295 serial8250_rpm_put_tx(p);
1299 static void serial8250_stop_tx(struct uart_port *port)
1301 struct uart_8250_port *up = up_to_u8250p(port);
1303 serial8250_rpm_get(up);
1307 * We really want to stop the transmitter from sending.
1309 if (port->type == PORT_16C950) {
1310 up->acr |= UART_ACR_TXDIS;
1311 serial_icr_write(up, UART_ACR, up->acr);
1313 serial8250_rpm_put(up);
1316 static void serial8250_start_tx(struct uart_port *port)
1318 struct uart_8250_port *up = up_to_u8250p(port);
1320 serial8250_rpm_get_tx(up);
1322 if (up->dma && !up->dma->tx_dma(up))
1325 if (!(up->ier & UART_IER_THRI)) {
1326 up->ier |= UART_IER_THRI;
1327 serial_port_out(port, UART_IER, up->ier);
1329 if (up->bugs & UART_BUG_TXEN) {
1331 lsr = serial_in(up, UART_LSR);
1332 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1333 if (lsr & UART_LSR_THRE)
1334 serial8250_tx_chars(up);
1339 * Re-enable the transmitter if we disabled it.
1341 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1342 up->acr &= ~UART_ACR_TXDIS;
1343 serial_icr_write(up, UART_ACR, up->acr);
1347 static void serial8250_throttle(struct uart_port *port)
1349 port->throttle(port);
1352 static void serial8250_unthrottle(struct uart_port *port)
1354 port->unthrottle(port);
1357 static void serial8250_stop_rx(struct uart_port *port)
1359 struct uart_8250_port *up = up_to_u8250p(port);
1361 serial8250_rpm_get(up);
1363 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1364 up->port.read_status_mask &= ~UART_LSR_DR;
1365 serial_port_out(port, UART_IER, up->ier);
1367 serial8250_rpm_put(up);
1370 static void serial8250_disable_ms(struct uart_port *port)
1372 struct uart_8250_port *up =
1373 container_of(port, struct uart_8250_port, port);
1375 /* no MSR capabilities */
1376 if (up->bugs & UART_BUG_NOMSR)
1379 up->ier &= ~UART_IER_MSI;
1380 serial_port_out(port, UART_IER, up->ier);
1383 static void serial8250_enable_ms(struct uart_port *port)
1385 struct uart_8250_port *up = up_to_u8250p(port);
1387 /* no MSR capabilities */
1388 if (up->bugs & UART_BUG_NOMSR)
1391 up->ier |= UART_IER_MSI;
1393 serial8250_rpm_get(up);
1394 serial_port_out(port, UART_IER, up->ier);
1395 serial8250_rpm_put(up);
1399 * serial8250_rx_chars: processes according to the passed in LSR
1400 * value, and returns the remaining LSR bits not handled
1401 * by this Rx routine.
1404 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1406 struct uart_port *port = &up->port;
1408 int max_count = 256;
1412 if (likely(lsr & UART_LSR_DR))
1413 ch = serial_in(up, UART_RX);
1416 * Intel 82571 has a Serial Over Lan device that will
1417 * set UART_LSR_BI without setting UART_LSR_DR when
1418 * it receives a break. To avoid reading from the
1419 * receive buffer without UART_LSR_DR bit set, we
1420 * just force the read character to be 0
1427 lsr |= up->lsr_saved_flags;
1428 up->lsr_saved_flags = 0;
1430 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1431 if (lsr & UART_LSR_BI) {
1432 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1435 * We do the SysRQ and SAK checking
1436 * here because otherwise the break
1437 * may get masked by ignore_status_mask
1438 * or read_status_mask.
1440 if (uart_handle_break(port))
1442 } else if (lsr & UART_LSR_PE)
1443 port->icount.parity++;
1444 else if (lsr & UART_LSR_FE)
1445 port->icount.frame++;
1446 if (lsr & UART_LSR_OE)
1447 port->icount.overrun++;
1450 * Mask off conditions which should be ignored.
1452 lsr &= port->read_status_mask;
1454 if (lsr & UART_LSR_BI) {
1455 DEBUG_INTR("handling break....");
1457 } else if (lsr & UART_LSR_PE)
1459 else if (lsr & UART_LSR_FE)
1462 if (uart_handle_sysrq_char(port, ch))
1465 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1468 lsr = serial_in(up, UART_LSR);
1469 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (--max_count > 0));
1470 spin_unlock(&port->lock);
1471 tty_flip_buffer_push(&port->state->port);
1472 spin_lock(&port->lock);
1475 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1477 void serial8250_tx_chars(struct uart_8250_port *up)
1479 struct uart_port *port = &up->port;
1480 struct circ_buf *xmit = &port->state->xmit;
1484 serial_out(up, UART_TX, port->x_char);
1489 if (uart_tx_stopped(port)) {
1490 serial8250_stop_tx(port);
1493 if (uart_circ_empty(xmit)) {
1498 count = up->tx_loadsz;
1500 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1501 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1503 if (uart_circ_empty(xmit))
1505 if (up->capabilities & UART_CAP_HFIFO) {
1506 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1510 } while (--count > 0);
1512 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1513 uart_write_wakeup(port);
1515 DEBUG_INTR("THRE...");
1518 * With RPM enabled, we have to wait until the FIFO is empty before the
1519 * HW can go idle. So we get here once again with empty FIFO and disable
1520 * the interrupt and RPM in __stop_tx()
1522 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1525 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1527 /* Caller holds uart port lock */
1528 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1530 struct uart_port *port = &up->port;
1531 unsigned int status = serial_in(up, UART_MSR);
1533 status |= up->msr_saved_flags;
1534 up->msr_saved_flags = 0;
1535 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1536 port->state != NULL) {
1537 if (status & UART_MSR_TERI)
1539 if (status & UART_MSR_DDSR)
1541 if (status & UART_MSR_DDCD)
1542 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1543 if (status & UART_MSR_DCTS)
1544 uart_handle_cts_change(port, status & UART_MSR_CTS);
1546 wake_up_interruptible(&port->state->port.delta_msr_wait);
1551 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1554 * This handles the interrupt from one port.
1556 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1558 unsigned char status;
1559 unsigned long flags;
1560 struct uart_8250_port *up = up_to_u8250p(port);
1563 if (iir & UART_IIR_NO_INT)
1566 spin_lock_irqsave(&port->lock, flags);
1568 status = serial_port_in(port, UART_LSR);
1570 DEBUG_INTR("status = %x...", status);
1572 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1574 dma_err = up->dma->rx_dma(up, iir);
1576 if (!up->dma || dma_err)
1577 status = serial8250_rx_chars(up, status);
1579 serial8250_modem_status(up);
1580 if ((!up->dma || (up->dma && up->dma->tx_err)) &&
1581 (status & UART_LSR_THRE))
1582 serial8250_tx_chars(up);
1584 spin_unlock_irqrestore(&port->lock, flags);
1587 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1589 static int serial8250_default_handle_irq(struct uart_port *port)
1591 struct uart_8250_port *up = up_to_u8250p(port);
1595 serial8250_rpm_get(up);
1597 iir = serial_port_in(port, UART_IIR);
1598 ret = serial8250_handle_irq(port, iir);
1600 serial8250_rpm_put(up);
1605 * These Exar UARTs have an extra interrupt indicator that could
1606 * fire for a few unimplemented interrupts. One of which is a
1607 * wakeup event when coming out of sleep. Put this here just
1608 * to be on the safe side that these interrupts don't go unhandled.
1610 static int exar_handle_irq(struct uart_port *port)
1612 unsigned char int0, int1, int2, int3;
1613 unsigned int iir = serial_port_in(port, UART_IIR);
1616 ret = serial8250_handle_irq(port, iir);
1618 if ((port->type == PORT_XR17V35X) ||
1619 (port->type == PORT_XR17D15X)) {
1620 int0 = serial_port_in(port, 0x80);
1621 int1 = serial_port_in(port, 0x81);
1622 int2 = serial_port_in(port, 0x82);
1623 int3 = serial_port_in(port, 0x83);
1629 static unsigned int serial8250_tx_empty(struct uart_port *port)
1631 struct uart_8250_port *up = up_to_u8250p(port);
1632 unsigned long flags;
1635 serial8250_rpm_get(up);
1637 spin_lock_irqsave(&port->lock, flags);
1638 lsr = serial_port_in(port, UART_LSR);
1639 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1640 spin_unlock_irqrestore(&port->lock, flags);
1642 serial8250_rpm_put(up);
1644 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1647 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1649 struct uart_8250_port *up = up_to_u8250p(port);
1650 unsigned int status;
1653 serial8250_rpm_get(up);
1654 status = serial8250_modem_status(up);
1655 serial8250_rpm_put(up);
1658 if (status & UART_MSR_DCD)
1660 if (status & UART_MSR_RI)
1662 if (status & UART_MSR_DSR)
1664 if (status & UART_MSR_CTS)
1669 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1671 struct uart_8250_port *up = up_to_u8250p(port);
1672 unsigned char mcr = 0;
1674 if (mctrl & TIOCM_RTS)
1675 mcr |= UART_MCR_RTS;
1676 if (mctrl & TIOCM_DTR)
1677 mcr |= UART_MCR_DTR;
1678 if (mctrl & TIOCM_OUT1)
1679 mcr |= UART_MCR_OUT1;
1680 if (mctrl & TIOCM_OUT2)
1681 mcr |= UART_MCR_OUT2;
1682 if (mctrl & TIOCM_LOOP)
1683 mcr |= UART_MCR_LOOP;
1685 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1687 serial_port_out(port, UART_MCR, mcr);
1689 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1691 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1693 if (port->set_mctrl)
1694 port->set_mctrl(port, mctrl);
1696 serial8250_do_set_mctrl(port, mctrl);
1699 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1701 struct uart_8250_port *up = up_to_u8250p(port);
1702 unsigned long flags;
1704 serial8250_rpm_get(up);
1705 spin_lock_irqsave(&port->lock, flags);
1706 if (break_state == -1)
1707 up->lcr |= UART_LCR_SBC;
1709 up->lcr &= ~UART_LCR_SBC;
1710 serial_port_out(port, UART_LCR, up->lcr);
1711 spin_unlock_irqrestore(&port->lock, flags);
1712 serial8250_rpm_put(up);
1716 * Wait for transmitter & holding register to empty
1718 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1720 unsigned int status, tmout = 10000;
1722 /* Wait up to 10ms for the character(s) to be sent. */
1724 status = serial_in(up, UART_LSR);
1726 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1728 if ((status & bits) == bits)
1735 /* Wait up to 1s for flow control if necessary */
1736 if (up->port.flags & UPF_CONS_FLOW) {
1738 for (tmout = 1000000; tmout; tmout--) {
1739 unsigned int msr = serial_in(up, UART_MSR);
1740 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1741 if (msr & UART_MSR_CTS)
1744 touch_nmi_watchdog();
1749 #ifdef CONFIG_CONSOLE_POLL
1751 * Console polling routines for writing and reading from the uart while
1752 * in an interrupt or debug context.
1755 static int serial8250_get_poll_char(struct uart_port *port)
1757 struct uart_8250_port *up = up_to_u8250p(port);
1761 serial8250_rpm_get(up);
1763 lsr = serial_port_in(port, UART_LSR);
1765 if (!(lsr & UART_LSR_DR)) {
1766 status = NO_POLL_CHAR;
1770 status = serial_port_in(port, UART_RX);
1772 serial8250_rpm_put(up);
1777 static void serial8250_put_poll_char(struct uart_port *port,
1781 struct uart_8250_port *up = up_to_u8250p(port);
1783 serial8250_rpm_get(up);
1785 * First save the IER then disable the interrupts
1787 ier = serial_port_in(port, UART_IER);
1788 if (up->capabilities & UART_CAP_UUE)
1789 serial_port_out(port, UART_IER, UART_IER_UUE);
1791 serial_port_out(port, UART_IER, 0);
1793 wait_for_xmitr(up, BOTH_EMPTY);
1795 * Send the character out.
1797 serial_port_out(port, UART_TX, c);
1800 * Finally, wait for transmitter to become empty
1801 * and restore the IER
1803 wait_for_xmitr(up, BOTH_EMPTY);
1804 serial_port_out(port, UART_IER, ier);
1805 serial8250_rpm_put(up);
1808 #endif /* CONFIG_CONSOLE_POLL */
1810 int serial8250_do_startup(struct uart_port *port)
1812 struct uart_8250_port *up = up_to_u8250p(port);
1813 unsigned long flags;
1814 unsigned char lsr, iir;
1817 if (!port->fifosize)
1818 port->fifosize = uart_config[port->type].fifo_size;
1820 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1821 if (!up->capabilities)
1822 up->capabilities = uart_config[port->type].flags;
1825 if (port->iotype != up->cur_iotype)
1826 set_io_from_upio(port);
1828 serial8250_rpm_get(up);
1829 if (port->type == PORT_16C950) {
1830 /* Wake up and initialize UART */
1832 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1833 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1834 serial_port_out(port, UART_IER, 0);
1835 serial_port_out(port, UART_LCR, 0);
1836 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1837 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1838 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1839 serial_port_out(port, UART_LCR, 0);
1842 #ifdef CONFIG_SERIAL_8250_RSA
1844 * If this is an RSA port, see if we can kick it up to the
1845 * higher speed clock.
1850 if (port->type == PORT_XR17V35X) {
1852 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
1853 * MCR [7:5] and MSR [7:0]
1855 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
1858 * Make sure all interrups are masked until initialization is
1859 * complete and the FIFOs are cleared
1861 serial_port_out(port, UART_IER, 0);
1865 * Clear the FIFO buffers and disable them.
1866 * (they will be reenabled in set_termios())
1868 serial8250_clear_fifos(up);
1871 * Clear the interrupt registers.
1873 serial_port_in(port, UART_LSR);
1874 serial_port_in(port, UART_RX);
1875 serial_port_in(port, UART_IIR);
1876 serial_port_in(port, UART_MSR);
1879 * At this point, there's no way the LSR could still be 0xff;
1880 * if it is, then bail out, because there's likely no UART
1883 if (!(port->flags & UPF_BUGGY_UART) &&
1884 (serial_port_in(port, UART_LSR) == 0xff)) {
1885 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1886 serial_index(port));
1892 * For a XR16C850, we need to set the trigger levels
1894 if (port->type == PORT_16850) {
1897 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1899 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1900 serial_port_out(port, UART_FCTR,
1901 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1902 serial_port_out(port, UART_TRG, UART_TRG_96);
1903 serial_port_out(port, UART_FCTR,
1904 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1905 serial_port_out(port, UART_TRG, UART_TRG_96);
1907 serial_port_out(port, UART_LCR, 0);
1913 * Test for UARTs that do not reassert THRE when the
1914 * transmitter is idle and the interrupt has already
1915 * been cleared. Real 16550s should always reassert
1916 * this interrupt whenever the transmitter is idle and
1917 * the interrupt is enabled. Delays are necessary to
1918 * allow register changes to become visible.
1920 spin_lock_irqsave(&port->lock, flags);
1921 if (up->port.irqflags & IRQF_SHARED)
1922 disable_irq_nosync(port->irq);
1924 wait_for_xmitr(up, UART_LSR_THRE);
1925 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1926 udelay(1); /* allow THRE to set */
1927 iir1 = serial_port_in(port, UART_IIR);
1928 serial_port_out(port, UART_IER, 0);
1929 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1930 udelay(1); /* allow a working UART time to re-assert THRE */
1931 iir = serial_port_in(port, UART_IIR);
1932 serial_port_out(port, UART_IER, 0);
1934 if (port->irqflags & IRQF_SHARED)
1935 enable_irq(port->irq);
1936 spin_unlock_irqrestore(&port->lock, flags);
1939 * If the interrupt is not reasserted, or we otherwise
1940 * don't trust the iir, setup a timer to kick the UART
1941 * on a regular basis.
1943 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
1944 up->port.flags & UPF_BUG_THRE) {
1945 up->bugs |= UART_BUG_THRE;
1949 retval = up->ops->setup_irq(up);
1954 * Now, initialize the UART
1956 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1958 spin_lock_irqsave(&port->lock, flags);
1959 if (up->port.flags & UPF_FOURPORT) {
1961 up->port.mctrl |= TIOCM_OUT1;
1964 * Most PC uarts need OUT2 raised to enable interrupts.
1967 up->port.mctrl |= TIOCM_OUT2;
1969 serial8250_set_mctrl(port, port->mctrl);
1971 /* Serial over Lan (SoL) hack:
1972 Intel 8257x Gigabit ethernet chips have a
1973 16550 emulation, to be used for Serial Over Lan.
1974 Those chips take a longer time than a normal
1975 serial device to signalize that a transmission
1976 data was queued. Due to that, the above test generally
1977 fails. One solution would be to delay the reading of
1978 iir. However, this is not reliable, since the timeout
1979 is variable. So, let's just don't test if we receive
1980 TX irq. This way, we'll never enable UART_BUG_TXEN.
1982 if (up->port.flags & UPF_NO_TXEN_TEST)
1983 goto dont_test_tx_en;
1986 * Do a quick test to see if we receive an
1987 * interrupt when we enable the TX irq.
1989 serial_port_out(port, UART_IER, UART_IER_THRI);
1990 lsr = serial_port_in(port, UART_LSR);
1991 iir = serial_port_in(port, UART_IIR);
1992 serial_port_out(port, UART_IER, 0);
1994 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1995 if (!(up->bugs & UART_BUG_TXEN)) {
1996 up->bugs |= UART_BUG_TXEN;
1997 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1998 serial_index(port));
2001 up->bugs &= ~UART_BUG_TXEN;
2005 spin_unlock_irqrestore(&port->lock, flags);
2008 * Clear the interrupt registers again for luck, and clear the
2009 * saved flags to avoid getting false values from polling
2010 * routines or the previous session.
2012 serial_port_in(port, UART_LSR);
2013 serial_port_in(port, UART_RX);
2014 serial_port_in(port, UART_IIR);
2015 serial_port_in(port, UART_MSR);
2016 up->lsr_saved_flags = 0;
2017 up->msr_saved_flags = 0;
2020 * Request DMA channels for both RX and TX.
2023 retval = serial8250_request_dma(up);
2025 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2026 serial_index(port));
2032 * Set the IER shadow for rx interrupts but defer actual interrupt
2033 * enable until after the FIFOs are enabled; otherwise, an already-
2034 * active sender can swamp the interrupt handler with "too much work".
2036 up->ier = UART_IER_RLSI | UART_IER_RDI;
2038 if (port->flags & UPF_FOURPORT) {
2041 * Enable interrupts on the AST Fourport board
2043 icp = (port->iobase & 0xfe0) | 0x01f;
2049 serial8250_rpm_put(up);
2052 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2054 static int serial8250_startup(struct uart_port *port)
2057 return port->startup(port);
2058 return serial8250_do_startup(port);
2061 void serial8250_do_shutdown(struct uart_port *port)
2063 struct uart_8250_port *up = up_to_u8250p(port);
2064 unsigned long flags;
2066 serial8250_rpm_get(up);
2068 * Disable interrupts from this port
2071 serial_port_out(port, UART_IER, 0);
2074 serial8250_release_dma(up);
2076 spin_lock_irqsave(&port->lock, flags);
2077 if (port->flags & UPF_FOURPORT) {
2078 /* reset interrupts on the AST Fourport board */
2079 inb((port->iobase & 0xfe0) | 0x1f);
2080 port->mctrl |= TIOCM_OUT1;
2082 port->mctrl &= ~TIOCM_OUT2;
2084 serial8250_set_mctrl(port, port->mctrl);
2085 spin_unlock_irqrestore(&port->lock, flags);
2088 * Disable break condition and FIFOs
2090 serial_port_out(port, UART_LCR,
2091 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2092 serial8250_clear_fifos(up);
2094 #ifdef CONFIG_SERIAL_8250_RSA
2096 * Reset the RSA board back to 115kbps compat mode.
2102 * Read data port to reset things, and then unlink from
2105 serial_port_in(port, UART_RX);
2106 serial8250_rpm_put(up);
2108 up->ops->release_irq(up);
2110 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2112 static void serial8250_shutdown(struct uart_port *port)
2115 port->shutdown(port);
2117 serial8250_do_shutdown(port);
2121 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2122 * Calculate divisor with extra 4-bit fractional portion
2124 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2128 struct uart_port *port = &up->port;
2129 unsigned int quot_16;
2131 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2132 *frac = quot_16 & 0x0f;
2134 return quot_16 >> 4;
2137 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2141 struct uart_port *port = &up->port;
2145 * Handle magic divisors for baud rates above baud_base on
2146 * SMSC SuperIO chips.
2149 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2150 baud == (port->uartclk/4))
2152 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2153 baud == (port->uartclk/8))
2155 else if (up->port.type == PORT_XR17V35X)
2156 quot = xr17v35x_get_divisor(up, baud, frac);
2158 quot = uart_get_divisor(port, baud);
2161 * Oxford Semi 952 rev B workaround
2163 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2169 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2174 switch (c_cflag & CSIZE) {
2176 cval = UART_LCR_WLEN5;
2179 cval = UART_LCR_WLEN6;
2182 cval = UART_LCR_WLEN7;
2186 cval = UART_LCR_WLEN8;
2190 if (c_cflag & CSTOPB)
2191 cval |= UART_LCR_STOP;
2192 if (c_cflag & PARENB) {
2193 cval |= UART_LCR_PARITY;
2194 if (up->bugs & UART_BUG_PARITY)
2195 up->fifo_bug = true;
2197 if (!(c_cflag & PARODD))
2198 cval |= UART_LCR_EPAR;
2200 if (c_cflag & CMSPAR)
2201 cval |= UART_LCR_SPAR;
2207 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2208 unsigned int quot, unsigned int quot_frac)
2210 struct uart_8250_port *up = up_to_u8250p(port);
2212 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2213 if (is_omap1510_8250(up)) {
2214 if (baud == 115200) {
2216 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2218 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2222 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2223 * otherwise just set DLAB
2225 if (up->capabilities & UART_NATSEMI)
2226 serial_port_out(port, UART_LCR, 0xe0);
2228 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2230 serial_dl_write(up, quot);
2232 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2233 if (up->port.type == PORT_XR17V35X)
2234 serial_port_out(port, 0x2, quot_frac);
2238 serial8250_get_baud_rate(struct uart_port *port, struct ktermios *termios,
2239 struct ktermios *old)
2241 unsigned int tolerance = port->uartclk / 100;
2244 * Ask the core to calculate the divisor for us.
2245 * Allow 1% tolerance at the upper limit so uart clks marginally
2246 * slower than nominal still match standard baud rates without
2247 * causing transmission errors.
2249 return uart_get_baud_rate(port, termios, old,
2250 port->uartclk / 16 / 0xffff,
2251 (port->uartclk + tolerance) / 16);
2255 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2256 struct ktermios *old)
2258 struct uart_8250_port *up = up_to_u8250p(port);
2260 unsigned long flags;
2261 unsigned int baud, quot, frac = 0;
2263 cval = serial8250_compute_lcr(up, termios->c_cflag);
2265 baud = serial8250_get_baud_rate(port, termios, old);
2266 quot = serial8250_get_divisor(up, baud, &frac);
2269 * Ok, we're now changing the port state. Do it with
2270 * interrupts disabled.
2272 serial8250_rpm_get(up);
2273 spin_lock_irqsave(&port->lock, flags);
2275 up->lcr = cval; /* Save computed LCR */
2277 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2278 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2279 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2280 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2281 up->fcr |= UART_FCR_TRIGGER_1;
2286 * MCR-based auto flow control. When AFE is enabled, RTS will be
2287 * deasserted when the receive FIFO contains more characters than
2288 * the trigger, or the MCR RTS bit is cleared. In the case where
2289 * the remote UART is not using CTS auto flow control, we must
2290 * have sufficient FIFO entries for the latency of the remote
2291 * UART to respond. IOW, at least 32 bytes of FIFO.
2293 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2294 up->mcr &= ~UART_MCR_AFE;
2295 if (termios->c_cflag & CRTSCTS)
2296 up->mcr |= UART_MCR_AFE;
2300 * Update the per-port timeout.
2302 uart_update_timeout(port, termios->c_cflag, baud);
2304 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2305 if (termios->c_iflag & INPCK)
2306 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2307 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2308 port->read_status_mask |= UART_LSR_BI;
2311 * Characteres to ignore
2313 port->ignore_status_mask = 0;
2314 if (termios->c_iflag & IGNPAR)
2315 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2316 if (termios->c_iflag & IGNBRK) {
2317 port->ignore_status_mask |= UART_LSR_BI;
2319 * If we're ignoring parity and break indicators,
2320 * ignore overruns too (for real raw support).
2322 if (termios->c_iflag & IGNPAR)
2323 port->ignore_status_mask |= UART_LSR_OE;
2327 * ignore all characters if CREAD is not set
2329 if ((termios->c_cflag & CREAD) == 0)
2330 port->ignore_status_mask |= UART_LSR_DR;
2333 * CTS flow control flag and modem status interrupts
2335 up->ier &= ~UART_IER_MSI;
2336 if (!(up->bugs & UART_BUG_NOMSR) &&
2337 UART_ENABLE_MS(&up->port, termios->c_cflag))
2338 up->ier |= UART_IER_MSI;
2339 if (up->capabilities & UART_CAP_UUE)
2340 up->ier |= UART_IER_UUE;
2341 if (up->capabilities & UART_CAP_RTOIE)
2342 up->ier |= UART_IER_RTOIE;
2344 serial_port_out(port, UART_IER, up->ier);
2346 if (up->capabilities & UART_CAP_EFR) {
2347 unsigned char efr = 0;
2349 * TI16C752/Startech hardware flow control. FIXME:
2350 * - TI16C752 requires control thresholds to be set.
2351 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2353 if (termios->c_cflag & CRTSCTS)
2354 efr |= UART_EFR_CTS;
2356 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2357 if (port->flags & UPF_EXAR_EFR)
2358 serial_port_out(port, UART_XR_EFR, efr);
2360 serial_port_out(port, UART_EFR, efr);
2363 serial8250_set_divisor(port, baud, quot, frac);
2366 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2367 * is written without DLAB set, this mode will be disabled.
2369 if (port->type == PORT_16750)
2370 serial_port_out(port, UART_FCR, up->fcr);
2372 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2373 if (port->type != PORT_16750) {
2374 /* emulated UARTs (Lucent Venus 167x) need two steps */
2375 if (up->fcr & UART_FCR_ENABLE_FIFO)
2376 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2377 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2379 serial8250_set_mctrl(port, port->mctrl);
2380 spin_unlock_irqrestore(&port->lock, flags);
2381 serial8250_rpm_put(up);
2383 /* Don't rewrite B0 */
2384 if (tty_termios_baud_rate(termios))
2385 tty_termios_encode_baud_rate(termios, baud, baud);
2387 EXPORT_SYMBOL(serial8250_do_set_termios);
2390 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2391 struct ktermios *old)
2393 if (port->set_termios)
2394 port->set_termios(port, termios, old);
2396 serial8250_do_set_termios(port, termios, old);
2400 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2402 if (termios->c_line == N_PPS) {
2403 port->flags |= UPF_HARDPPS_CD;
2404 spin_lock_irq(&port->lock);
2405 serial8250_enable_ms(port);
2406 spin_unlock_irq(&port->lock);
2408 port->flags &= ~UPF_HARDPPS_CD;
2409 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2410 spin_lock_irq(&port->lock);
2411 serial8250_disable_ms(port);
2412 spin_unlock_irq(&port->lock);
2418 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2419 unsigned int oldstate)
2421 struct uart_8250_port *p = up_to_u8250p(port);
2423 serial8250_set_sleep(p, state != 0);
2425 EXPORT_SYMBOL(serial8250_do_pm);
2428 serial8250_pm(struct uart_port *port, unsigned int state,
2429 unsigned int oldstate)
2432 port->pm(port, state, oldstate);
2434 serial8250_do_pm(port, state, oldstate);
2437 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2439 if (pt->port.mapsize)
2440 return pt->port.mapsize;
2441 if (pt->port.iotype == UPIO_AU) {
2442 if (pt->port.type == PORT_RT2880)
2446 if (is_omap1_8250(pt))
2447 return 0x16 << pt->port.regshift;
2449 return 8 << pt->port.regshift;
2453 * Resource handling.
2455 static int serial8250_request_std_resource(struct uart_8250_port *up)
2457 unsigned int size = serial8250_port_size(up);
2458 struct uart_port *port = &up->port;
2461 switch (port->iotype) {
2470 if (!request_mem_region(port->mapbase, size, "serial")) {
2475 if (port->flags & UPF_IOREMAP) {
2476 port->membase = ioremap_nocache(port->mapbase, size);
2477 if (!port->membase) {
2478 release_mem_region(port->mapbase, size);
2486 if (!request_region(port->iobase, size, "serial"))
2493 static void serial8250_release_std_resource(struct uart_8250_port *up)
2495 unsigned int size = serial8250_port_size(up);
2496 struct uart_port *port = &up->port;
2498 switch (port->iotype) {
2507 if (port->flags & UPF_IOREMAP) {
2508 iounmap(port->membase);
2509 port->membase = NULL;
2512 release_mem_region(port->mapbase, size);
2517 release_region(port->iobase, size);
2522 static void serial8250_release_port(struct uart_port *port)
2524 struct uart_8250_port *up = up_to_u8250p(port);
2526 serial8250_release_std_resource(up);
2529 static int serial8250_request_port(struct uart_port *port)
2531 struct uart_8250_port *up = up_to_u8250p(port);
2533 return serial8250_request_std_resource(up);
2536 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2538 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2539 unsigned char bytes;
2541 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2543 return bytes ? bytes : -EOPNOTSUPP;
2546 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2548 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2551 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2554 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2555 if (bytes < conf_type->rxtrig_bytes[i])
2556 /* Use the nearest lower value */
2557 return (--i) << UART_FCR_R_TRIG_SHIFT;
2560 return UART_FCR_R_TRIG_11;
2563 static int do_get_rxtrig(struct tty_port *port)
2565 struct uart_state *state = container_of(port, struct uart_state, port);
2566 struct uart_port *uport = state->uart_port;
2567 struct uart_8250_port *up =
2568 container_of(uport, struct uart_8250_port, port);
2570 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2573 return fcr_get_rxtrig_bytes(up);
2576 static int do_serial8250_get_rxtrig(struct tty_port *port)
2580 mutex_lock(&port->mutex);
2581 rxtrig_bytes = do_get_rxtrig(port);
2582 mutex_unlock(&port->mutex);
2584 return rxtrig_bytes;
2587 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2588 struct device_attribute *attr, char *buf)
2590 struct tty_port *port = dev_get_drvdata(dev);
2593 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2594 if (rxtrig_bytes < 0)
2595 return rxtrig_bytes;
2597 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2600 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2602 struct uart_state *state = container_of(port, struct uart_state, port);
2603 struct uart_port *uport = state->uart_port;
2604 struct uart_8250_port *up =
2605 container_of(uport, struct uart_8250_port, port);
2608 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2612 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2616 serial8250_clear_fifos(up);
2617 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2618 up->fcr |= (unsigned char)rxtrig;
2619 serial_out(up, UART_FCR, up->fcr);
2623 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2627 mutex_lock(&port->mutex);
2628 ret = do_set_rxtrig(port, bytes);
2629 mutex_unlock(&port->mutex);
2634 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2635 struct device_attribute *attr, const char *buf, size_t count)
2637 struct tty_port *port = dev_get_drvdata(dev);
2638 unsigned char bytes;
2644 ret = kstrtou8(buf, 10, &bytes);
2648 ret = do_serial8250_set_rxtrig(port, bytes);
2655 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2656 serial8250_get_attr_rx_trig_bytes,
2657 serial8250_set_attr_rx_trig_bytes);
2659 static struct attribute *serial8250_dev_attrs[] = {
2660 &dev_attr_rx_trig_bytes.attr,
2664 static struct attribute_group serial8250_dev_attr_group = {
2665 .attrs = serial8250_dev_attrs,
2668 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2670 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2672 if (conf_type->rxtrig_bytes[0])
2673 up->port.attr_group = &serial8250_dev_attr_group;
2676 static void serial8250_config_port(struct uart_port *port, int flags)
2678 struct uart_8250_port *up = up_to_u8250p(port);
2682 * Find the region that we can probe for. This in turn
2683 * tells us whether we can probe for the type of port.
2685 ret = serial8250_request_std_resource(up);
2689 if (port->iotype != up->cur_iotype)
2690 set_io_from_upio(port);
2692 if (flags & UART_CONFIG_TYPE)
2695 /* if access method is AU, it is a 16550 with a quirk */
2696 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2697 up->bugs |= UART_BUG_NOMSR;
2699 /* HW bugs may trigger IRQ while IIR == NO_INT */
2700 if (port->type == PORT_TEGRA)
2701 up->bugs |= UART_BUG_NOMSR;
2703 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2706 if (port->type == PORT_UNKNOWN)
2707 serial8250_release_std_resource(up);
2709 /* Fixme: probably not the best place for this */
2710 if ((port->type == PORT_XR17V35X) ||
2711 (port->type == PORT_XR17D15X))
2712 port->handle_irq = exar_handle_irq;
2714 register_dev_spec_attr_grp(up);
2715 up->fcr = uart_config[up->port.type].fcr;
2719 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2721 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2722 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2723 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2724 ser->type == PORT_STARTECH)
2730 serial8250_type(struct uart_port *port)
2732 int type = port->type;
2734 if (type >= ARRAY_SIZE(uart_config))
2736 return uart_config[type].name;
2739 static const struct uart_ops serial8250_pops = {
2740 .tx_empty = serial8250_tx_empty,
2741 .set_mctrl = serial8250_set_mctrl,
2742 .get_mctrl = serial8250_get_mctrl,
2743 .stop_tx = serial8250_stop_tx,
2744 .start_tx = serial8250_start_tx,
2745 .throttle = serial8250_throttle,
2746 .unthrottle = serial8250_unthrottle,
2747 .stop_rx = serial8250_stop_rx,
2748 .enable_ms = serial8250_enable_ms,
2749 .break_ctl = serial8250_break_ctl,
2750 .startup = serial8250_startup,
2751 .shutdown = serial8250_shutdown,
2752 .set_termios = serial8250_set_termios,
2753 .set_ldisc = serial8250_set_ldisc,
2754 .pm = serial8250_pm,
2755 .type = serial8250_type,
2756 .release_port = serial8250_release_port,
2757 .request_port = serial8250_request_port,
2758 .config_port = serial8250_config_port,
2759 .verify_port = serial8250_verify_port,
2760 #ifdef CONFIG_CONSOLE_POLL
2761 .poll_get_char = serial8250_get_poll_char,
2762 .poll_put_char = serial8250_put_poll_char,
2766 void serial8250_init_port(struct uart_8250_port *up)
2768 struct uart_port *port = &up->port;
2770 spin_lock_init(&port->lock);
2771 port->ops = &serial8250_pops;
2773 up->cur_iotype = 0xFF;
2775 EXPORT_SYMBOL_GPL(serial8250_init_port);
2777 void serial8250_set_defaults(struct uart_8250_port *up)
2779 struct uart_port *port = &up->port;
2781 if (up->port.flags & UPF_FIXED_TYPE) {
2782 unsigned int type = up->port.type;
2784 if (!up->port.fifosize)
2785 up->port.fifosize = uart_config[type].fifo_size;
2787 up->tx_loadsz = uart_config[type].tx_loadsz;
2788 if (!up->capabilities)
2789 up->capabilities = uart_config[type].flags;
2792 set_io_from_upio(port);
2794 /* default dma handlers */
2796 if (!up->dma->tx_dma)
2797 up->dma->tx_dma = serial8250_tx_dma;
2798 if (!up->dma->rx_dma)
2799 up->dma->rx_dma = serial8250_rx_dma;
2802 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
2804 #ifdef CONFIG_SERIAL_8250_CONSOLE
2806 static void serial8250_console_putchar(struct uart_port *port, int ch)
2808 struct uart_8250_port *up = up_to_u8250p(port);
2810 wait_for_xmitr(up, UART_LSR_THRE);
2811 serial_port_out(port, UART_TX, ch);
2815 * Restore serial console when h/w power-off detected
2817 static void serial8250_console_restore(struct uart_8250_port *up)
2819 struct uart_port *port = &up->port;
2820 struct ktermios termios;
2821 unsigned int baud, quot, frac = 0;
2823 termios.c_cflag = port->cons->cflag;
2824 if (port->state->port.tty && termios.c_cflag == 0)
2825 termios.c_cflag = port->state->port.tty->termios.c_cflag;
2827 baud = serial8250_get_baud_rate(port, &termios, NULL);
2828 quot = serial8250_get_divisor(up, baud, &frac);
2830 serial8250_set_divisor(port, baud, quot, frac);
2831 serial_port_out(port, UART_LCR, up->lcr);
2832 serial_port_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
2836 * Print a string to the serial port trying not to disturb
2837 * any possible real use of the port...
2839 * The console_lock must be held when we get here.
2841 void serial8250_console_write(struct uart_8250_port *up, const char *s,
2844 struct uart_port *port = &up->port;
2845 unsigned long flags;
2849 touch_nmi_watchdog();
2851 serial8250_rpm_get(up);
2855 else if (oops_in_progress || in_kdb_printk())
2856 locked = spin_trylock_irqsave(&port->lock, flags);
2858 spin_lock_irqsave(&port->lock, flags);
2861 * First save the IER then disable the interrupts
2863 ier = serial_port_in(port, UART_IER);
2865 if (up->capabilities & UART_CAP_UUE)
2866 serial_port_out(port, UART_IER, UART_IER_UUE);
2868 serial_port_out(port, UART_IER, 0);
2870 /* check scratch reg to see if port powered off during system sleep */
2871 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
2872 serial8250_console_restore(up);
2876 uart_console_write(port, s, count, serial8250_console_putchar);
2879 * Finally, wait for transmitter to become empty
2880 * and restore the IER
2882 wait_for_xmitr(up, BOTH_EMPTY);
2883 serial_port_out(port, UART_IER, ier);
2886 * The receive handling will happen properly because the
2887 * receive ready bit will still be set; it is not cleared
2888 * on read. However, modem control will not, we must
2889 * call it if we have saved something in the saved flags
2890 * while processing with interrupts off.
2892 if (up->msr_saved_flags)
2893 serial8250_modem_status(up);
2896 spin_unlock_irqrestore(&port->lock, flags);
2897 serial8250_rpm_put(up);
2900 static unsigned int probe_baud(struct uart_port *port)
2902 unsigned char lcr, dll, dlm;
2905 lcr = serial_port_in(port, UART_LCR);
2906 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
2907 dll = serial_port_in(port, UART_DLL);
2908 dlm = serial_port_in(port, UART_DLM);
2909 serial_port_out(port, UART_LCR, lcr);
2911 quot = (dlm << 8) | dll;
2912 return (port->uartclk / 16) / quot;
2915 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
2922 if (!port->iobase && !port->membase)
2926 uart_parse_options(options, &baud, &parity, &bits, &flow);
2928 baud = probe_baud(port);
2930 return uart_set_options(port, port->cons, baud, parity, bits, flow);
2933 #endif /* CONFIG_SERIAL_8250_CONSOLE */
2935 MODULE_LICENSE("GPL");