2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/kdb.h>
39 #include <linux/uaccess.h>
40 #include <linux/pm_runtime.h>
51 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
53 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
56 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
59 * Here we define the default xmit fifo size used for each type of UART.
61 static const struct serial8250_config uart_config[] = {
86 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
87 .rxtrig_bytes = {1, 4, 8, 14},
88 .flags = UART_CAP_FIFO,
99 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
105 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
107 .rxtrig_bytes = {8, 16, 24, 28},
108 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
114 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
116 .rxtrig_bytes = {1, 16, 32, 56},
117 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
125 .name = "16C950/954",
128 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
129 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
130 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
136 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
138 .rxtrig_bytes = {8, 16, 56, 60},
139 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
145 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
146 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
152 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
153 .flags = UART_CAP_FIFO,
159 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
160 .flags = UART_CAP_FIFO | UART_NATSEMI,
166 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
167 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
173 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
174 .flags = UART_CAP_FIFO,
180 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
181 .flags = UART_CAP_FIFO | UART_CAP_AFE,
187 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
188 .flags = UART_CAP_FIFO | UART_CAP_AFE,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
196 .rxtrig_bytes = {1, 4, 8, 14},
197 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
203 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
204 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
211 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
213 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
220 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
221 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
222 .flags = UART_CAP_FIFO,
224 [PORT_BRCM_TRUMANAGE] = {
228 .flags = UART_CAP_HFIFO,
233 [PORT_ALTR_16550_F32] = {
234 .name = "Altera 16550 FIFO32",
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
238 .flags = UART_CAP_FIFO | UART_CAP_AFE,
240 [PORT_ALTR_16550_F64] = {
241 .name = "Altera 16550 FIFO64",
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_CAP_AFE,
247 [PORT_ALTR_16550_F128] = {
248 .name = "Altera 16550 FIFO128",
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_AFE,
254 /* tx_loadsz is set to 63-bytes instead of 64-bytes to implement
255 workaround of errata A-008006 which states that tx_loadsz should be
256 configured less than Maximum supported fifo bytes */
257 [PORT_16550A_FSL64] = {
258 .name = "16550A_FSL64",
261 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
263 .flags = UART_CAP_FIFO,
266 .name = "Palmchip BK-3103",
269 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
270 .rxtrig_bytes = {1, 4, 8, 14},
271 .flags = UART_CAP_FIFO,
275 /* Uart divisor latch read */
276 static int default_serial_dl_read(struct uart_8250_port *up)
278 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
281 /* Uart divisor latch write */
282 static void default_serial_dl_write(struct uart_8250_port *up, int value)
284 serial_out(up, UART_DLL, value & 0xff);
285 serial_out(up, UART_DLM, value >> 8 & 0xff);
288 #ifdef CONFIG_SERIAL_8250_RT288X
290 /* Au1x00/RT288x UART hardware has a weird register layout */
291 static const s8 au_io_in_map[8] = {
299 -1, /* UART_SCR (unmapped) */
302 static const s8 au_io_out_map[8] = {
308 -1, /* UART_LSR (unmapped) */
309 -1, /* UART_MSR (unmapped) */
310 -1, /* UART_SCR (unmapped) */
313 static unsigned int au_serial_in(struct uart_port *p, int offset)
315 if (offset >= ARRAY_SIZE(au_io_in_map))
317 offset = au_io_in_map[offset];
320 return __raw_readl(p->membase + (offset << p->regshift));
323 static void au_serial_out(struct uart_port *p, int offset, int value)
325 if (offset >= ARRAY_SIZE(au_io_out_map))
327 offset = au_io_out_map[offset];
330 __raw_writel(value, p->membase + (offset << p->regshift));
333 /* Au1x00 haven't got a standard divisor latch */
334 static int au_serial_dl_read(struct uart_8250_port *up)
336 return __raw_readl(up->port.membase + 0x28);
339 static void au_serial_dl_write(struct uart_8250_port *up, int value)
341 __raw_writel(value, up->port.membase + 0x28);
346 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
348 offset = offset << p->regshift;
349 outb(p->hub6 - 1 + offset, p->iobase);
350 return inb(p->iobase + 1);
353 static void hub6_serial_out(struct uart_port *p, int offset, int value)
355 offset = offset << p->regshift;
356 outb(p->hub6 - 1 + offset, p->iobase);
357 outb(value, p->iobase + 1);
360 static unsigned int mem_serial_in(struct uart_port *p, int offset)
362 offset = offset << p->regshift;
363 return readb(p->membase + offset);
366 static void mem_serial_out(struct uart_port *p, int offset, int value)
368 offset = offset << p->regshift;
369 writeb(value, p->membase + offset);
372 static void mem32_serial_out(struct uart_port *p, int offset, int value)
374 offset = offset << p->regshift;
375 writel(value, p->membase + offset);
378 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
380 offset = offset << p->regshift;
381 return readl(p->membase + offset);
384 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
386 offset = offset << p->regshift;
387 iowrite32be(value, p->membase + offset);
390 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
392 offset = offset << p->regshift;
393 return ioread32be(p->membase + offset);
396 static unsigned int io_serial_in(struct uart_port *p, int offset)
398 offset = offset << p->regshift;
399 return inb(p->iobase + offset);
402 static void io_serial_out(struct uart_port *p, int offset, int value)
404 offset = offset << p->regshift;
405 outb(value, p->iobase + offset);
408 static int serial8250_default_handle_irq(struct uart_port *port);
409 static int exar_handle_irq(struct uart_port *port);
411 static void set_io_from_upio(struct uart_port *p)
413 struct uart_8250_port *up = up_to_u8250p(p);
415 up->dl_read = default_serial_dl_read;
416 up->dl_write = default_serial_dl_write;
420 p->serial_in = hub6_serial_in;
421 p->serial_out = hub6_serial_out;
425 p->serial_in = mem_serial_in;
426 p->serial_out = mem_serial_out;
430 p->serial_in = mem32_serial_in;
431 p->serial_out = mem32_serial_out;
435 p->serial_in = mem32be_serial_in;
436 p->serial_out = mem32be_serial_out;
439 #ifdef CONFIG_SERIAL_8250_RT288X
441 p->serial_in = au_serial_in;
442 p->serial_out = au_serial_out;
443 up->dl_read = au_serial_dl_read;
444 up->dl_write = au_serial_dl_write;
449 p->serial_in = io_serial_in;
450 p->serial_out = io_serial_out;
453 /* Remember loaded iotype */
454 up->cur_iotype = p->iotype;
455 p->handle_irq = serial8250_default_handle_irq;
459 serial_port_out_sync(struct uart_port *p, int offset, int value)
466 p->serial_out(p, offset, value);
467 p->serial_in(p, UART_LCR); /* safe, no side-effects */
470 p->serial_out(p, offset, value);
477 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
479 serial_out(up, UART_SCR, offset);
480 serial_out(up, UART_ICR, value);
483 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
487 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
488 serial_out(up, UART_SCR, offset);
489 value = serial_in(up, UART_ICR);
490 serial_icr_write(up, UART_ACR, up->acr);
498 static void serial8250_clear_fifos(struct uart_8250_port *p)
500 if (p->capabilities & UART_CAP_FIFO) {
501 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
502 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
503 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
504 serial_out(p, UART_FCR, 0);
508 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
510 serial8250_clear_fifos(p);
511 serial_out(p, UART_FCR, p->fcr);
513 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
515 void serial8250_rpm_get(struct uart_8250_port *p)
517 if (!(p->capabilities & UART_CAP_RPM))
519 pm_runtime_get_sync(p->port.dev);
521 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
523 void serial8250_rpm_put(struct uart_8250_port *p)
525 if (!(p->capabilities & UART_CAP_RPM))
527 pm_runtime_mark_last_busy(p->port.dev);
528 pm_runtime_put_autosuspend(p->port.dev);
530 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
533 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
534 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
535 * empty and the HW can idle again.
537 static void serial8250_rpm_get_tx(struct uart_8250_port *p)
539 unsigned char rpm_active;
541 if (!(p->capabilities & UART_CAP_RPM))
544 rpm_active = xchg(&p->rpm_tx_active, 1);
547 pm_runtime_get_sync(p->port.dev);
550 static void serial8250_rpm_put_tx(struct uart_8250_port *p)
552 unsigned char rpm_active;
554 if (!(p->capabilities & UART_CAP_RPM))
557 rpm_active = xchg(&p->rpm_tx_active, 0);
560 pm_runtime_mark_last_busy(p->port.dev);
561 pm_runtime_put_autosuspend(p->port.dev);
565 * IER sleep support. UARTs which have EFRs need the "extended
566 * capability" bit enabled. Note that on XR16C850s, we need to
567 * reset LCR to write to IER.
569 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
571 unsigned char lcr = 0, efr = 0;
573 * Exar UARTs have a SLEEP register that enables or disables
574 * each UART to enter sleep mode separately. On the XR17V35x the
575 * register is accessible to each UART at the UART_EXAR_SLEEP
576 * offset but the UART channel may only write to the corresponding
579 serial8250_rpm_get(p);
580 if ((p->port.type == PORT_XR17V35X) ||
581 (p->port.type == PORT_XR17D15X)) {
582 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
586 if (p->capabilities & UART_CAP_SLEEP) {
587 if (p->capabilities & UART_CAP_EFR) {
588 lcr = serial_in(p, UART_LCR);
589 efr = serial_in(p, UART_EFR);
590 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
591 serial_out(p, UART_EFR, UART_EFR_ECB);
592 serial_out(p, UART_LCR, 0);
594 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
595 if (p->capabilities & UART_CAP_EFR) {
596 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
597 serial_out(p, UART_EFR, efr);
598 serial_out(p, UART_LCR, lcr);
602 serial8250_rpm_put(p);
605 #ifdef CONFIG_SERIAL_8250_RSA
607 * Attempts to turn on the RSA FIFO. Returns zero on failure.
608 * We set the port uart clock rate if we succeed.
610 static int __enable_rsa(struct uart_8250_port *up)
615 mode = serial_in(up, UART_RSA_MSR);
616 result = mode & UART_RSA_MSR_FIFO;
619 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
620 mode = serial_in(up, UART_RSA_MSR);
621 result = mode & UART_RSA_MSR_FIFO;
625 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
630 static void enable_rsa(struct uart_8250_port *up)
632 if (up->port.type == PORT_RSA) {
633 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
634 spin_lock_irq(&up->port.lock);
636 spin_unlock_irq(&up->port.lock);
638 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
639 serial_out(up, UART_RSA_FRR, 0);
644 * Attempts to turn off the RSA FIFO. Returns zero on failure.
645 * It is unknown why interrupts were disabled in here. However,
646 * the caller is expected to preserve this behaviour by grabbing
647 * the spinlock before calling this function.
649 static void disable_rsa(struct uart_8250_port *up)
654 if (up->port.type == PORT_RSA &&
655 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
656 spin_lock_irq(&up->port.lock);
658 mode = serial_in(up, UART_RSA_MSR);
659 result = !(mode & UART_RSA_MSR_FIFO);
662 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
663 mode = serial_in(up, UART_RSA_MSR);
664 result = !(mode & UART_RSA_MSR_FIFO);
668 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
669 spin_unlock_irq(&up->port.lock);
672 #endif /* CONFIG_SERIAL_8250_RSA */
675 * This is a quickie test to see how big the FIFO is.
676 * It doesn't work at all the time, more's the pity.
678 static int size_fifo(struct uart_8250_port *up)
680 unsigned char old_fcr, old_mcr, old_lcr;
681 unsigned short old_dl;
684 old_lcr = serial_in(up, UART_LCR);
685 serial_out(up, UART_LCR, 0);
686 old_fcr = serial_in(up, UART_FCR);
687 old_mcr = serial_in(up, UART_MCR);
688 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
689 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
690 serial_out(up, UART_MCR, UART_MCR_LOOP);
691 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
692 old_dl = serial_dl_read(up);
693 serial_dl_write(up, 0x0001);
694 serial_out(up, UART_LCR, 0x03);
695 for (count = 0; count < 256; count++)
696 serial_out(up, UART_TX, count);
697 mdelay(20);/* FIXME - schedule_timeout */
698 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
699 (count < 256); count++)
700 serial_in(up, UART_RX);
701 serial_out(up, UART_FCR, old_fcr);
702 serial_out(up, UART_MCR, old_mcr);
703 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
704 serial_dl_write(up, old_dl);
705 serial_out(up, UART_LCR, old_lcr);
711 * Read UART ID using the divisor method - set DLL and DLM to zero
712 * and the revision will be in DLL and device type in DLM. We
713 * preserve the device state across this.
715 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
717 unsigned char old_lcr;
718 unsigned int id, old_dl;
720 old_lcr = serial_in(p, UART_LCR);
721 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
722 old_dl = serial_dl_read(p);
723 serial_dl_write(p, 0);
724 id = serial_dl_read(p);
725 serial_dl_write(p, old_dl);
727 serial_out(p, UART_LCR, old_lcr);
733 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
734 * When this function is called we know it is at least a StarTech
735 * 16650 V2, but it might be one of several StarTech UARTs, or one of
736 * its clones. (We treat the broken original StarTech 16650 V1 as a
737 * 16550, and why not? Startech doesn't seem to even acknowledge its
740 * What evil have men's minds wrought...
742 static void autoconfig_has_efr(struct uart_8250_port *up)
744 unsigned int id1, id2, id3, rev;
747 * Everything with an EFR has SLEEP
749 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
752 * First we check to see if it's an Oxford Semiconductor UART.
754 * If we have to do this here because some non-National
755 * Semiconductor clone chips lock up if you try writing to the
756 * LSR register (which serial_icr_read does)
760 * Check for Oxford Semiconductor 16C950.
762 * EFR [4] must be set else this test fails.
764 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
765 * claims that it's needed for 952 dual UART's (which are not
766 * recommended for new designs).
769 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
770 serial_out(up, UART_EFR, UART_EFR_ECB);
771 serial_out(up, UART_LCR, 0x00);
772 id1 = serial_icr_read(up, UART_ID1);
773 id2 = serial_icr_read(up, UART_ID2);
774 id3 = serial_icr_read(up, UART_ID3);
775 rev = serial_icr_read(up, UART_REV);
777 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
779 if (id1 == 0x16 && id2 == 0xC9 &&
780 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
781 up->port.type = PORT_16C950;
784 * Enable work around for the Oxford Semiconductor 952 rev B
785 * chip which causes it to seriously miscalculate baud rates
788 if (id3 == 0x52 && rev == 0x01)
789 up->bugs |= UART_BUG_QUOT;
794 * We check for a XR16C850 by setting DLL and DLM to 0, and then
795 * reading back DLL and DLM. The chip type depends on the DLM
797 * 0x10 - XR16C850 and the DLL contains the chip revision.
801 id1 = autoconfig_read_divisor_id(up);
802 DEBUG_AUTOCONF("850id=%04x ", id1);
805 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
806 up->port.type = PORT_16850;
811 * It wasn't an XR16C850.
813 * We distinguish between the '654 and the '650 by counting
814 * how many bytes are in the FIFO. I'm using this for now,
815 * since that's the technique that was sent to me in the
816 * serial driver update, but I'm not convinced this works.
817 * I've had problems doing this in the past. -TYT
819 if (size_fifo(up) == 64)
820 up->port.type = PORT_16654;
822 up->port.type = PORT_16650V2;
826 * We detected a chip without a FIFO. Only two fall into
827 * this category - the original 8250 and the 16450. The
828 * 16450 has a scratch register (accessible with LCR=0)
830 static void autoconfig_8250(struct uart_8250_port *up)
832 unsigned char scratch, status1, status2;
834 up->port.type = PORT_8250;
836 scratch = serial_in(up, UART_SCR);
837 serial_out(up, UART_SCR, 0xa5);
838 status1 = serial_in(up, UART_SCR);
839 serial_out(up, UART_SCR, 0x5a);
840 status2 = serial_in(up, UART_SCR);
841 serial_out(up, UART_SCR, scratch);
843 if (status1 == 0xa5 && status2 == 0x5a)
844 up->port.type = PORT_16450;
847 static int broken_efr(struct uart_8250_port *up)
850 * Exar ST16C2550 "A2" devices incorrectly detect as
851 * having an EFR, and report an ID of 0x0201. See
852 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
854 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
861 * We know that the chip has FIFOs. Does it have an EFR? The
862 * EFR is located in the same register position as the IIR and
863 * we know the top two bits of the IIR are currently set. The
864 * EFR should contain zero. Try to read the EFR.
866 static void autoconfig_16550a(struct uart_8250_port *up)
868 unsigned char status1, status2;
869 unsigned int iersave;
871 up->port.type = PORT_16550A;
872 up->capabilities |= UART_CAP_FIFO;
875 * XR17V35x UARTs have an extra divisor register, DLD
876 * that gets enabled with when DLAB is set which will
877 * cause the device to incorrectly match and assign
878 * port type to PORT_16650. The EFR for this UART is
879 * found at offset 0x09. Instead check the Deice ID (DVID)
880 * register for a 2, 4 or 8 port UART.
882 if (up->port.flags & UPF_EXAR_EFR) {
883 status1 = serial_in(up, UART_EXAR_DVID);
884 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
885 DEBUG_AUTOCONF("Exar XR17V35x ");
886 up->port.type = PORT_XR17V35X;
887 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
896 * Check for presence of the EFR when DLAB is set.
897 * Only ST16C650V1 UARTs pass this test.
899 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
900 if (serial_in(up, UART_EFR) == 0) {
901 serial_out(up, UART_EFR, 0xA8);
902 if (serial_in(up, UART_EFR) != 0) {
903 DEBUG_AUTOCONF("EFRv1 ");
904 up->port.type = PORT_16650;
905 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
907 serial_out(up, UART_LCR, 0);
908 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
910 status1 = serial_in(up, UART_IIR) >> 5;
911 serial_out(up, UART_FCR, 0);
912 serial_out(up, UART_LCR, 0);
915 up->port.type = PORT_16550A_FSL64;
917 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
919 serial_out(up, UART_EFR, 0);
924 * Maybe it requires 0xbf to be written to the LCR.
925 * (other ST16C650V2 UARTs, TI16C752A, etc)
927 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
928 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
929 DEBUG_AUTOCONF("EFRv2 ");
930 autoconfig_has_efr(up);
935 * Check for a National Semiconductor SuperIO chip.
936 * Attempt to switch to bank 2, read the value of the LOOP bit
937 * from EXCR1. Switch back to bank 0, change it in MCR. Then
938 * switch back to bank 2, read it from EXCR1 again and check
939 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
941 serial_out(up, UART_LCR, 0);
942 status1 = serial_in(up, UART_MCR);
943 serial_out(up, UART_LCR, 0xE0);
944 status2 = serial_in(up, 0x02); /* EXCR1 */
946 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
947 serial_out(up, UART_LCR, 0);
948 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
949 serial_out(up, UART_LCR, 0xE0);
950 status2 = serial_in(up, 0x02); /* EXCR1 */
951 serial_out(up, UART_LCR, 0);
952 serial_out(up, UART_MCR, status1);
954 if ((status2 ^ status1) & UART_MCR_LOOP) {
957 serial_out(up, UART_LCR, 0xE0);
959 quot = serial_dl_read(up);
962 if (ns16550a_goto_highspeed(up))
963 serial_dl_write(up, quot);
965 serial_out(up, UART_LCR, 0);
967 up->port.uartclk = 921600*16;
968 up->port.type = PORT_NS16550A;
969 up->capabilities |= UART_NATSEMI;
975 * No EFR. Try to detect a TI16750, which only sets bit 5 of
976 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
977 * Try setting it with and without DLAB set. Cheap clones
978 * set bit 5 without DLAB set.
980 serial_out(up, UART_LCR, 0);
981 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
982 status1 = serial_in(up, UART_IIR) >> 5;
983 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
984 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
985 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
986 status2 = serial_in(up, UART_IIR) >> 5;
987 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
988 serial_out(up, UART_LCR, 0);
990 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
992 if (status1 == 6 && status2 == 7) {
993 up->port.type = PORT_16750;
994 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
999 * Try writing and reading the UART_IER_UUE bit (b6).
1000 * If it works, this is probably one of the Xscale platform's
1002 * We're going to explicitly set the UUE bit to 0 before
1003 * trying to write and read a 1 just to make sure it's not
1004 * already a 1 and maybe locked there before we even start start.
1006 iersave = serial_in(up, UART_IER);
1007 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1008 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1010 * OK it's in a known zero state, try writing and reading
1011 * without disturbing the current state of the other bits.
1013 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1014 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1017 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1019 DEBUG_AUTOCONF("Xscale ");
1020 up->port.type = PORT_XSCALE;
1021 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1026 * If we got here we couldn't force the IER_UUE bit to 0.
1027 * Log it and continue.
1029 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1031 serial_out(up, UART_IER, iersave);
1034 * Exar uarts have EFR in a weird location
1036 if (up->port.flags & UPF_EXAR_EFR) {
1037 DEBUG_AUTOCONF("Exar XR17D15x ");
1038 up->port.type = PORT_XR17D15X;
1039 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1046 * We distinguish between 16550A and U6 16550A by counting
1047 * how many bytes are in the FIFO.
1049 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1050 up->port.type = PORT_U6_16550A;
1051 up->capabilities |= UART_CAP_AFE;
1056 * This routine is called by rs_init() to initialize a specific serial
1057 * port. It determines what type of UART chip this serial port is
1058 * using: 8250, 16450, 16550, 16550A. The important question is
1059 * whether or not this UART is a 16550A or not, since this will
1060 * determine whether or not we can use its FIFO features or not.
1062 static void autoconfig(struct uart_8250_port *up)
1064 unsigned char status1, scratch, scratch2, scratch3;
1065 unsigned char save_lcr, save_mcr;
1066 struct uart_port *port = &up->port;
1067 unsigned long flags;
1068 unsigned int old_capabilities;
1070 if (!port->iobase && !port->mapbase && !port->membase)
1073 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1074 serial_index(port), port->iobase, port->membase);
1077 * We really do need global IRQs disabled here - we're going to
1078 * be frobbing the chips IRQ enable register to see if it exists.
1080 spin_lock_irqsave(&port->lock, flags);
1082 up->capabilities = 0;
1085 if (!(port->flags & UPF_BUGGY_UART)) {
1087 * Do a simple existence test first; if we fail this,
1088 * there's no point trying anything else.
1090 * 0x80 is used as a nonsense port to prevent against
1091 * false positives due to ISA bus float. The
1092 * assumption is that 0x80 is a non-existent port;
1093 * which should be safe since include/asm/io.h also
1094 * makes this assumption.
1096 * Note: this is safe as long as MCR bit 4 is clear
1097 * and the device is in "PC" mode.
1099 scratch = serial_in(up, UART_IER);
1100 serial_out(up, UART_IER, 0);
1105 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1106 * 16C754B) allow only to modify them if an EFR bit is set.
1108 scratch2 = serial_in(up, UART_IER) & 0x0f;
1109 serial_out(up, UART_IER, 0x0F);
1113 scratch3 = serial_in(up, UART_IER) & 0x0f;
1114 serial_out(up, UART_IER, scratch);
1115 if (scratch2 != 0 || scratch3 != 0x0F) {
1117 * We failed; there's nothing here
1119 spin_unlock_irqrestore(&port->lock, flags);
1120 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1121 scratch2, scratch3);
1126 save_mcr = serial_in(up, UART_MCR);
1127 save_lcr = serial_in(up, UART_LCR);
1130 * Check to see if a UART is really there. Certain broken
1131 * internal modems based on the Rockwell chipset fail this
1132 * test, because they apparently don't implement the loopback
1133 * test mode. So this test is skipped on the COM 1 through
1134 * COM 4 ports. This *should* be safe, since no board
1135 * manufacturer would be stupid enough to design a board
1136 * that conflicts with COM 1-4 --- we hope!
1138 if (!(port->flags & UPF_SKIP_TEST)) {
1139 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1140 status1 = serial_in(up, UART_MSR) & 0xF0;
1141 serial_out(up, UART_MCR, save_mcr);
1142 if (status1 != 0x90) {
1143 spin_unlock_irqrestore(&port->lock, flags);
1144 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1151 * We're pretty sure there's a port here. Lets find out what
1152 * type of port it is. The IIR top two bits allows us to find
1153 * out if it's 8250 or 16450, 16550, 16550A or later. This
1154 * determines what we test for next.
1156 * We also initialise the EFR (if any) to zero for later. The
1157 * EFR occupies the same register location as the FCR and IIR.
1159 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1160 serial_out(up, UART_EFR, 0);
1161 serial_out(up, UART_LCR, 0);
1163 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1164 scratch = serial_in(up, UART_IIR) >> 6;
1168 autoconfig_8250(up);
1171 port->type = PORT_UNKNOWN;
1174 port->type = PORT_16550;
1177 autoconfig_16550a(up);
1181 #ifdef CONFIG_SERIAL_8250_RSA
1183 * Only probe for RSA ports if we got the region.
1185 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1187 port->type = PORT_RSA;
1190 serial_out(up, UART_LCR, save_lcr);
1192 port->fifosize = uart_config[up->port.type].fifo_size;
1193 old_capabilities = up->capabilities;
1194 up->capabilities = uart_config[port->type].flags;
1195 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1197 if (port->type == PORT_UNKNOWN)
1203 #ifdef CONFIG_SERIAL_8250_RSA
1204 if (port->type == PORT_RSA)
1205 serial_out(up, UART_RSA_FRR, 0);
1207 serial_out(up, UART_MCR, save_mcr);
1208 serial8250_clear_fifos(up);
1209 serial_in(up, UART_RX);
1210 if (up->capabilities & UART_CAP_UUE)
1211 serial_out(up, UART_IER, UART_IER_UUE);
1213 serial_out(up, UART_IER, 0);
1216 spin_unlock_irqrestore(&port->lock, flags);
1217 if (up->capabilities != old_capabilities) {
1219 "ttyS%d: detected caps %08x should be %08x\n",
1220 serial_index(port), old_capabilities,
1224 DEBUG_AUTOCONF("iir=%d ", scratch);
1225 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1228 static void autoconfig_irq(struct uart_8250_port *up)
1230 struct uart_port *port = &up->port;
1231 unsigned char save_mcr, save_ier;
1232 unsigned char save_ICP = 0;
1233 unsigned int ICP = 0;
1237 if (port->flags & UPF_FOURPORT) {
1238 ICP = (port->iobase & 0xfe0) | 0x1f;
1239 save_ICP = inb_p(ICP);
1244 if (uart_console(port))
1247 /* forget possible initially masked and pending IRQ */
1248 probe_irq_off(probe_irq_on());
1249 save_mcr = serial_in(up, UART_MCR);
1250 save_ier = serial_in(up, UART_IER);
1251 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1253 irqs = probe_irq_on();
1254 serial_out(up, UART_MCR, 0);
1256 if (port->flags & UPF_FOURPORT) {
1257 serial_out(up, UART_MCR,
1258 UART_MCR_DTR | UART_MCR_RTS);
1260 serial_out(up, UART_MCR,
1261 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1263 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1264 serial_in(up, UART_LSR);
1265 serial_in(up, UART_RX);
1266 serial_in(up, UART_IIR);
1267 serial_in(up, UART_MSR);
1268 serial_out(up, UART_TX, 0xFF);
1270 irq = probe_irq_off(irqs);
1272 serial_out(up, UART_MCR, save_mcr);
1273 serial_out(up, UART_IER, save_ier);
1275 if (port->flags & UPF_FOURPORT)
1276 outb_p(save_ICP, ICP);
1278 if (uart_console(port))
1281 port->irq = (irq > 0) ? irq : 0;
1284 static inline void __stop_tx(struct uart_8250_port *p)
1286 if (p->ier & UART_IER_THRI) {
1287 p->ier &= ~UART_IER_THRI;
1288 serial_out(p, UART_IER, p->ier);
1289 serial8250_rpm_put_tx(p);
1293 static void serial8250_stop_tx(struct uart_port *port)
1295 struct uart_8250_port *up = up_to_u8250p(port);
1297 serial8250_rpm_get(up);
1301 * We really want to stop the transmitter from sending.
1303 if (port->type == PORT_16C950) {
1304 up->acr |= UART_ACR_TXDIS;
1305 serial_icr_write(up, UART_ACR, up->acr);
1307 serial8250_rpm_put(up);
1310 static void serial8250_start_tx(struct uart_port *port)
1312 struct uart_8250_port *up = up_to_u8250p(port);
1314 serial8250_rpm_get_tx(up);
1316 if (up->dma && !up->dma->tx_dma(up))
1319 if (!(up->ier & UART_IER_THRI)) {
1320 up->ier |= UART_IER_THRI;
1321 serial_port_out(port, UART_IER, up->ier);
1323 if (up->bugs & UART_BUG_TXEN) {
1325 lsr = serial_in(up, UART_LSR);
1326 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1327 if (lsr & UART_LSR_THRE)
1328 serial8250_tx_chars(up);
1333 * Re-enable the transmitter if we disabled it.
1335 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1336 up->acr &= ~UART_ACR_TXDIS;
1337 serial_icr_write(up, UART_ACR, up->acr);
1341 static void serial8250_throttle(struct uart_port *port)
1343 port->throttle(port);
1346 static void serial8250_unthrottle(struct uart_port *port)
1348 port->unthrottle(port);
1351 static void serial8250_stop_rx(struct uart_port *port)
1353 struct uart_8250_port *up = up_to_u8250p(port);
1355 serial8250_rpm_get(up);
1357 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1358 up->port.read_status_mask &= ~UART_LSR_DR;
1359 serial_port_out(port, UART_IER, up->ier);
1361 serial8250_rpm_put(up);
1364 static void serial8250_disable_ms(struct uart_port *port)
1366 struct uart_8250_port *up =
1367 container_of(port, struct uart_8250_port, port);
1369 /* no MSR capabilities */
1370 if (up->bugs & UART_BUG_NOMSR)
1373 up->ier &= ~UART_IER_MSI;
1374 serial_port_out(port, UART_IER, up->ier);
1377 static void serial8250_enable_ms(struct uart_port *port)
1379 struct uart_8250_port *up = up_to_u8250p(port);
1381 /* no MSR capabilities */
1382 if (up->bugs & UART_BUG_NOMSR)
1385 up->ier |= UART_IER_MSI;
1387 serial8250_rpm_get(up);
1388 serial_port_out(port, UART_IER, up->ier);
1389 serial8250_rpm_put(up);
1393 * serial8250_rx_chars: processes according to the passed in LSR
1394 * value, and returns the remaining LSR bits not handled
1395 * by this Rx routine.
1398 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1400 struct uart_port *port = &up->port;
1402 int max_count = 256;
1406 if (likely(lsr & UART_LSR_DR))
1407 ch = serial_in(up, UART_RX);
1410 * Intel 82571 has a Serial Over Lan device that will
1411 * set UART_LSR_BI without setting UART_LSR_DR when
1412 * it receives a break. To avoid reading from the
1413 * receive buffer without UART_LSR_DR bit set, we
1414 * just force the read character to be 0
1421 lsr |= up->lsr_saved_flags;
1422 up->lsr_saved_flags = 0;
1424 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1425 if (lsr & UART_LSR_BI) {
1426 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1429 * We do the SysRQ and SAK checking
1430 * here because otherwise the break
1431 * may get masked by ignore_status_mask
1432 * or read_status_mask.
1434 if (uart_handle_break(port))
1436 } else if (lsr & UART_LSR_PE)
1437 port->icount.parity++;
1438 else if (lsr & UART_LSR_FE)
1439 port->icount.frame++;
1440 if (lsr & UART_LSR_OE)
1441 port->icount.overrun++;
1444 * Mask off conditions which should be ignored.
1446 lsr &= port->read_status_mask;
1448 if (lsr & UART_LSR_BI) {
1449 DEBUG_INTR("handling break....");
1451 } else if (lsr & UART_LSR_PE)
1453 else if (lsr & UART_LSR_FE)
1456 if (uart_handle_sysrq_char(port, ch))
1459 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1462 lsr = serial_in(up, UART_LSR);
1463 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (--max_count > 0));
1464 spin_unlock(&port->lock);
1465 tty_flip_buffer_push(&port->state->port);
1466 spin_lock(&port->lock);
1469 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1471 void serial8250_tx_chars(struct uart_8250_port *up)
1473 struct uart_port *port = &up->port;
1474 struct circ_buf *xmit = &port->state->xmit;
1478 serial_out(up, UART_TX, port->x_char);
1483 if (uart_tx_stopped(port)) {
1484 serial8250_stop_tx(port);
1487 if (uart_circ_empty(xmit)) {
1492 count = up->tx_loadsz;
1494 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1495 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1497 if (uart_circ_empty(xmit))
1499 if (up->capabilities & UART_CAP_HFIFO) {
1500 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1504 } while (--count > 0);
1506 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1507 uart_write_wakeup(port);
1509 DEBUG_INTR("THRE...");
1512 * With RPM enabled, we have to wait until the FIFO is empty before the
1513 * HW can go idle. So we get here once again with empty FIFO and disable
1514 * the interrupt and RPM in __stop_tx()
1516 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1519 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1521 /* Caller holds uart port lock */
1522 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1524 struct uart_port *port = &up->port;
1525 unsigned int status = serial_in(up, UART_MSR);
1527 status |= up->msr_saved_flags;
1528 up->msr_saved_flags = 0;
1529 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1530 port->state != NULL) {
1531 if (status & UART_MSR_TERI)
1533 if (status & UART_MSR_DDSR)
1535 if (status & UART_MSR_DDCD)
1536 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1537 if (status & UART_MSR_DCTS)
1538 uart_handle_cts_change(port, status & UART_MSR_CTS);
1540 wake_up_interruptible(&port->state->port.delta_msr_wait);
1545 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1548 * This handles the interrupt from one port.
1550 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1552 unsigned char status;
1553 unsigned long flags;
1554 struct uart_8250_port *up = up_to_u8250p(port);
1557 if (iir & UART_IIR_NO_INT)
1560 spin_lock_irqsave(&port->lock, flags);
1562 status = serial_port_in(port, UART_LSR);
1564 DEBUG_INTR("status = %x...", status);
1566 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1568 dma_err = up->dma->rx_dma(up, iir);
1570 if (!up->dma || dma_err)
1571 status = serial8250_rx_chars(up, status);
1573 serial8250_modem_status(up);
1574 if ((!up->dma || (up->dma && up->dma->tx_err)) &&
1575 (status & UART_LSR_THRE))
1576 serial8250_tx_chars(up);
1578 spin_unlock_irqrestore(&port->lock, flags);
1581 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1583 static int serial8250_default_handle_irq(struct uart_port *port)
1585 struct uart_8250_port *up = up_to_u8250p(port);
1589 serial8250_rpm_get(up);
1591 iir = serial_port_in(port, UART_IIR);
1592 ret = serial8250_handle_irq(port, iir);
1594 serial8250_rpm_put(up);
1599 * These Exar UARTs have an extra interrupt indicator that could
1600 * fire for a few unimplemented interrupts. One of which is a
1601 * wakeup event when coming out of sleep. Put this here just
1602 * to be on the safe side that these interrupts don't go unhandled.
1604 static int exar_handle_irq(struct uart_port *port)
1606 unsigned char int0, int1, int2, int3;
1607 unsigned int iir = serial_port_in(port, UART_IIR);
1610 ret = serial8250_handle_irq(port, iir);
1612 if ((port->type == PORT_XR17V35X) ||
1613 (port->type == PORT_XR17D15X)) {
1614 int0 = serial_port_in(port, 0x80);
1615 int1 = serial_port_in(port, 0x81);
1616 int2 = serial_port_in(port, 0x82);
1617 int3 = serial_port_in(port, 0x83);
1623 static unsigned int serial8250_tx_empty(struct uart_port *port)
1625 struct uart_8250_port *up = up_to_u8250p(port);
1626 unsigned long flags;
1629 serial8250_rpm_get(up);
1631 spin_lock_irqsave(&port->lock, flags);
1632 lsr = serial_port_in(port, UART_LSR);
1633 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1634 spin_unlock_irqrestore(&port->lock, flags);
1636 serial8250_rpm_put(up);
1638 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1641 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1643 struct uart_8250_port *up = up_to_u8250p(port);
1644 unsigned int status;
1647 serial8250_rpm_get(up);
1648 status = serial8250_modem_status(up);
1649 serial8250_rpm_put(up);
1652 if (status & UART_MSR_DCD)
1654 if (status & UART_MSR_RI)
1656 if (status & UART_MSR_DSR)
1658 if (status & UART_MSR_CTS)
1663 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1665 struct uart_8250_port *up = up_to_u8250p(port);
1666 unsigned char mcr = 0;
1668 if (mctrl & TIOCM_RTS)
1669 mcr |= UART_MCR_RTS;
1670 if (mctrl & TIOCM_DTR)
1671 mcr |= UART_MCR_DTR;
1672 if (mctrl & TIOCM_OUT1)
1673 mcr |= UART_MCR_OUT1;
1674 if (mctrl & TIOCM_OUT2)
1675 mcr |= UART_MCR_OUT2;
1676 if (mctrl & TIOCM_LOOP)
1677 mcr |= UART_MCR_LOOP;
1679 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1681 serial_port_out(port, UART_MCR, mcr);
1683 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1685 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1687 if (port->set_mctrl)
1688 port->set_mctrl(port, mctrl);
1690 serial8250_do_set_mctrl(port, mctrl);
1693 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1695 struct uart_8250_port *up = up_to_u8250p(port);
1696 unsigned long flags;
1698 serial8250_rpm_get(up);
1699 spin_lock_irqsave(&port->lock, flags);
1700 if (break_state == -1)
1701 up->lcr |= UART_LCR_SBC;
1703 up->lcr &= ~UART_LCR_SBC;
1704 serial_port_out(port, UART_LCR, up->lcr);
1705 spin_unlock_irqrestore(&port->lock, flags);
1706 serial8250_rpm_put(up);
1710 * Wait for transmitter & holding register to empty
1712 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1714 unsigned int status, tmout = 10000;
1716 /* Wait up to 10ms for the character(s) to be sent. */
1718 status = serial_in(up, UART_LSR);
1720 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1722 if ((status & bits) == bits)
1729 /* Wait up to 1s for flow control if necessary */
1730 if (up->port.flags & UPF_CONS_FLOW) {
1732 for (tmout = 1000000; tmout; tmout--) {
1733 unsigned int msr = serial_in(up, UART_MSR);
1734 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1735 if (msr & UART_MSR_CTS)
1738 touch_nmi_watchdog();
1743 #ifdef CONFIG_CONSOLE_POLL
1745 * Console polling routines for writing and reading from the uart while
1746 * in an interrupt or debug context.
1749 static int serial8250_get_poll_char(struct uart_port *port)
1751 struct uart_8250_port *up = up_to_u8250p(port);
1755 serial8250_rpm_get(up);
1757 lsr = serial_port_in(port, UART_LSR);
1759 if (!(lsr & UART_LSR_DR)) {
1760 status = NO_POLL_CHAR;
1764 status = serial_port_in(port, UART_RX);
1766 serial8250_rpm_put(up);
1771 static void serial8250_put_poll_char(struct uart_port *port,
1775 struct uart_8250_port *up = up_to_u8250p(port);
1777 serial8250_rpm_get(up);
1779 * First save the IER then disable the interrupts
1781 ier = serial_port_in(port, UART_IER);
1782 if (up->capabilities & UART_CAP_UUE)
1783 serial_port_out(port, UART_IER, UART_IER_UUE);
1785 serial_port_out(port, UART_IER, 0);
1787 wait_for_xmitr(up, BOTH_EMPTY);
1789 * Send the character out.
1791 serial_port_out(port, UART_TX, c);
1794 * Finally, wait for transmitter to become empty
1795 * and restore the IER
1797 wait_for_xmitr(up, BOTH_EMPTY);
1798 serial_port_out(port, UART_IER, ier);
1799 serial8250_rpm_put(up);
1802 #endif /* CONFIG_CONSOLE_POLL */
1804 int serial8250_do_startup(struct uart_port *port)
1806 struct uart_8250_port *up = up_to_u8250p(port);
1807 unsigned long flags;
1808 unsigned char lsr, iir;
1811 if (!port->fifosize)
1812 port->fifosize = uart_config[port->type].fifo_size;
1814 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1815 if (!up->capabilities)
1816 up->capabilities = uart_config[port->type].flags;
1819 if (port->iotype != up->cur_iotype)
1820 set_io_from_upio(port);
1822 serial8250_rpm_get(up);
1823 if (port->type == PORT_16C950) {
1824 /* Wake up and initialize UART */
1826 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1827 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1828 serial_port_out(port, UART_IER, 0);
1829 serial_port_out(port, UART_LCR, 0);
1830 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1831 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1832 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1833 serial_port_out(port, UART_LCR, 0);
1836 #ifdef CONFIG_SERIAL_8250_RSA
1838 * If this is an RSA port, see if we can kick it up to the
1839 * higher speed clock.
1844 if (port->type == PORT_XR17V35X) {
1846 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
1847 * MCR [7:5] and MSR [7:0]
1849 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
1852 * Make sure all interrups are masked until initialization is
1853 * complete and the FIFOs are cleared
1855 serial_port_out(port, UART_IER, 0);
1859 * Clear the FIFO buffers and disable them.
1860 * (they will be reenabled in set_termios())
1862 serial8250_clear_fifos(up);
1865 * Clear the interrupt registers.
1867 serial_port_in(port, UART_LSR);
1868 serial_port_in(port, UART_RX);
1869 serial_port_in(port, UART_IIR);
1870 serial_port_in(port, UART_MSR);
1873 * At this point, there's no way the LSR could still be 0xff;
1874 * if it is, then bail out, because there's likely no UART
1877 if (!(port->flags & UPF_BUGGY_UART) &&
1878 (serial_port_in(port, UART_LSR) == 0xff)) {
1879 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1880 serial_index(port));
1886 * For a XR16C850, we need to set the trigger levels
1888 if (port->type == PORT_16850) {
1891 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1893 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1894 serial_port_out(port, UART_FCTR,
1895 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1896 serial_port_out(port, UART_TRG, UART_TRG_96);
1897 serial_port_out(port, UART_FCTR,
1898 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1899 serial_port_out(port, UART_TRG, UART_TRG_96);
1901 serial_port_out(port, UART_LCR, 0);
1907 * Test for UARTs that do not reassert THRE when the
1908 * transmitter is idle and the interrupt has already
1909 * been cleared. Real 16550s should always reassert
1910 * this interrupt whenever the transmitter is idle and
1911 * the interrupt is enabled. Delays are necessary to
1912 * allow register changes to become visible.
1914 spin_lock_irqsave(&port->lock, flags);
1915 if (up->port.irqflags & IRQF_SHARED)
1916 disable_irq_nosync(port->irq);
1918 wait_for_xmitr(up, UART_LSR_THRE);
1919 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1920 udelay(1); /* allow THRE to set */
1921 iir1 = serial_port_in(port, UART_IIR);
1922 serial_port_out(port, UART_IER, 0);
1923 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1924 udelay(1); /* allow a working UART time to re-assert THRE */
1925 iir = serial_port_in(port, UART_IIR);
1926 serial_port_out(port, UART_IER, 0);
1928 if (port->irqflags & IRQF_SHARED)
1929 enable_irq(port->irq);
1930 spin_unlock_irqrestore(&port->lock, flags);
1933 * If the interrupt is not reasserted, or we otherwise
1934 * don't trust the iir, setup a timer to kick the UART
1935 * on a regular basis.
1937 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
1938 up->port.flags & UPF_BUG_THRE) {
1939 up->bugs |= UART_BUG_THRE;
1943 retval = up->ops->setup_irq(up);
1948 * Now, initialize the UART
1950 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1952 spin_lock_irqsave(&port->lock, flags);
1953 if (up->port.flags & UPF_FOURPORT) {
1955 up->port.mctrl |= TIOCM_OUT1;
1958 * Most PC uarts need OUT2 raised to enable interrupts.
1961 up->port.mctrl |= TIOCM_OUT2;
1963 serial8250_set_mctrl(port, port->mctrl);
1965 /* Serial over Lan (SoL) hack:
1966 Intel 8257x Gigabit ethernet chips have a
1967 16550 emulation, to be used for Serial Over Lan.
1968 Those chips take a longer time than a normal
1969 serial device to signalize that a transmission
1970 data was queued. Due to that, the above test generally
1971 fails. One solution would be to delay the reading of
1972 iir. However, this is not reliable, since the timeout
1973 is variable. So, let's just don't test if we receive
1974 TX irq. This way, we'll never enable UART_BUG_TXEN.
1976 if (up->port.flags & UPF_NO_TXEN_TEST)
1977 goto dont_test_tx_en;
1980 * Do a quick test to see if we receive an
1981 * interrupt when we enable the TX irq.
1983 serial_port_out(port, UART_IER, UART_IER_THRI);
1984 lsr = serial_port_in(port, UART_LSR);
1985 iir = serial_port_in(port, UART_IIR);
1986 serial_port_out(port, UART_IER, 0);
1988 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1989 if (!(up->bugs & UART_BUG_TXEN)) {
1990 up->bugs |= UART_BUG_TXEN;
1991 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1992 serial_index(port));
1995 up->bugs &= ~UART_BUG_TXEN;
1999 spin_unlock_irqrestore(&port->lock, flags);
2002 * Clear the interrupt registers again for luck, and clear the
2003 * saved flags to avoid getting false values from polling
2004 * routines or the previous session.
2006 serial_port_in(port, UART_LSR);
2007 serial_port_in(port, UART_RX);
2008 serial_port_in(port, UART_IIR);
2009 serial_port_in(port, UART_MSR);
2010 up->lsr_saved_flags = 0;
2011 up->msr_saved_flags = 0;
2014 * Request DMA channels for both RX and TX.
2017 retval = serial8250_request_dma(up);
2019 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2020 serial_index(port));
2026 * Set the IER shadow for rx interrupts but defer actual interrupt
2027 * enable until after the FIFOs are enabled; otherwise, an already-
2028 * active sender can swamp the interrupt handler with "too much work".
2030 up->ier = UART_IER_RLSI | UART_IER_RDI;
2032 if (port->flags & UPF_FOURPORT) {
2035 * Enable interrupts on the AST Fourport board
2037 icp = (port->iobase & 0xfe0) | 0x01f;
2043 serial8250_rpm_put(up);
2046 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2048 static int serial8250_startup(struct uart_port *port)
2051 return port->startup(port);
2052 return serial8250_do_startup(port);
2055 void serial8250_do_shutdown(struct uart_port *port)
2057 struct uart_8250_port *up = up_to_u8250p(port);
2058 unsigned long flags;
2060 serial8250_rpm_get(up);
2062 * Disable interrupts from this port
2065 serial_port_out(port, UART_IER, 0);
2068 serial8250_release_dma(up);
2070 spin_lock_irqsave(&port->lock, flags);
2071 if (port->flags & UPF_FOURPORT) {
2072 /* reset interrupts on the AST Fourport board */
2073 inb((port->iobase & 0xfe0) | 0x1f);
2074 port->mctrl |= TIOCM_OUT1;
2076 port->mctrl &= ~TIOCM_OUT2;
2078 serial8250_set_mctrl(port, port->mctrl);
2079 spin_unlock_irqrestore(&port->lock, flags);
2082 * Disable break condition and FIFOs
2084 serial_port_out(port, UART_LCR,
2085 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2086 serial8250_clear_fifos(up);
2088 #ifdef CONFIG_SERIAL_8250_RSA
2090 * Reset the RSA board back to 115kbps compat mode.
2096 * Read data port to reset things, and then unlink from
2099 serial_port_in(port, UART_RX);
2100 serial8250_rpm_put(up);
2102 up->ops->release_irq(up);
2104 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2106 static void serial8250_shutdown(struct uart_port *port)
2109 port->shutdown(port);
2111 serial8250_do_shutdown(port);
2115 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2116 * Calculate divisor with extra 4-bit fractional portion
2118 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2122 struct uart_port *port = &up->port;
2123 unsigned int quot_16;
2125 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2126 *frac = quot_16 & 0x0f;
2128 return quot_16 >> 4;
2131 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2135 struct uart_port *port = &up->port;
2139 * Handle magic divisors for baud rates above baud_base on
2140 * SMSC SuperIO chips.
2143 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2144 baud == (port->uartclk/4))
2146 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2147 baud == (port->uartclk/8))
2149 else if (up->port.type == PORT_XR17V35X)
2150 quot = xr17v35x_get_divisor(up, baud, frac);
2152 quot = uart_get_divisor(port, baud);
2155 * Oxford Semi 952 rev B workaround
2157 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2163 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2168 switch (c_cflag & CSIZE) {
2170 cval = UART_LCR_WLEN5;
2173 cval = UART_LCR_WLEN6;
2176 cval = UART_LCR_WLEN7;
2180 cval = UART_LCR_WLEN8;
2184 if (c_cflag & CSTOPB)
2185 cval |= UART_LCR_STOP;
2186 if (c_cflag & PARENB) {
2187 cval |= UART_LCR_PARITY;
2188 if (up->bugs & UART_BUG_PARITY)
2189 up->fifo_bug = true;
2191 if (!(c_cflag & PARODD))
2192 cval |= UART_LCR_EPAR;
2194 if (c_cflag & CMSPAR)
2195 cval |= UART_LCR_SPAR;
2201 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2202 unsigned int quot, unsigned int quot_frac)
2204 struct uart_8250_port *up = up_to_u8250p(port);
2206 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2207 if (is_omap1510_8250(up)) {
2208 if (baud == 115200) {
2210 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2212 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2216 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2217 * otherwise just set DLAB
2219 if (up->capabilities & UART_NATSEMI)
2220 serial_port_out(port, UART_LCR, 0xe0);
2222 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2224 serial_dl_write(up, quot);
2226 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2227 if (up->port.type == PORT_XR17V35X)
2228 serial_port_out(port, 0x2, quot_frac);
2232 serial8250_get_baud_rate(struct uart_port *port, struct ktermios *termios,
2233 struct ktermios *old)
2235 unsigned int tolerance = port->uartclk / 100;
2238 * Ask the core to calculate the divisor for us.
2239 * Allow 1% tolerance at the upper limit so uart clks marginally
2240 * slower than nominal still match standard baud rates without
2241 * causing transmission errors.
2243 return uart_get_baud_rate(port, termios, old,
2244 port->uartclk / 16 / 0xffff,
2245 (port->uartclk + tolerance) / 16);
2249 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2250 struct ktermios *old)
2252 struct uart_8250_port *up = up_to_u8250p(port);
2254 unsigned long flags;
2255 unsigned int baud, quot, frac = 0;
2257 cval = serial8250_compute_lcr(up, termios->c_cflag);
2259 baud = serial8250_get_baud_rate(port, termios, old);
2260 quot = serial8250_get_divisor(up, baud, &frac);
2263 * Ok, we're now changing the port state. Do it with
2264 * interrupts disabled.
2266 serial8250_rpm_get(up);
2267 spin_lock_irqsave(&port->lock, flags);
2269 up->lcr = cval; /* Save computed LCR */
2271 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2272 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2273 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2274 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2275 up->fcr |= UART_FCR_TRIGGER_1;
2280 * MCR-based auto flow control. When AFE is enabled, RTS will be
2281 * deasserted when the receive FIFO contains more characters than
2282 * the trigger, or the MCR RTS bit is cleared. In the case where
2283 * the remote UART is not using CTS auto flow control, we must
2284 * have sufficient FIFO entries for the latency of the remote
2285 * UART to respond. IOW, at least 32 bytes of FIFO.
2287 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2288 up->mcr &= ~UART_MCR_AFE;
2289 if (termios->c_cflag & CRTSCTS)
2290 up->mcr |= UART_MCR_AFE;
2294 * Update the per-port timeout.
2296 uart_update_timeout(port, termios->c_cflag, baud);
2298 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2299 if (termios->c_iflag & INPCK)
2300 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2301 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2302 port->read_status_mask |= UART_LSR_BI;
2305 * Characteres to ignore
2307 port->ignore_status_mask = 0;
2308 if (termios->c_iflag & IGNPAR)
2309 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2310 if (termios->c_iflag & IGNBRK) {
2311 port->ignore_status_mask |= UART_LSR_BI;
2313 * If we're ignoring parity and break indicators,
2314 * ignore overruns too (for real raw support).
2316 if (termios->c_iflag & IGNPAR)
2317 port->ignore_status_mask |= UART_LSR_OE;
2321 * ignore all characters if CREAD is not set
2323 if ((termios->c_cflag & CREAD) == 0)
2324 port->ignore_status_mask |= UART_LSR_DR;
2327 * CTS flow control flag and modem status interrupts
2329 up->ier &= ~UART_IER_MSI;
2330 if (!(up->bugs & UART_BUG_NOMSR) &&
2331 UART_ENABLE_MS(&up->port, termios->c_cflag))
2332 up->ier |= UART_IER_MSI;
2333 if (up->capabilities & UART_CAP_UUE)
2334 up->ier |= UART_IER_UUE;
2335 if (up->capabilities & UART_CAP_RTOIE)
2336 up->ier |= UART_IER_RTOIE;
2338 serial_port_out(port, UART_IER, up->ier);
2340 if (up->capabilities & UART_CAP_EFR) {
2341 unsigned char efr = 0;
2343 * TI16C752/Startech hardware flow control. FIXME:
2344 * - TI16C752 requires control thresholds to be set.
2345 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2347 if (termios->c_cflag & CRTSCTS)
2348 efr |= UART_EFR_CTS;
2350 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2351 if (port->flags & UPF_EXAR_EFR)
2352 serial_port_out(port, UART_XR_EFR, efr);
2354 serial_port_out(port, UART_EFR, efr);
2357 serial8250_set_divisor(port, baud, quot, frac);
2360 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2361 * is written without DLAB set, this mode will be disabled.
2363 if (port->type == PORT_16750)
2364 serial_port_out(port, UART_FCR, up->fcr);
2366 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2367 if (port->type != PORT_16750) {
2368 /* emulated UARTs (Lucent Venus 167x) need two steps */
2369 if (up->fcr & UART_FCR_ENABLE_FIFO)
2370 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2371 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2373 serial8250_set_mctrl(port, port->mctrl);
2374 spin_unlock_irqrestore(&port->lock, flags);
2375 serial8250_rpm_put(up);
2377 /* Don't rewrite B0 */
2378 if (tty_termios_baud_rate(termios))
2379 tty_termios_encode_baud_rate(termios, baud, baud);
2381 EXPORT_SYMBOL(serial8250_do_set_termios);
2384 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2385 struct ktermios *old)
2387 if (port->set_termios)
2388 port->set_termios(port, termios, old);
2390 serial8250_do_set_termios(port, termios, old);
2394 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2396 if (termios->c_line == N_PPS) {
2397 port->flags |= UPF_HARDPPS_CD;
2398 spin_lock_irq(&port->lock);
2399 serial8250_enable_ms(port);
2400 spin_unlock_irq(&port->lock);
2402 port->flags &= ~UPF_HARDPPS_CD;
2403 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2404 spin_lock_irq(&port->lock);
2405 serial8250_disable_ms(port);
2406 spin_unlock_irq(&port->lock);
2412 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2413 unsigned int oldstate)
2415 struct uart_8250_port *p = up_to_u8250p(port);
2417 serial8250_set_sleep(p, state != 0);
2419 EXPORT_SYMBOL(serial8250_do_pm);
2422 serial8250_pm(struct uart_port *port, unsigned int state,
2423 unsigned int oldstate)
2426 port->pm(port, state, oldstate);
2428 serial8250_do_pm(port, state, oldstate);
2431 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2433 if (pt->port.mapsize)
2434 return pt->port.mapsize;
2435 if (pt->port.iotype == UPIO_AU) {
2436 if (pt->port.type == PORT_RT2880)
2440 if (is_omap1_8250(pt))
2441 return 0x16 << pt->port.regshift;
2443 return 8 << pt->port.regshift;
2447 * Resource handling.
2449 static int serial8250_request_std_resource(struct uart_8250_port *up)
2451 unsigned int size = serial8250_port_size(up);
2452 struct uart_port *port = &up->port;
2455 switch (port->iotype) {
2464 if (!request_mem_region(port->mapbase, size, "serial")) {
2469 if (port->flags & UPF_IOREMAP) {
2470 port->membase = ioremap_nocache(port->mapbase, size);
2471 if (!port->membase) {
2472 release_mem_region(port->mapbase, size);
2480 if (!request_region(port->iobase, size, "serial"))
2487 static void serial8250_release_std_resource(struct uart_8250_port *up)
2489 unsigned int size = serial8250_port_size(up);
2490 struct uart_port *port = &up->port;
2492 switch (port->iotype) {
2501 if (port->flags & UPF_IOREMAP) {
2502 iounmap(port->membase);
2503 port->membase = NULL;
2506 release_mem_region(port->mapbase, size);
2511 release_region(port->iobase, size);
2516 static void serial8250_release_port(struct uart_port *port)
2518 struct uart_8250_port *up = up_to_u8250p(port);
2520 serial8250_release_std_resource(up);
2523 static int serial8250_request_port(struct uart_port *port)
2525 struct uart_8250_port *up = up_to_u8250p(port);
2527 return serial8250_request_std_resource(up);
2530 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2532 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2533 unsigned char bytes;
2535 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2537 return bytes ? bytes : -EOPNOTSUPP;
2540 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2542 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2545 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2548 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2549 if (bytes < conf_type->rxtrig_bytes[i])
2550 /* Use the nearest lower value */
2551 return (--i) << UART_FCR_R_TRIG_SHIFT;
2554 return UART_FCR_R_TRIG_11;
2557 static int do_get_rxtrig(struct tty_port *port)
2559 struct uart_state *state = container_of(port, struct uart_state, port);
2560 struct uart_port *uport = state->uart_port;
2561 struct uart_8250_port *up =
2562 container_of(uport, struct uart_8250_port, port);
2564 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2567 return fcr_get_rxtrig_bytes(up);
2570 static int do_serial8250_get_rxtrig(struct tty_port *port)
2574 mutex_lock(&port->mutex);
2575 rxtrig_bytes = do_get_rxtrig(port);
2576 mutex_unlock(&port->mutex);
2578 return rxtrig_bytes;
2581 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2582 struct device_attribute *attr, char *buf)
2584 struct tty_port *port = dev_get_drvdata(dev);
2587 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2588 if (rxtrig_bytes < 0)
2589 return rxtrig_bytes;
2591 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2594 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2596 struct uart_state *state = container_of(port, struct uart_state, port);
2597 struct uart_port *uport = state->uart_port;
2598 struct uart_8250_port *up =
2599 container_of(uport, struct uart_8250_port, port);
2602 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2606 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2610 serial8250_clear_fifos(up);
2611 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2612 up->fcr |= (unsigned char)rxtrig;
2613 serial_out(up, UART_FCR, up->fcr);
2617 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2621 mutex_lock(&port->mutex);
2622 ret = do_set_rxtrig(port, bytes);
2623 mutex_unlock(&port->mutex);
2628 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2629 struct device_attribute *attr, const char *buf, size_t count)
2631 struct tty_port *port = dev_get_drvdata(dev);
2632 unsigned char bytes;
2638 ret = kstrtou8(buf, 10, &bytes);
2642 ret = do_serial8250_set_rxtrig(port, bytes);
2649 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2650 serial8250_get_attr_rx_trig_bytes,
2651 serial8250_set_attr_rx_trig_bytes);
2653 static struct attribute *serial8250_dev_attrs[] = {
2654 &dev_attr_rx_trig_bytes.attr,
2658 static struct attribute_group serial8250_dev_attr_group = {
2659 .attrs = serial8250_dev_attrs,
2662 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2664 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2666 if (conf_type->rxtrig_bytes[0])
2667 up->port.attr_group = &serial8250_dev_attr_group;
2670 static void serial8250_config_port(struct uart_port *port, int flags)
2672 struct uart_8250_port *up = up_to_u8250p(port);
2676 * Find the region that we can probe for. This in turn
2677 * tells us whether we can probe for the type of port.
2679 ret = serial8250_request_std_resource(up);
2683 if (port->iotype != up->cur_iotype)
2684 set_io_from_upio(port);
2686 if (flags & UART_CONFIG_TYPE)
2689 /* if access method is AU, it is a 16550 with a quirk */
2690 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2691 up->bugs |= UART_BUG_NOMSR;
2693 /* HW bugs may trigger IRQ while IIR == NO_INT */
2694 if (port->type == PORT_TEGRA)
2695 up->bugs |= UART_BUG_NOMSR;
2697 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2700 if (port->type == PORT_UNKNOWN)
2701 serial8250_release_std_resource(up);
2703 /* Fixme: probably not the best place for this */
2704 if ((port->type == PORT_XR17V35X) ||
2705 (port->type == PORT_XR17D15X))
2706 port->handle_irq = exar_handle_irq;
2708 register_dev_spec_attr_grp(up);
2709 up->fcr = uart_config[up->port.type].fcr;
2713 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2715 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2716 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2717 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2718 ser->type == PORT_STARTECH)
2724 serial8250_type(struct uart_port *port)
2726 int type = port->type;
2728 if (type >= ARRAY_SIZE(uart_config))
2730 return uart_config[type].name;
2733 static const struct uart_ops serial8250_pops = {
2734 .tx_empty = serial8250_tx_empty,
2735 .set_mctrl = serial8250_set_mctrl,
2736 .get_mctrl = serial8250_get_mctrl,
2737 .stop_tx = serial8250_stop_tx,
2738 .start_tx = serial8250_start_tx,
2739 .throttle = serial8250_throttle,
2740 .unthrottle = serial8250_unthrottle,
2741 .stop_rx = serial8250_stop_rx,
2742 .enable_ms = serial8250_enable_ms,
2743 .break_ctl = serial8250_break_ctl,
2744 .startup = serial8250_startup,
2745 .shutdown = serial8250_shutdown,
2746 .set_termios = serial8250_set_termios,
2747 .set_ldisc = serial8250_set_ldisc,
2748 .pm = serial8250_pm,
2749 .type = serial8250_type,
2750 .release_port = serial8250_release_port,
2751 .request_port = serial8250_request_port,
2752 .config_port = serial8250_config_port,
2753 .verify_port = serial8250_verify_port,
2754 #ifdef CONFIG_CONSOLE_POLL
2755 .poll_get_char = serial8250_get_poll_char,
2756 .poll_put_char = serial8250_put_poll_char,
2760 void serial8250_init_port(struct uart_8250_port *up)
2762 struct uart_port *port = &up->port;
2764 spin_lock_init(&port->lock);
2765 port->ops = &serial8250_pops;
2767 up->cur_iotype = 0xFF;
2769 EXPORT_SYMBOL_GPL(serial8250_init_port);
2771 void serial8250_set_defaults(struct uart_8250_port *up)
2773 struct uart_port *port = &up->port;
2775 if (up->port.flags & UPF_FIXED_TYPE) {
2776 unsigned int type = up->port.type;
2778 if (!up->port.fifosize)
2779 up->port.fifosize = uart_config[type].fifo_size;
2781 up->tx_loadsz = uart_config[type].tx_loadsz;
2782 if (!up->capabilities)
2783 up->capabilities = uart_config[type].flags;
2786 set_io_from_upio(port);
2788 /* default dma handlers */
2790 if (!up->dma->tx_dma)
2791 up->dma->tx_dma = serial8250_tx_dma;
2792 if (!up->dma->rx_dma)
2793 up->dma->rx_dma = serial8250_rx_dma;
2796 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
2798 #ifdef CONFIG_SERIAL_8250_CONSOLE
2800 static void serial8250_console_putchar(struct uart_port *port, int ch)
2802 struct uart_8250_port *up = up_to_u8250p(port);
2804 wait_for_xmitr(up, UART_LSR_THRE);
2805 serial_port_out(port, UART_TX, ch);
2809 * Restore serial console when h/w power-off detected
2811 static void serial8250_console_restore(struct uart_8250_port *up)
2813 struct uart_port *port = &up->port;
2814 struct ktermios termios;
2815 unsigned int baud, quot, frac = 0;
2817 termios.c_cflag = port->cons->cflag;
2818 if (port->state->port.tty && termios.c_cflag == 0)
2819 termios.c_cflag = port->state->port.tty->termios.c_cflag;
2821 baud = serial8250_get_baud_rate(port, &termios, NULL);
2822 quot = serial8250_get_divisor(up, baud, &frac);
2824 serial8250_set_divisor(port, baud, quot, frac);
2825 serial_port_out(port, UART_LCR, up->lcr);
2826 serial_port_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
2830 * Print a string to the serial port trying not to disturb
2831 * any possible real use of the port...
2833 * The console_lock must be held when we get here.
2835 void serial8250_console_write(struct uart_8250_port *up, const char *s,
2838 struct uart_port *port = &up->port;
2839 unsigned long flags;
2843 touch_nmi_watchdog();
2845 serial8250_rpm_get(up);
2847 if (port->sysrq || oops_in_progress)
2849 else if (in_kdb_printk())
2850 locked = spin_trylock_irqsave(&port->lock, flags);
2852 spin_lock_irqsave(&port->lock, flags);
2855 * First save the IER then disable the interrupts
2857 ier = serial_port_in(port, UART_IER);
2859 if (up->capabilities & UART_CAP_UUE)
2860 serial_port_out(port, UART_IER, UART_IER_UUE);
2862 serial_port_out(port, UART_IER, 0);
2864 /* check scratch reg to see if port powered off during system sleep */
2865 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
2866 serial8250_console_restore(up);
2870 uart_console_write(port, s, count, serial8250_console_putchar);
2873 * Finally, wait for transmitter to become empty
2874 * and restore the IER
2876 wait_for_xmitr(up, BOTH_EMPTY);
2877 serial_port_out(port, UART_IER, ier);
2880 * The receive handling will happen properly because the
2881 * receive ready bit will still be set; it is not cleared
2882 * on read. However, modem control will not, we must
2883 * call it if we have saved something in the saved flags
2884 * while processing with interrupts off.
2886 if (up->msr_saved_flags)
2887 serial8250_modem_status(up);
2890 spin_unlock_irqrestore(&port->lock, flags);
2891 serial8250_rpm_put(up);
2894 static unsigned int probe_baud(struct uart_port *port)
2896 unsigned char lcr, dll, dlm;
2899 lcr = serial_port_in(port, UART_LCR);
2900 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
2901 dll = serial_port_in(port, UART_DLL);
2902 dlm = serial_port_in(port, UART_DLM);
2903 serial_port_out(port, UART_LCR, lcr);
2905 quot = (dlm << 8) | dll;
2906 return (port->uartclk / 16) / quot;
2909 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
2916 if (!port->iobase && !port->membase)
2920 uart_parse_options(options, &baud, &parity, &bits, &flow);
2922 baud = probe_baud(port);
2924 return uart_set_options(port, port->cons, baud, parity, bits, flow);
2927 #endif /* CONFIG_SERIAL_8250_CONSOLE */
2929 MODULE_LICENSE("GPL");