2 * Probe module for 8250/16550-type PCI serial ports.
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24 #include <linux/rational.h>
26 #include <asm/byteorder.h>
29 #include <linux/dmaengine.h>
30 #include <linux/platform_data/dma-dw.h>
35 * init function returns:
36 * > 0 - number of ports
37 * = 0 - use board->num_ports
40 struct pci_serial_quirk {
45 int (*probe)(struct pci_dev *dev);
46 int (*init)(struct pci_dev *dev);
47 int (*setup)(struct serial_private *,
48 const struct pciserial_board *,
49 struct uart_8250_port *, int);
50 void (*exit)(struct pci_dev *dev);
53 #define PCI_NUM_BAR_RESOURCES 6
55 struct serial_private {
58 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
59 struct pci_serial_quirk *quirk;
63 static int pci_default_setup(struct serial_private*,
64 const struct pciserial_board*, struct uart_8250_port *, int);
66 static void moan_device(const char *str, struct pci_dev *dev)
70 "Please send the output of lspci -vv, this\n"
71 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
72 "manufacturer and name of serial board or\n"
73 "modem board to <linux-serial@vger.kernel.org>.\n",
74 pci_name(dev), str, dev->vendor, dev->device,
75 dev->subsystem_vendor, dev->subsystem_device);
79 setup_port(struct serial_private *priv, struct uart_8250_port *port,
80 int bar, int offset, int regshift)
82 struct pci_dev *dev = priv->dev;
84 if (bar >= PCI_NUM_BAR_RESOURCES)
87 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
88 if (!priv->remapped_bar[bar])
89 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
90 if (!priv->remapped_bar[bar])
93 port->port.iotype = UPIO_MEM;
94 port->port.iobase = 0;
95 port->port.mapbase = pci_resource_start(dev, bar) + offset;
96 port->port.membase = priv->remapped_bar[bar] + offset;
97 port->port.regshift = regshift;
99 port->port.iotype = UPIO_PORT;
100 port->port.iobase = pci_resource_start(dev, bar) + offset;
101 port->port.mapbase = 0;
102 port->port.membase = NULL;
103 port->port.regshift = 0;
109 * ADDI-DATA GmbH communication cards <info@addi-data.com>
111 static int addidata_apci7800_setup(struct serial_private *priv,
112 const struct pciserial_board *board,
113 struct uart_8250_port *port, int idx)
115 unsigned int bar = 0, offset = board->first_offset;
116 bar = FL_GET_BASE(board->flags);
119 offset += idx * board->uart_offset;
120 } else if ((idx >= 2) && (idx < 4)) {
122 offset += ((idx - 2) * board->uart_offset);
123 } else if ((idx >= 4) && (idx < 6)) {
125 offset += ((idx - 4) * board->uart_offset);
126 } else if (idx >= 6) {
128 offset += ((idx - 6) * board->uart_offset);
131 return setup_port(priv, port, bar, offset, board->reg_shift);
135 * AFAVLAB uses a different mixture of BARs and offsets
136 * Not that ugly ;) -- HW
139 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
140 struct uart_8250_port *port, int idx)
142 unsigned int bar, offset = board->first_offset;
144 bar = FL_GET_BASE(board->flags);
149 offset += (idx - 4) * board->uart_offset;
152 return setup_port(priv, port, bar, offset, board->reg_shift);
156 * HP's Remote Management Console. The Diva chip came in several
157 * different versions. N-class, L2000 and A500 have two Diva chips, each
158 * with 3 UARTs (the third UART on the second chip is unused). Superdome
159 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
160 * one Diva chip, but it has been expanded to 5 UARTs.
162 static int pci_hp_diva_init(struct pci_dev *dev)
166 switch (dev->subsystem_device) {
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
168 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
169 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
170 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
176 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
180 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
189 * HP's Diva chip puts the 4th/5th serial port further out, and
190 * some serial ports are supposed to be hidden on certain models.
193 pci_hp_diva_setup(struct serial_private *priv,
194 const struct pciserial_board *board,
195 struct uart_8250_port *port, int idx)
197 unsigned int offset = board->first_offset;
198 unsigned int bar = FL_GET_BASE(board->flags);
200 switch (priv->dev->subsystem_device) {
201 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
205 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
215 offset += idx * board->uart_offset;
217 return setup_port(priv, port, bar, offset, board->reg_shift);
221 * Added for EKF Intel i960 serial boards
223 static int pci_inteli960ni_init(struct pci_dev *dev)
227 if (!(dev->subsystem_device & 0x1000))
230 /* is firmware started? */
231 pci_read_config_dword(dev, 0x44, &oldval);
232 if (oldval == 0x00001000L) { /* RESET value */
233 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
240 * Some PCI serial cards using the PLX 9050 PCI interface chip require
241 * that the card interrupt be explicitly enabled or disabled. This
242 * seems to be mainly needed on card using the PLX which also use I/O
245 static int pci_plx9050_init(struct pci_dev *dev)
250 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
251 moan_device("no memory in bar 0", dev);
256 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
257 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
260 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
261 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
263 * As the megawolf cards have the int pins active
264 * high, and have 2 UART chips, both ints must be
265 * enabled on the 9050. Also, the UARTS are set in
266 * 16450 mode by default, so we have to enable the
267 * 16C950 'enhanced' mode so that we can use the
272 * enable/disable interrupts
274 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
277 writel(irq_config, p + 0x4c);
280 * Read the register back to ensure that it took effect.
288 static void pci_plx9050_exit(struct pci_dev *dev)
292 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
298 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
303 * Read the register back to ensure that it took effect.
310 #define NI8420_INT_ENABLE_REG 0x38
311 #define NI8420_INT_ENABLE_BIT 0x2000
313 static void pci_ni8420_exit(struct pci_dev *dev)
316 unsigned int bar = 0;
318 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
319 moan_device("no memory in bar", dev);
323 p = pci_ioremap_bar(dev, bar);
327 /* Disable the CPU Interrupt */
328 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
329 p + NI8420_INT_ENABLE_REG);
335 #define MITE_IOWBSR1 0xc4
336 #define MITE_IOWCR1 0xf4
337 #define MITE_LCIMR1 0x08
338 #define MITE_LCIMR2 0x10
340 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
342 static void pci_ni8430_exit(struct pci_dev *dev)
345 unsigned int bar = 0;
347 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
348 moan_device("no memory in bar", dev);
352 p = pci_ioremap_bar(dev, bar);
356 /* Disable the CPU Interrupt */
357 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
361 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
363 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
364 struct uart_8250_port *port, int idx)
366 unsigned int bar, offset = board->first_offset;
371 /* first four channels map to 0, 0x100, 0x200, 0x300 */
372 offset += idx * board->uart_offset;
373 } else if (idx < 8) {
374 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
375 offset += idx * board->uart_offset + 0xC00;
376 } else /* we have only 8 ports on PMC-OCTALPRO */
379 return setup_port(priv, port, bar, offset, board->reg_shift);
383 * This does initialization for PMC OCTALPRO cards:
384 * maps the device memory, resets the UARTs (needed, bc
385 * if the module is removed and inserted again, the card
386 * is in the sleep mode) and enables global interrupt.
389 /* global control register offset for SBS PMC-OctalPro */
390 #define OCT_REG_CR_OFF 0x500
392 static int sbs_init(struct pci_dev *dev)
396 p = pci_ioremap_bar(dev, 0);
400 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
401 writeb(0x10, p + OCT_REG_CR_OFF);
403 writeb(0x0, p + OCT_REG_CR_OFF);
405 /* Set bit-2 (INTENABLE) of Control Register */
406 writeb(0x4, p + OCT_REG_CR_OFF);
413 * Disables the global interrupt of PMC-OctalPro
416 static void sbs_exit(struct pci_dev *dev)
420 p = pci_ioremap_bar(dev, 0);
421 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
423 writeb(0, p + OCT_REG_CR_OFF);
428 * SIIG serial cards have an PCI interface chip which also controls
429 * the UART clocking frequency. Each UART can be clocked independently
430 * (except cards equipped with 4 UARTs) and initial clocking settings
431 * are stored in the EEPROM chip. It can cause problems because this
432 * version of serial driver doesn't support differently clocked UART's
433 * on single PCI card. To prevent this, initialization functions set
434 * high frequency clocking for all UART's on given card. It is safe (I
435 * hope) because it doesn't touch EEPROM settings to prevent conflicts
436 * with other OSes (like M$ DOS).
438 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
440 * There is two family of SIIG serial cards with different PCI
441 * interface chip and different configuration methods:
442 * - 10x cards have control registers in IO and/or memory space;
443 * - 20x cards have control registers in standard PCI configuration space.
445 * Note: all 10x cards have PCI device ids 0x10..
446 * all 20x cards have PCI device ids 0x20..
448 * There are also Quartet Serial cards which use Oxford Semiconductor
449 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
451 * Note: some SIIG cards are probed by the parport_serial object.
454 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
455 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
457 static int pci_siig10x_init(struct pci_dev *dev)
462 switch (dev->device & 0xfff8) {
463 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
466 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
469 default: /* 1S1P, 4S */
474 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
478 writew(readw(p + 0x28) & data, p + 0x28);
484 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
485 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
487 static int pci_siig20x_init(struct pci_dev *dev)
491 /* Change clock frequency for the first UART. */
492 pci_read_config_byte(dev, 0x6f, &data);
493 pci_write_config_byte(dev, 0x6f, data & 0xef);
495 /* If this card has 2 UART, we have to do the same with second UART. */
496 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
497 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
498 pci_read_config_byte(dev, 0x73, &data);
499 pci_write_config_byte(dev, 0x73, data & 0xef);
504 static int pci_siig_init(struct pci_dev *dev)
506 unsigned int type = dev->device & 0xff00;
509 return pci_siig10x_init(dev);
510 else if (type == 0x2000)
511 return pci_siig20x_init(dev);
513 moan_device("Unknown SIIG card", dev);
517 static int pci_siig_setup(struct serial_private *priv,
518 const struct pciserial_board *board,
519 struct uart_8250_port *port, int idx)
521 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
525 offset = (idx - 4) * 8;
528 return setup_port(priv, port, bar, offset, 0);
532 * Timedia has an explosion of boards, and to avoid the PCI table from
533 * growing *huge*, we use this function to collapse some 70 entries
534 * in the PCI table into one, for sanity's and compactness's sake.
536 static const unsigned short timedia_single_port[] = {
537 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
540 static const unsigned short timedia_dual_port[] = {
541 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
542 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
543 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
544 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
548 static const unsigned short timedia_quad_port[] = {
549 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
550 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
551 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
555 static const unsigned short timedia_eight_port[] = {
556 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
557 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
560 static const struct timedia_struct {
562 const unsigned short *ids;
564 { 1, timedia_single_port },
565 { 2, timedia_dual_port },
566 { 4, timedia_quad_port },
567 { 8, timedia_eight_port }
571 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
572 * listing them individually, this driver merely grabs them all with
573 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
574 * and should be left free to be claimed by parport_serial instead.
576 static int pci_timedia_probe(struct pci_dev *dev)
579 * Check the third digit of the subdevice ID
580 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
582 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
584 "ignoring Timedia subdevice %04x for parport_serial\n",
585 dev->subsystem_device);
592 static int pci_timedia_init(struct pci_dev *dev)
594 const unsigned short *ids;
597 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
598 ids = timedia_data[i].ids;
599 for (j = 0; ids[j]; j++)
600 if (dev->subsystem_device == ids[j])
601 return timedia_data[i].num;
607 * Timedia/SUNIX uses a mixture of BARs and offsets
608 * Ugh, this is ugly as all hell --- TYT
611 pci_timedia_setup(struct serial_private *priv,
612 const struct pciserial_board *board,
613 struct uart_8250_port *port, int idx)
615 unsigned int bar = 0, offset = board->first_offset;
622 offset = board->uart_offset;
629 offset = board->uart_offset;
638 return setup_port(priv, port, bar, offset, board->reg_shift);
642 * Some Titan cards are also a little weird
645 titan_400l_800l_setup(struct serial_private *priv,
646 const struct pciserial_board *board,
647 struct uart_8250_port *port, int idx)
649 unsigned int bar, offset = board->first_offset;
660 offset = (idx - 2) * board->uart_offset;
663 return setup_port(priv, port, bar, offset, board->reg_shift);
666 static int pci_xircom_init(struct pci_dev *dev)
672 static int pci_ni8420_init(struct pci_dev *dev)
675 unsigned int bar = 0;
677 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
678 moan_device("no memory in bar", dev);
682 p = pci_ioremap_bar(dev, bar);
686 /* Enable CPU Interrupt */
687 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
688 p + NI8420_INT_ENABLE_REG);
694 #define MITE_IOWBSR1_WSIZE 0xa
695 #define MITE_IOWBSR1_WIN_OFFSET 0x800
696 #define MITE_IOWBSR1_WENAB (1 << 7)
697 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
698 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
699 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
701 static int pci_ni8430_init(struct pci_dev *dev)
704 struct pci_bus_region region;
706 unsigned int bar = 0;
708 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
709 moan_device("no memory in bar", dev);
713 p = pci_ioremap_bar(dev, bar);
718 * Set device window address and size in BAR0, while acknowledging that
719 * the resource structure may contain a translated address that differs
720 * from the address the device responds to.
722 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
723 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
724 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
725 writel(device_window, p + MITE_IOWBSR1);
727 /* Set window access to go to RAMSEL IO address space */
728 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
731 /* Enable IO Bus Interrupt 0 */
732 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
734 /* Enable CPU Interrupt */
735 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
741 /* UART Port Control Register */
742 #define NI8430_PORTCON 0x0f
743 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
746 pci_ni8430_setup(struct serial_private *priv,
747 const struct pciserial_board *board,
748 struct uart_8250_port *port, int idx)
750 struct pci_dev *dev = priv->dev;
752 unsigned int bar, offset = board->first_offset;
754 if (idx >= board->num_ports)
757 bar = FL_GET_BASE(board->flags);
758 offset += idx * board->uart_offset;
760 p = pci_ioremap_bar(dev, bar);
764 /* enable the transceiver */
765 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
766 p + offset + NI8430_PORTCON);
770 return setup_port(priv, port, bar, offset, board->reg_shift);
773 static int pci_netmos_9900_setup(struct serial_private *priv,
774 const struct pciserial_board *board,
775 struct uart_8250_port *port, int idx)
779 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
780 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
781 /* netmos apparently orders BARs by datasheet layout, so serial
782 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
786 return setup_port(priv, port, bar, 0, board->reg_shift);
788 return pci_default_setup(priv, board, port, idx);
792 /* the 99xx series comes with a range of device IDs and a variety
795 * 9900 has varying capabilities and can cascade to sub-controllers
796 * (cascading should be purely internal)
797 * 9904 is hardwired with 4 serial ports
798 * 9912 and 9922 are hardwired with 2 serial ports
800 static int pci_netmos_9900_numports(struct pci_dev *dev)
802 unsigned int c = dev->class;
804 unsigned short sub_serports;
810 } else if ((pi == 0) &&
811 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
812 /* two possibilities: 0x30ps encodes number of parallel and
813 * serial ports, or 0x1000 indicates *something*. This is not
814 * immediately obvious, since the 2s1p+4s configuration seems
815 * to offer all functionality on functions 0..2, while still
816 * advertising the same function 3 as the 4s+2s1p config.
818 sub_serports = dev->subsystem_device & 0xf;
819 if (sub_serports > 0) {
822 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
827 moan_device("unknown NetMos/Mostech program interface", dev);
831 static int pci_netmos_init(struct pci_dev *dev)
833 /* subdevice 0x00PS means <P> parallel, <S> serial */
834 unsigned int num_serial = dev->subsystem_device & 0xf;
836 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
837 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
840 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
841 dev->subsystem_device == 0x0299)
844 switch (dev->device) { /* FALLTHROUGH on all */
845 case PCI_DEVICE_ID_NETMOS_9904:
846 case PCI_DEVICE_ID_NETMOS_9912:
847 case PCI_DEVICE_ID_NETMOS_9922:
848 case PCI_DEVICE_ID_NETMOS_9900:
849 num_serial = pci_netmos_9900_numports(dev);
853 if (num_serial == 0 ) {
854 moan_device("unknown NetMos/Mostech device", dev);
865 * These chips are available with optionally one parallel port and up to
866 * two serial ports. Unfortunately they all have the same product id.
868 * Basic configuration is done over a region of 32 I/O ports. The base
869 * ioport is called INTA or INTC, depending on docs/other drivers.
871 * The region of the 32 I/O ports is configured in POSIO0R...
875 #define ITE_887x_MISCR 0x9c
876 #define ITE_887x_INTCBAR 0x78
877 #define ITE_887x_UARTBAR 0x7c
878 #define ITE_887x_PS0BAR 0x10
879 #define ITE_887x_POSIO0 0x60
882 #define ITE_887x_IOSIZE 32
883 /* I/O space size (bits 26-24; 8 bytes = 011b) */
884 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
885 /* I/O space size (bits 26-24; 32 bytes = 101b) */
886 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
887 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
888 #define ITE_887x_POSIO_SPEED (3 << 29)
889 /* enable IO_Space bit */
890 #define ITE_887x_POSIO_ENABLE (1 << 31)
892 static int pci_ite887x_init(struct pci_dev *dev)
894 /* inta_addr are the configuration addresses of the ITE */
895 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
898 struct resource *iobase = NULL;
899 u32 miscr, uartbar, ioport;
901 /* search for the base-ioport */
903 while (inta_addr[i] && iobase == NULL) {
904 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
906 if (iobase != NULL) {
907 /* write POSIO0R - speed | size | ioport */
908 pci_write_config_dword(dev, ITE_887x_POSIO0,
909 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
910 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
911 /* write INTCBAR - ioport */
912 pci_write_config_dword(dev, ITE_887x_INTCBAR,
914 ret = inb(inta_addr[i]);
916 /* ioport connected */
919 release_region(iobase->start, ITE_887x_IOSIZE);
926 dev_err(&dev->dev, "ite887x: could not find iobase\n");
930 /* start of undocumented type checking (see parport_pc.c) */
931 type = inb(iobase->start + 0x18) & 0x0f;
934 case 0x2: /* ITE8871 (1P) */
935 case 0xa: /* ITE8875 (1P) */
938 case 0xe: /* ITE8872 (2S1P) */
941 case 0x6: /* ITE8873 (1S) */
944 case 0x8: /* ITE8874 (2S) */
948 moan_device("Unknown ITE887x", dev);
952 /* configure all serial ports */
953 for (i = 0; i < ret; i++) {
954 /* read the I/O port from the device */
955 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
957 ioport &= 0x0000FF00; /* the actual base address */
958 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
959 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
960 ITE_887x_POSIO_IOSIZE_8 | ioport);
962 /* write the ioport to the UARTBAR */
963 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
964 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
965 uartbar |= (ioport << (16 * i)); /* set the ioport */
966 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
968 /* get current config */
969 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
970 /* disable interrupts (UARTx_Routing[3:0]) */
971 miscr &= ~(0xf << (12 - 4 * i));
972 /* activate the UART (UARTx_En) */
973 miscr |= 1 << (23 - i);
974 /* write new config with activated UART */
975 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
979 /* the device has no UARTs if we get here */
980 release_region(iobase->start, ITE_887x_IOSIZE);
986 static void pci_ite887x_exit(struct pci_dev *dev)
989 /* the ioport is bit 0-15 in POSIO0R */
990 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
992 release_region(ioport, ITE_887x_IOSIZE);
996 * EndRun Technologies.
997 * Determine the number of ports available on the device.
999 #define PCI_VENDOR_ID_ENDRUN 0x7401
1000 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1002 static int pci_endrun_init(struct pci_dev *dev)
1005 unsigned long deviceID;
1006 unsigned int number_uarts = 0;
1008 /* EndRun device is all 0xexxx */
1009 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1010 (dev->device & 0xf000) != 0xe000)
1013 p = pci_iomap(dev, 0, 5);
1017 deviceID = ioread32(p);
1019 if (deviceID == 0x07000200) {
1020 number_uarts = ioread8(p + 4);
1022 "%d ports detected on EndRun PCI Express device\n",
1025 pci_iounmap(dev, p);
1026 return number_uarts;
1030 * Oxford Semiconductor Inc.
1031 * Check that device is part of the Tornado range of devices, then determine
1032 * the number of ports available on the device.
1034 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1037 unsigned long deviceID;
1038 unsigned int number_uarts = 0;
1040 /* OxSemi Tornado devices are all 0xCxxx */
1041 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1042 (dev->device & 0xF000) != 0xC000)
1045 p = pci_iomap(dev, 0, 5);
1049 deviceID = ioread32(p);
1050 /* Tornado device */
1051 if (deviceID == 0x07000200) {
1052 number_uarts = ioread8(p + 4);
1054 "%d ports detected on Oxford PCI Express device\n",
1057 pci_iounmap(dev, p);
1058 return number_uarts;
1061 static int pci_asix_setup(struct serial_private *priv,
1062 const struct pciserial_board *board,
1063 struct uart_8250_port *port, int idx)
1065 port->bugs |= UART_BUG_PARITY;
1066 return pci_default_setup(priv, board, port, idx);
1069 /* Quatech devices have their own extra interface features */
1071 struct quatech_feature {
1076 #define QPCR_TEST_FOR1 0x3F
1077 #define QPCR_TEST_GET1 0x00
1078 #define QPCR_TEST_FOR2 0x40
1079 #define QPCR_TEST_GET2 0x40
1080 #define QPCR_TEST_FOR3 0x80
1081 #define QPCR_TEST_GET3 0x40
1082 #define QPCR_TEST_FOR4 0xC0
1083 #define QPCR_TEST_GET4 0x80
1085 #define QOPR_CLOCK_X1 0x0000
1086 #define QOPR_CLOCK_X2 0x0001
1087 #define QOPR_CLOCK_X4 0x0002
1088 #define QOPR_CLOCK_X8 0x0003
1089 #define QOPR_CLOCK_RATE_MASK 0x0003
1092 static struct quatech_feature quatech_cards[] = {
1093 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1095 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1096 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1097 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1098 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1099 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1100 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1101 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1102 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1103 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1104 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1105 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1106 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1107 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1108 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1109 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1110 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1111 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1115 static int pci_quatech_amcc(u16 devid)
1117 struct quatech_feature *qf = &quatech_cards[0];
1119 if (qf->devid == devid)
1123 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1127 static int pci_quatech_rqopr(struct uart_8250_port *port)
1129 unsigned long base = port->port.iobase;
1132 LCR = inb(base + UART_LCR);
1133 outb(0xBF, base + UART_LCR);
1134 val = inb(base + UART_SCR);
1135 outb(LCR, base + UART_LCR);
1139 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1141 unsigned long base = port->port.iobase;
1144 LCR = inb(base + UART_LCR);
1145 outb(0xBF, base + UART_LCR);
1146 val = inb(base + UART_SCR);
1147 outb(qopr, base + UART_SCR);
1148 outb(LCR, base + UART_LCR);
1151 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1153 unsigned long base = port->port.iobase;
1156 LCR = inb(base + UART_LCR);
1157 outb(0xBF, base + UART_LCR);
1158 val = inb(base + UART_SCR);
1159 outb(val | 0x10, base + UART_SCR);
1160 qmcr = inb(base + UART_MCR);
1161 outb(val, base + UART_SCR);
1162 outb(LCR, base + UART_LCR);
1167 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1169 unsigned long base = port->port.iobase;
1172 LCR = inb(base + UART_LCR);
1173 outb(0xBF, base + UART_LCR);
1174 val = inb(base + UART_SCR);
1175 outb(val | 0x10, base + UART_SCR);
1176 outb(qmcr, base + UART_MCR);
1177 outb(val, base + UART_SCR);
1178 outb(LCR, base + UART_LCR);
1181 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1183 unsigned long base = port->port.iobase;
1186 LCR = inb(base + UART_LCR);
1187 outb(0xBF, base + UART_LCR);
1188 val = inb(base + UART_SCR);
1190 outb(0x80, UART_LCR);
1191 if (!(inb(UART_SCR) & 0x20)) {
1192 outb(LCR, base + UART_LCR);
1199 static int pci_quatech_test(struct uart_8250_port *port)
1202 u8 qopr = pci_quatech_rqopr(port);
1203 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1204 reg = pci_quatech_rqopr(port) & 0xC0;
1205 if (reg != QPCR_TEST_GET1)
1207 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1208 reg = pci_quatech_rqopr(port) & 0xC0;
1209 if (reg != QPCR_TEST_GET2)
1211 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1212 reg = pci_quatech_rqopr(port) & 0xC0;
1213 if (reg != QPCR_TEST_GET3)
1215 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1216 reg = pci_quatech_rqopr(port) & 0xC0;
1217 if (reg != QPCR_TEST_GET4)
1220 pci_quatech_wqopr(port, qopr);
1224 static int pci_quatech_clock(struct uart_8250_port *port)
1227 unsigned long clock;
1229 if (pci_quatech_test(port) < 0)
1232 qopr = pci_quatech_rqopr(port);
1234 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1235 reg = pci_quatech_rqopr(port);
1236 if (reg & QOPR_CLOCK_X8) {
1240 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1241 reg = pci_quatech_rqopr(port);
1242 if (!(reg & QOPR_CLOCK_X8)) {
1246 reg &= QOPR_CLOCK_X8;
1247 if (reg == QOPR_CLOCK_X2) {
1249 set = QOPR_CLOCK_X2;
1250 } else if (reg == QOPR_CLOCK_X4) {
1252 set = QOPR_CLOCK_X4;
1253 } else if (reg == QOPR_CLOCK_X8) {
1255 set = QOPR_CLOCK_X8;
1258 set = QOPR_CLOCK_X1;
1260 qopr &= ~QOPR_CLOCK_RATE_MASK;
1264 pci_quatech_wqopr(port, qopr);
1268 static int pci_quatech_rs422(struct uart_8250_port *port)
1273 if (!pci_quatech_has_qmcr(port))
1275 qmcr = pci_quatech_rqmcr(port);
1276 pci_quatech_wqmcr(port, 0xFF);
1277 if (pci_quatech_rqmcr(port))
1279 pci_quatech_wqmcr(port, qmcr);
1283 static int pci_quatech_init(struct pci_dev *dev)
1285 if (pci_quatech_amcc(dev->device)) {
1286 unsigned long base = pci_resource_start(dev, 0);
1289 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1290 tmp = inl(base + 0x3c);
1291 outl(tmp | 0x01000000, base + 0x3c);
1292 outl(tmp &= ~0x01000000, base + 0x3c);
1298 static int pci_quatech_setup(struct serial_private *priv,
1299 const struct pciserial_board *board,
1300 struct uart_8250_port *port, int idx)
1302 /* Needed by pci_quatech calls below */
1303 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1304 /* Set up the clocking */
1305 port->port.uartclk = pci_quatech_clock(port);
1306 /* For now just warn about RS422 */
1307 if (pci_quatech_rs422(port))
1308 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1309 return pci_default_setup(priv, board, port, idx);
1312 static void pci_quatech_exit(struct pci_dev *dev)
1316 static int pci_default_setup(struct serial_private *priv,
1317 const struct pciserial_board *board,
1318 struct uart_8250_port *port, int idx)
1320 unsigned int bar, offset = board->first_offset, maxnr;
1322 bar = FL_GET_BASE(board->flags);
1323 if (board->flags & FL_BASE_BARS)
1326 offset += idx * board->uart_offset;
1328 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1329 (board->reg_shift + 3);
1331 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1334 return setup_port(priv, port, bar, offset, board->reg_shift);
1337 static int pci_pericom_setup(struct serial_private *priv,
1338 const struct pciserial_board *board,
1339 struct uart_8250_port *port, int idx)
1341 unsigned int bar, offset = board->first_offset, maxnr;
1343 bar = FL_GET_BASE(board->flags);
1344 if (board->flags & FL_BASE_BARS)
1347 offset += idx * board->uart_offset;
1349 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1350 (board->reg_shift + 3);
1352 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1355 port->port.uartclk = 14745600;
1357 return setup_port(priv, port, bar, offset, board->reg_shift);
1361 ce4100_serial_setup(struct serial_private *priv,
1362 const struct pciserial_board *board,
1363 struct uart_8250_port *port, int idx)
1367 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1368 port->port.iotype = UPIO_MEM32;
1369 port->port.type = PORT_XSCALE;
1370 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1371 port->port.regshift = 2;
1376 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1377 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1379 #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1380 #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1382 #define PCI_DEVICE_ID_INTEL_BDW_UART1 0x9ce3
1383 #define PCI_DEVICE_ID_INTEL_BDW_UART2 0x9ce4
1385 #define BYT_PRV_CLK 0x800
1386 #define BYT_PRV_CLK_EN (1 << 0)
1387 #define BYT_PRV_CLK_M_VAL_SHIFT 1
1388 #define BYT_PRV_CLK_N_VAL_SHIFT 16
1389 #define BYT_PRV_CLK_UPDATE (1 << 31)
1391 #define BYT_TX_OVF_INT 0x820
1392 #define BYT_TX_OVF_INT_MASK (1 << 1)
1395 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1396 struct ktermios *old)
1398 unsigned int baud = tty_termios_baud_rate(termios);
1399 unsigned long fref = 100000000, fuart = baud * 16;
1400 unsigned long w = BIT(15) - 1;
1404 /* Gracefully handle the B0 case: fall back to B9600 */
1405 fuart = fuart ? fuart : 9600 * 16;
1407 /* Get Fuart closer to Fref */
1408 fuart *= rounddown_pow_of_two(fref / fuart);
1411 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1412 * dividers must be adjusted.
1414 * uartclk = (m / n) * 100 MHz, where m <= n
1416 rational_best_approximation(fuart, fref, w, w, &m, &n);
1419 /* Reset the clock */
1420 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1421 writel(reg, p->membase + BYT_PRV_CLK);
1422 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1423 writel(reg, p->membase + BYT_PRV_CLK);
1425 p->status &= ~UPSTAT_AUTOCTS;
1426 if (termios->c_cflag & CRTSCTS)
1427 p->status |= UPSTAT_AUTOCTS;
1429 serial8250_do_set_termios(p, termios, old);
1432 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1434 struct dw_dma_slave *dws = param;
1436 if (dws->dma_dev != chan->device->dev)
1439 chan->private = dws;
1444 byt_serial_setup(struct serial_private *priv,
1445 const struct pciserial_board *board,
1446 struct uart_8250_port *port, int idx)
1448 struct pci_dev *pdev = priv->dev;
1449 struct device *dev = port->port.dev;
1450 struct uart_8250_dma *dma;
1451 struct dw_dma_slave *tx_param, *rx_param;
1452 struct pci_dev *dma_dev;
1455 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1459 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1463 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1467 switch (pdev->device) {
1468 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1469 case PCI_DEVICE_ID_INTEL_BSW_UART1:
1470 case PCI_DEVICE_ID_INTEL_BDW_UART1:
1471 rx_param->src_id = 3;
1472 tx_param->dst_id = 2;
1474 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1475 case PCI_DEVICE_ID_INTEL_BSW_UART2:
1476 case PCI_DEVICE_ID_INTEL_BDW_UART2:
1477 rx_param->src_id = 5;
1478 tx_param->dst_id = 4;
1484 rx_param->src_master = 1;
1485 rx_param->dst_master = 0;
1487 dma->rxconf.src_maxburst = 16;
1489 tx_param->src_master = 1;
1490 tx_param->dst_master = 0;
1492 dma->txconf.dst_maxburst = 16;
1494 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1495 rx_param->dma_dev = &dma_dev->dev;
1496 tx_param->dma_dev = &dma_dev->dev;
1498 dma->fn = byt_dma_filter;
1499 dma->rx_param = rx_param;
1500 dma->tx_param = tx_param;
1502 ret = pci_default_setup(priv, board, port, idx);
1503 port->port.iotype = UPIO_MEM;
1504 port->port.type = PORT_16550A;
1505 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1506 port->port.set_termios = byt_set_termios;
1507 port->port.fifosize = 64;
1508 port->tx_loadsz = 64;
1510 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1512 /* Disable Tx counter interrupts */
1513 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1519 pci_omegapci_setup(struct serial_private *priv,
1520 const struct pciserial_board *board,
1521 struct uart_8250_port *port, int idx)
1523 return setup_port(priv, port, 2, idx * 8, 0);
1527 pci_brcm_trumanage_setup(struct serial_private *priv,
1528 const struct pciserial_board *board,
1529 struct uart_8250_port *port, int idx)
1531 int ret = pci_default_setup(priv, board, port, idx);
1533 port->port.type = PORT_BRCM_TRUMANAGE;
1534 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1538 /* RTS will control by MCR if this bit is 0 */
1539 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1540 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1541 #define FINTEK_RTS_INVERT BIT(5)
1543 /* We should do proper H/W transceiver setting before change to RS485 mode */
1544 static int pci_fintek_rs485_config(struct uart_port *port,
1545 struct serial_rs485 *rs485)
1548 u8 *index = (u8 *) port->private_data;
1549 struct pci_dev *pci_dev = container_of(port->dev, struct pci_dev,
1552 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1555 rs485 = &port->rs485;
1556 else if (rs485->flags & SER_RS485_ENABLED)
1557 memset(rs485->padding, 0, sizeof(rs485->padding));
1559 memset(rs485, 0, sizeof(*rs485));
1561 /* F81504/508/512 not support RTS delay before or after send */
1562 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1564 if (rs485->flags & SER_RS485_ENABLED) {
1565 /* Enable RTS H/W control mode */
1566 setting |= FINTEK_RTS_CONTROL_BY_HW;
1568 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1569 /* RTS driving high on TX */
1570 setting &= ~FINTEK_RTS_INVERT;
1572 /* RTS driving low on TX */
1573 setting |= FINTEK_RTS_INVERT;
1576 rs485->delay_rts_after_send = 0;
1577 rs485->delay_rts_before_send = 0;
1579 /* Disable RTS H/W control mode */
1580 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1583 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1585 if (rs485 != &port->rs485)
1586 port->rs485 = *rs485;
1591 static int pci_fintek_setup(struct serial_private *priv,
1592 const struct pciserial_board *board,
1593 struct uart_8250_port *port, int idx)
1595 struct pci_dev *pdev = priv->dev;
1600 config_base = 0x40 + 0x08 * idx;
1602 /* Get the io address from configuration space */
1603 pci_read_config_word(pdev, config_base + 4, &iobase);
1605 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1607 port->port.iotype = UPIO_PORT;
1608 port->port.iobase = iobase;
1609 port->port.rs485_config = pci_fintek_rs485_config;
1611 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1615 /* preserve index in PCI configuration space */
1617 port->port.private_data = data;
1622 static int pci_fintek_init(struct pci_dev *dev)
1624 unsigned long iobase;
1628 struct serial_private *priv = pci_get_drvdata(dev);
1629 struct uart_8250_port *port;
1631 switch (dev->device) {
1632 case 0x1104: /* 4 ports */
1633 case 0x1108: /* 8 ports */
1634 max_port = dev->device & 0xff;
1636 case 0x1112: /* 12 ports */
1643 /* Get the io address dispatch from the BIOS */
1644 pci_read_config_dword(dev, 0x24, &bar_data[0]);
1645 pci_read_config_dword(dev, 0x20, &bar_data[1]);
1646 pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1648 for (i = 0; i < max_port; ++i) {
1649 /* UART0 configuration offset start from 0x40 */
1650 config_base = 0x40 + 0x08 * i;
1652 /* Calculate Real IO Port */
1653 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1655 /* Enable UART I/O port */
1656 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1658 /* Select 128-byte FIFO and 8x FIFO threshold */
1659 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1662 pci_write_config_byte(dev, config_base + 0x04,
1663 (u8)(iobase & 0xff));
1666 pci_write_config_byte(dev, config_base + 0x05,
1667 (u8)((iobase & 0xff00) >> 8));
1669 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1672 /* re-apply RS232/485 mode when
1673 * pciserial_resume_ports()
1675 port = serial8250_get_port(priv->line[i]);
1676 pci_fintek_rs485_config(&port->port, NULL);
1678 /* First init without port data
1679 * force init to RS232 Mode
1681 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1688 static int skip_tx_en_setup(struct serial_private *priv,
1689 const struct pciserial_board *board,
1690 struct uart_8250_port *port, int idx)
1692 port->port.flags |= UPF_NO_TXEN_TEST;
1693 dev_dbg(&priv->dev->dev,
1694 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1695 priv->dev->vendor, priv->dev->device,
1696 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1698 return pci_default_setup(priv, board, port, idx);
1701 static void kt_handle_break(struct uart_port *p)
1703 struct uart_8250_port *up = up_to_u8250p(p);
1705 * On receipt of a BI, serial device in Intel ME (Intel
1706 * management engine) needs to have its fifos cleared for sane
1707 * SOL (Serial Over Lan) output.
1709 serial8250_clear_and_reinit_fifos(up);
1712 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1714 struct uart_8250_port *up = up_to_u8250p(p);
1718 * When the Intel ME (management engine) gets reset its serial
1719 * port registers could return 0 momentarily. Functions like
1720 * serial8250_console_write, read and save the IER, perform
1721 * some operation and then restore it. In order to avoid
1722 * setting IER register inadvertently to 0, if the value read
1723 * is 0, double check with ier value in uart_8250_port and use
1724 * that instead. up->ier should be the same value as what is
1725 * currently configured.
1727 val = inb(p->iobase + offset);
1728 if (offset == UART_IER) {
1735 static int kt_serial_setup(struct serial_private *priv,
1736 const struct pciserial_board *board,
1737 struct uart_8250_port *port, int idx)
1739 port->port.flags |= UPF_BUG_THRE;
1740 port->port.serial_in = kt_serial_in;
1741 port->port.handle_break = kt_handle_break;
1742 return skip_tx_en_setup(priv, board, port, idx);
1745 static int pci_eg20t_init(struct pci_dev *dev)
1747 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1754 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
1755 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
1758 pci_xr17c154_setup(struct serial_private *priv,
1759 const struct pciserial_board *board,
1760 struct uart_8250_port *port, int idx)
1762 port->port.flags |= UPF_EXAR_EFR;
1763 return pci_default_setup(priv, board, port, idx);
1767 xr17v35x_has_slave(struct serial_private *priv)
1769 const int dev_id = priv->dev->device;
1771 return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1772 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1776 pci_xr17v35x_setup(struct serial_private *priv,
1777 const struct pciserial_board *board,
1778 struct uart_8250_port *port, int idx)
1782 p = pci_ioremap_bar(priv->dev, 0);
1786 port->port.flags |= UPF_EXAR_EFR;
1789 * Setup the uart clock for the devices on expansion slot to
1790 * half the clock speed of the main chip (which is 125MHz)
1792 if (xr17v35x_has_slave(priv) && idx >= 8)
1793 port->port.uartclk = (7812500 * 16 / 2);
1796 * Setup Multipurpose Input/Output pins.
1799 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1800 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1801 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1802 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1803 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1804 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1805 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1806 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1807 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1808 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1809 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1810 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1812 writeb(0x00, p + UART_EXAR_8XMODE);
1813 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1814 writeb(128, p + UART_EXAR_TXTRG);
1815 writeb(128, p + UART_EXAR_RXTRG);
1818 return pci_default_setup(priv, board, port, idx);
1821 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1822 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1823 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1824 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1827 pci_fastcom335_setup(struct serial_private *priv,
1828 const struct pciserial_board *board,
1829 struct uart_8250_port *port, int idx)
1833 p = pci_ioremap_bar(priv->dev, 0);
1837 port->port.flags |= UPF_EXAR_EFR;
1840 * Setup Multipurpose Input/Output pins.
1843 switch (priv->dev->device) {
1844 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1845 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1846 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1847 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1848 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1850 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1851 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1852 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1853 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1854 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1857 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1858 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1859 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1861 writeb(0x00, p + UART_EXAR_8XMODE);
1862 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1863 writeb(32, p + UART_EXAR_TXTRG);
1864 writeb(32, p + UART_EXAR_RXTRG);
1867 return pci_default_setup(priv, board, port, idx);
1871 pci_wch_ch353_setup(struct serial_private *priv,
1872 const struct pciserial_board *board,
1873 struct uart_8250_port *port, int idx)
1875 port->port.flags |= UPF_FIXED_TYPE;
1876 port->port.type = PORT_16550A;
1877 return pci_default_setup(priv, board, port, idx);
1881 pci_wch_ch38x_setup(struct serial_private *priv,
1882 const struct pciserial_board *board,
1883 struct uart_8250_port *port, int idx)
1885 port->port.flags |= UPF_FIXED_TYPE;
1886 port->port.type = PORT_16850;
1887 return pci_default_setup(priv, board, port, idx);
1890 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1891 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1892 #define PCI_DEVICE_ID_OCTPRO 0x0001
1893 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1894 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1895 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1896 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1897 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1898 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1899 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1900 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1901 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1902 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1903 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1904 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1905 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1906 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1907 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1908 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1909 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1910 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1911 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1912 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1913 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1914 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1915 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1916 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1917 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1918 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1919 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1920 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1921 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1922 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1923 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1924 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1925 #define PCI_VENDOR_ID_WCH 0x4348
1926 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1927 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1928 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1929 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1930 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1931 #define PCI_VENDOR_ID_AGESTAR 0x5372
1932 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1933 #define PCI_VENDOR_ID_ASIX 0x9710
1934 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1935 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1936 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1937 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1938 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1939 #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
1941 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1942 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1944 #define PCIE_VENDOR_ID_WCH 0x1c00
1945 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1946 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1947 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1949 #define PCI_VENDOR_ID_PERICOM 0x12D8
1950 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
1951 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
1952 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
1953 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
1955 #define PCI_VENDOR_ID_ACCESIO 0x494f
1956 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1957 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1958 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1959 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1960 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1961 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1962 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1963 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1964 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1965 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1966 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1967 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1968 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1969 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1970 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1971 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1972 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1973 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1974 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1975 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1976 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1977 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1978 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1979 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1980 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1981 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1982 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1983 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1984 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1985 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1986 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1987 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1988 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1992 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1993 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1994 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1997 * Master list of serial port init/setup/exit quirks.
1998 * This does not describe the general nature of the port.
1999 * (ie, baud base, number and location of ports, etc)
2001 * This list is ordered alphabetically by vendor then device.
2002 * Specific entries must come before more generic entries.
2004 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
2006 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2009 .vendor = PCI_VENDOR_ID_AMCC,
2010 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2011 .subvendor = PCI_ANY_ID,
2012 .subdevice = PCI_ANY_ID,
2013 .setup = addidata_apci7800_setup,
2016 * AFAVLAB cards - these may be called via parport_serial
2017 * It is not clear whether this applies to all products.
2020 .vendor = PCI_VENDOR_ID_AFAVLAB,
2021 .device = PCI_ANY_ID,
2022 .subvendor = PCI_ANY_ID,
2023 .subdevice = PCI_ANY_ID,
2024 .setup = afavlab_setup,
2030 .vendor = PCI_VENDOR_ID_HP,
2031 .device = PCI_DEVICE_ID_HP_DIVA,
2032 .subvendor = PCI_ANY_ID,
2033 .subdevice = PCI_ANY_ID,
2034 .init = pci_hp_diva_init,
2035 .setup = pci_hp_diva_setup,
2041 .vendor = PCI_VENDOR_ID_INTEL,
2042 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2043 .subvendor = 0xe4bf,
2044 .subdevice = PCI_ANY_ID,
2045 .init = pci_inteli960ni_init,
2046 .setup = pci_default_setup,
2049 .vendor = PCI_VENDOR_ID_INTEL,
2050 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2051 .subvendor = PCI_ANY_ID,
2052 .subdevice = PCI_ANY_ID,
2053 .setup = skip_tx_en_setup,
2056 .vendor = PCI_VENDOR_ID_INTEL,
2057 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2058 .subvendor = PCI_ANY_ID,
2059 .subdevice = PCI_ANY_ID,
2060 .setup = skip_tx_en_setup,
2063 .vendor = PCI_VENDOR_ID_INTEL,
2064 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2065 .subvendor = PCI_ANY_ID,
2066 .subdevice = PCI_ANY_ID,
2067 .setup = skip_tx_en_setup,
2070 .vendor = PCI_VENDOR_ID_INTEL,
2071 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2072 .subvendor = PCI_ANY_ID,
2073 .subdevice = PCI_ANY_ID,
2074 .setup = ce4100_serial_setup,
2077 .vendor = PCI_VENDOR_ID_INTEL,
2078 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2079 .subvendor = PCI_ANY_ID,
2080 .subdevice = PCI_ANY_ID,
2081 .setup = kt_serial_setup,
2084 .vendor = PCI_VENDOR_ID_INTEL,
2085 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
2086 .subvendor = PCI_ANY_ID,
2087 .subdevice = PCI_ANY_ID,
2088 .setup = byt_serial_setup,
2091 .vendor = PCI_VENDOR_ID_INTEL,
2092 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
2093 .subvendor = PCI_ANY_ID,
2094 .subdevice = PCI_ANY_ID,
2095 .setup = byt_serial_setup,
2098 .vendor = PCI_VENDOR_ID_INTEL,
2099 .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
2100 .subvendor = PCI_ANY_ID,
2101 .subdevice = PCI_ANY_ID,
2102 .setup = byt_serial_setup,
2105 .vendor = PCI_VENDOR_ID_INTEL,
2106 .device = PCI_DEVICE_ID_INTEL_BSW_UART2,
2107 .subvendor = PCI_ANY_ID,
2108 .subdevice = PCI_ANY_ID,
2109 .setup = byt_serial_setup,
2112 .vendor = PCI_VENDOR_ID_INTEL,
2113 .device = PCI_DEVICE_ID_INTEL_BDW_UART1,
2114 .subvendor = PCI_ANY_ID,
2115 .subdevice = PCI_ANY_ID,
2116 .setup = byt_serial_setup,
2119 .vendor = PCI_VENDOR_ID_INTEL,
2120 .device = PCI_DEVICE_ID_INTEL_BDW_UART2,
2121 .subvendor = PCI_ANY_ID,
2122 .subdevice = PCI_ANY_ID,
2123 .setup = byt_serial_setup,
2129 .vendor = PCI_VENDOR_ID_ITE,
2130 .device = PCI_DEVICE_ID_ITE_8872,
2131 .subvendor = PCI_ANY_ID,
2132 .subdevice = PCI_ANY_ID,
2133 .init = pci_ite887x_init,
2134 .setup = pci_default_setup,
2135 .exit = pci_ite887x_exit,
2138 * National Instruments
2141 .vendor = PCI_VENDOR_ID_NI,
2142 .device = PCI_DEVICE_ID_NI_PCI23216,
2143 .subvendor = PCI_ANY_ID,
2144 .subdevice = PCI_ANY_ID,
2145 .init = pci_ni8420_init,
2146 .setup = pci_default_setup,
2147 .exit = pci_ni8420_exit,
2150 .vendor = PCI_VENDOR_ID_NI,
2151 .device = PCI_DEVICE_ID_NI_PCI2328,
2152 .subvendor = PCI_ANY_ID,
2153 .subdevice = PCI_ANY_ID,
2154 .init = pci_ni8420_init,
2155 .setup = pci_default_setup,
2156 .exit = pci_ni8420_exit,
2159 .vendor = PCI_VENDOR_ID_NI,
2160 .device = PCI_DEVICE_ID_NI_PCI2324,
2161 .subvendor = PCI_ANY_ID,
2162 .subdevice = PCI_ANY_ID,
2163 .init = pci_ni8420_init,
2164 .setup = pci_default_setup,
2165 .exit = pci_ni8420_exit,
2168 .vendor = PCI_VENDOR_ID_NI,
2169 .device = PCI_DEVICE_ID_NI_PCI2322,
2170 .subvendor = PCI_ANY_ID,
2171 .subdevice = PCI_ANY_ID,
2172 .init = pci_ni8420_init,
2173 .setup = pci_default_setup,
2174 .exit = pci_ni8420_exit,
2177 .vendor = PCI_VENDOR_ID_NI,
2178 .device = PCI_DEVICE_ID_NI_PCI2324I,
2179 .subvendor = PCI_ANY_ID,
2180 .subdevice = PCI_ANY_ID,
2181 .init = pci_ni8420_init,
2182 .setup = pci_default_setup,
2183 .exit = pci_ni8420_exit,
2186 .vendor = PCI_VENDOR_ID_NI,
2187 .device = PCI_DEVICE_ID_NI_PCI2322I,
2188 .subvendor = PCI_ANY_ID,
2189 .subdevice = PCI_ANY_ID,
2190 .init = pci_ni8420_init,
2191 .setup = pci_default_setup,
2192 .exit = pci_ni8420_exit,
2195 .vendor = PCI_VENDOR_ID_NI,
2196 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2197 .subvendor = PCI_ANY_ID,
2198 .subdevice = PCI_ANY_ID,
2199 .init = pci_ni8420_init,
2200 .setup = pci_default_setup,
2201 .exit = pci_ni8420_exit,
2204 .vendor = PCI_VENDOR_ID_NI,
2205 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2206 .subvendor = PCI_ANY_ID,
2207 .subdevice = PCI_ANY_ID,
2208 .init = pci_ni8420_init,
2209 .setup = pci_default_setup,
2210 .exit = pci_ni8420_exit,
2213 .vendor = PCI_VENDOR_ID_NI,
2214 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2215 .subvendor = PCI_ANY_ID,
2216 .subdevice = PCI_ANY_ID,
2217 .init = pci_ni8420_init,
2218 .setup = pci_default_setup,
2219 .exit = pci_ni8420_exit,
2222 .vendor = PCI_VENDOR_ID_NI,
2223 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2224 .subvendor = PCI_ANY_ID,
2225 .subdevice = PCI_ANY_ID,
2226 .init = pci_ni8420_init,
2227 .setup = pci_default_setup,
2228 .exit = pci_ni8420_exit,
2231 .vendor = PCI_VENDOR_ID_NI,
2232 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2233 .subvendor = PCI_ANY_ID,
2234 .subdevice = PCI_ANY_ID,
2235 .init = pci_ni8420_init,
2236 .setup = pci_default_setup,
2237 .exit = pci_ni8420_exit,
2240 .vendor = PCI_VENDOR_ID_NI,
2241 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2242 .subvendor = PCI_ANY_ID,
2243 .subdevice = PCI_ANY_ID,
2244 .init = pci_ni8420_init,
2245 .setup = pci_default_setup,
2246 .exit = pci_ni8420_exit,
2249 .vendor = PCI_VENDOR_ID_NI,
2250 .device = PCI_ANY_ID,
2251 .subvendor = PCI_ANY_ID,
2252 .subdevice = PCI_ANY_ID,
2253 .init = pci_ni8430_init,
2254 .setup = pci_ni8430_setup,
2255 .exit = pci_ni8430_exit,
2259 .vendor = PCI_VENDOR_ID_QUATECH,
2260 .device = PCI_ANY_ID,
2261 .subvendor = PCI_ANY_ID,
2262 .subdevice = PCI_ANY_ID,
2263 .init = pci_quatech_init,
2264 .setup = pci_quatech_setup,
2265 .exit = pci_quatech_exit,
2271 .vendor = PCI_VENDOR_ID_PANACOM,
2272 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2273 .subvendor = PCI_ANY_ID,
2274 .subdevice = PCI_ANY_ID,
2275 .init = pci_plx9050_init,
2276 .setup = pci_default_setup,
2277 .exit = pci_plx9050_exit,
2280 .vendor = PCI_VENDOR_ID_PANACOM,
2281 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2282 .subvendor = PCI_ANY_ID,
2283 .subdevice = PCI_ANY_ID,
2284 .init = pci_plx9050_init,
2285 .setup = pci_default_setup,
2286 .exit = pci_plx9050_exit,
2292 .vendor = PCI_VENDOR_ID_PERICOM,
2293 .device = PCI_ANY_ID,
2294 .subvendor = PCI_ANY_ID,
2295 .subdevice = PCI_ANY_ID,
2296 .setup = pci_pericom_setup,
2302 .vendor = PCI_VENDOR_ID_PLX,
2303 .device = PCI_DEVICE_ID_PLX_9050,
2304 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2305 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2306 .init = pci_plx9050_init,
2307 .setup = pci_default_setup,
2308 .exit = pci_plx9050_exit,
2311 .vendor = PCI_VENDOR_ID_PLX,
2312 .device = PCI_DEVICE_ID_PLX_9050,
2313 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2314 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2315 .init = pci_plx9050_init,
2316 .setup = pci_default_setup,
2317 .exit = pci_plx9050_exit,
2320 .vendor = PCI_VENDOR_ID_PLX,
2321 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2322 .subvendor = PCI_VENDOR_ID_PLX,
2323 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2324 .init = pci_plx9050_init,
2325 .setup = pci_default_setup,
2326 .exit = pci_plx9050_exit,
2329 * SBS Technologies, Inc., PMC-OCTALPRO 232
2332 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2333 .device = PCI_DEVICE_ID_OCTPRO,
2334 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2335 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2341 * SBS Technologies, Inc., PMC-OCTALPRO 422
2344 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2345 .device = PCI_DEVICE_ID_OCTPRO,
2346 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2347 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2353 * SBS Technologies, Inc., P-Octal 232
2356 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2357 .device = PCI_DEVICE_ID_OCTPRO,
2358 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2359 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2365 * SBS Technologies, Inc., P-Octal 422
2368 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2369 .device = PCI_DEVICE_ID_OCTPRO,
2370 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2371 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2377 * SIIG cards - these may be called via parport_serial
2380 .vendor = PCI_VENDOR_ID_SIIG,
2381 .device = PCI_ANY_ID,
2382 .subvendor = PCI_ANY_ID,
2383 .subdevice = PCI_ANY_ID,
2384 .init = pci_siig_init,
2385 .setup = pci_siig_setup,
2391 .vendor = PCI_VENDOR_ID_TITAN,
2392 .device = PCI_DEVICE_ID_TITAN_400L,
2393 .subvendor = PCI_ANY_ID,
2394 .subdevice = PCI_ANY_ID,
2395 .setup = titan_400l_800l_setup,
2398 .vendor = PCI_VENDOR_ID_TITAN,
2399 .device = PCI_DEVICE_ID_TITAN_800L,
2400 .subvendor = PCI_ANY_ID,
2401 .subdevice = PCI_ANY_ID,
2402 .setup = titan_400l_800l_setup,
2408 .vendor = PCI_VENDOR_ID_TIMEDIA,
2409 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2410 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2411 .subdevice = PCI_ANY_ID,
2412 .probe = pci_timedia_probe,
2413 .init = pci_timedia_init,
2414 .setup = pci_timedia_setup,
2417 .vendor = PCI_VENDOR_ID_TIMEDIA,
2418 .device = PCI_ANY_ID,
2419 .subvendor = PCI_ANY_ID,
2420 .subdevice = PCI_ANY_ID,
2421 .setup = pci_timedia_setup,
2424 * SUNIX (Timedia) cards
2425 * Do not "probe" for these cards as there is at least one combination
2426 * card that should be handled by parport_pc that doesn't match the
2427 * rule in pci_timedia_probe.
2428 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2429 * There are some boards with part number SER5037AL that report
2430 * subdevice ID 0x0002.
2433 .vendor = PCI_VENDOR_ID_SUNIX,
2434 .device = PCI_DEVICE_ID_SUNIX_1999,
2435 .subvendor = PCI_VENDOR_ID_SUNIX,
2436 .subdevice = PCI_ANY_ID,
2437 .init = pci_timedia_init,
2438 .setup = pci_timedia_setup,
2444 .vendor = PCI_VENDOR_ID_EXAR,
2445 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2446 .subvendor = PCI_ANY_ID,
2447 .subdevice = PCI_ANY_ID,
2448 .setup = pci_xr17c154_setup,
2451 .vendor = PCI_VENDOR_ID_EXAR,
2452 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2453 .subvendor = PCI_ANY_ID,
2454 .subdevice = PCI_ANY_ID,
2455 .setup = pci_xr17c154_setup,
2458 .vendor = PCI_VENDOR_ID_EXAR,
2459 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2460 .subvendor = PCI_ANY_ID,
2461 .subdevice = PCI_ANY_ID,
2462 .setup = pci_xr17c154_setup,
2465 .vendor = PCI_VENDOR_ID_EXAR,
2466 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2467 .subvendor = PCI_ANY_ID,
2468 .subdevice = PCI_ANY_ID,
2469 .setup = pci_xr17v35x_setup,
2472 .vendor = PCI_VENDOR_ID_EXAR,
2473 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2474 .subvendor = PCI_ANY_ID,
2475 .subdevice = PCI_ANY_ID,
2476 .setup = pci_xr17v35x_setup,
2479 .vendor = PCI_VENDOR_ID_EXAR,
2480 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2481 .subvendor = PCI_ANY_ID,
2482 .subdevice = PCI_ANY_ID,
2483 .setup = pci_xr17v35x_setup,
2486 .vendor = PCI_VENDOR_ID_EXAR,
2487 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2488 .subvendor = PCI_ANY_ID,
2489 .subdevice = PCI_ANY_ID,
2490 .setup = pci_xr17v35x_setup,
2493 .vendor = PCI_VENDOR_ID_EXAR,
2494 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2495 .subvendor = PCI_ANY_ID,
2496 .subdevice = PCI_ANY_ID,
2497 .setup = pci_xr17v35x_setup,
2503 .vendor = PCI_VENDOR_ID_XIRCOM,
2504 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2505 .subvendor = PCI_ANY_ID,
2506 .subdevice = PCI_ANY_ID,
2507 .init = pci_xircom_init,
2508 .setup = pci_default_setup,
2511 * Netmos cards - these may be called via parport_serial
2514 .vendor = PCI_VENDOR_ID_NETMOS,
2515 .device = PCI_ANY_ID,
2516 .subvendor = PCI_ANY_ID,
2517 .subdevice = PCI_ANY_ID,
2518 .init = pci_netmos_init,
2519 .setup = pci_netmos_9900_setup,
2522 * EndRun Technologies
2525 .vendor = PCI_VENDOR_ID_ENDRUN,
2526 .device = PCI_ANY_ID,
2527 .subvendor = PCI_ANY_ID,
2528 .subdevice = PCI_ANY_ID,
2529 .init = pci_endrun_init,
2530 .setup = pci_default_setup,
2533 * For Oxford Semiconductor Tornado based devices
2536 .vendor = PCI_VENDOR_ID_OXSEMI,
2537 .device = PCI_ANY_ID,
2538 .subvendor = PCI_ANY_ID,
2539 .subdevice = PCI_ANY_ID,
2540 .init = pci_oxsemi_tornado_init,
2541 .setup = pci_default_setup,
2544 .vendor = PCI_VENDOR_ID_MAINPINE,
2545 .device = PCI_ANY_ID,
2546 .subvendor = PCI_ANY_ID,
2547 .subdevice = PCI_ANY_ID,
2548 .init = pci_oxsemi_tornado_init,
2549 .setup = pci_default_setup,
2552 .vendor = PCI_VENDOR_ID_DIGI,
2553 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2554 .subvendor = PCI_SUBVENDOR_ID_IBM,
2555 .subdevice = PCI_ANY_ID,
2556 .init = pci_oxsemi_tornado_init,
2557 .setup = pci_default_setup,
2560 .vendor = PCI_VENDOR_ID_INTEL,
2562 .subvendor = PCI_ANY_ID,
2563 .subdevice = PCI_ANY_ID,
2564 .init = pci_eg20t_init,
2565 .setup = pci_default_setup,
2568 .vendor = PCI_VENDOR_ID_INTEL,
2570 .subvendor = PCI_ANY_ID,
2571 .subdevice = PCI_ANY_ID,
2572 .init = pci_eg20t_init,
2573 .setup = pci_default_setup,
2576 .vendor = PCI_VENDOR_ID_INTEL,
2578 .subvendor = PCI_ANY_ID,
2579 .subdevice = PCI_ANY_ID,
2580 .init = pci_eg20t_init,
2581 .setup = pci_default_setup,
2584 .vendor = PCI_VENDOR_ID_INTEL,
2586 .subvendor = PCI_ANY_ID,
2587 .subdevice = PCI_ANY_ID,
2588 .init = pci_eg20t_init,
2589 .setup = pci_default_setup,
2594 .subvendor = PCI_ANY_ID,
2595 .subdevice = PCI_ANY_ID,
2596 .init = pci_eg20t_init,
2597 .setup = pci_default_setup,
2602 .subvendor = PCI_ANY_ID,
2603 .subdevice = PCI_ANY_ID,
2604 .init = pci_eg20t_init,
2605 .setup = pci_default_setup,
2610 .subvendor = PCI_ANY_ID,
2611 .subdevice = PCI_ANY_ID,
2612 .init = pci_eg20t_init,
2613 .setup = pci_default_setup,
2618 .subvendor = PCI_ANY_ID,
2619 .subdevice = PCI_ANY_ID,
2620 .init = pci_eg20t_init,
2621 .setup = pci_default_setup,
2626 .subvendor = PCI_ANY_ID,
2627 .subdevice = PCI_ANY_ID,
2628 .init = pci_eg20t_init,
2629 .setup = pci_default_setup,
2632 * Cronyx Omega PCI (PLX-chip based)
2635 .vendor = PCI_VENDOR_ID_PLX,
2636 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2637 .subvendor = PCI_ANY_ID,
2638 .subdevice = PCI_ANY_ID,
2639 .setup = pci_omegapci_setup,
2641 /* WCH CH353 1S1P card (16550 clone) */
2643 .vendor = PCI_VENDOR_ID_WCH,
2644 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2645 .subvendor = PCI_ANY_ID,
2646 .subdevice = PCI_ANY_ID,
2647 .setup = pci_wch_ch353_setup,
2649 /* WCH CH353 2S1P card (16550 clone) */
2651 .vendor = PCI_VENDOR_ID_WCH,
2652 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2653 .subvendor = PCI_ANY_ID,
2654 .subdevice = PCI_ANY_ID,
2655 .setup = pci_wch_ch353_setup,
2657 /* WCH CH353 4S card (16550 clone) */
2659 .vendor = PCI_VENDOR_ID_WCH,
2660 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2661 .subvendor = PCI_ANY_ID,
2662 .subdevice = PCI_ANY_ID,
2663 .setup = pci_wch_ch353_setup,
2665 /* WCH CH353 2S1PF card (16550 clone) */
2667 .vendor = PCI_VENDOR_ID_WCH,
2668 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2669 .subvendor = PCI_ANY_ID,
2670 .subdevice = PCI_ANY_ID,
2671 .setup = pci_wch_ch353_setup,
2673 /* WCH CH352 2S card (16550 clone) */
2675 .vendor = PCI_VENDOR_ID_WCH,
2676 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2677 .subvendor = PCI_ANY_ID,
2678 .subdevice = PCI_ANY_ID,
2679 .setup = pci_wch_ch353_setup,
2681 /* WCH CH382 2S card (16850 clone) */
2683 .vendor = PCIE_VENDOR_ID_WCH,
2684 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2685 .subvendor = PCI_ANY_ID,
2686 .subdevice = PCI_ANY_ID,
2687 .setup = pci_wch_ch38x_setup,
2689 /* WCH CH382 2S1P card (16850 clone) */
2691 .vendor = PCIE_VENDOR_ID_WCH,
2692 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2693 .subvendor = PCI_ANY_ID,
2694 .subdevice = PCI_ANY_ID,
2695 .setup = pci_wch_ch38x_setup,
2697 /* WCH CH384 4S card (16850 clone) */
2699 .vendor = PCIE_VENDOR_ID_WCH,
2700 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2701 .subvendor = PCI_ANY_ID,
2702 .subdevice = PCI_ANY_ID,
2703 .setup = pci_wch_ch38x_setup,
2706 * ASIX devices with FIFO bug
2709 .vendor = PCI_VENDOR_ID_ASIX,
2710 .device = PCI_ANY_ID,
2711 .subvendor = PCI_ANY_ID,
2712 .subdevice = PCI_ANY_ID,
2713 .setup = pci_asix_setup,
2716 * Commtech, Inc. Fastcom adapters
2720 .vendor = PCI_VENDOR_ID_COMMTECH,
2721 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2722 .subvendor = PCI_ANY_ID,
2723 .subdevice = PCI_ANY_ID,
2724 .setup = pci_fastcom335_setup,
2727 .vendor = PCI_VENDOR_ID_COMMTECH,
2728 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2729 .subvendor = PCI_ANY_ID,
2730 .subdevice = PCI_ANY_ID,
2731 .setup = pci_fastcom335_setup,
2734 .vendor = PCI_VENDOR_ID_COMMTECH,
2735 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2736 .subvendor = PCI_ANY_ID,
2737 .subdevice = PCI_ANY_ID,
2738 .setup = pci_fastcom335_setup,
2741 .vendor = PCI_VENDOR_ID_COMMTECH,
2742 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2743 .subvendor = PCI_ANY_ID,
2744 .subdevice = PCI_ANY_ID,
2745 .setup = pci_fastcom335_setup,
2748 .vendor = PCI_VENDOR_ID_COMMTECH,
2749 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2750 .subvendor = PCI_ANY_ID,
2751 .subdevice = PCI_ANY_ID,
2752 .setup = pci_xr17v35x_setup,
2755 .vendor = PCI_VENDOR_ID_COMMTECH,
2756 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2757 .subvendor = PCI_ANY_ID,
2758 .subdevice = PCI_ANY_ID,
2759 .setup = pci_xr17v35x_setup,
2762 .vendor = PCI_VENDOR_ID_COMMTECH,
2763 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2764 .subvendor = PCI_ANY_ID,
2765 .subdevice = PCI_ANY_ID,
2766 .setup = pci_xr17v35x_setup,
2769 * Broadcom TruManage (NetXtreme)
2772 .vendor = PCI_VENDOR_ID_BROADCOM,
2773 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2774 .subvendor = PCI_ANY_ID,
2775 .subdevice = PCI_ANY_ID,
2776 .setup = pci_brcm_trumanage_setup,
2781 .subvendor = PCI_ANY_ID,
2782 .subdevice = PCI_ANY_ID,
2783 .setup = pci_fintek_setup,
2784 .init = pci_fintek_init,
2789 .subvendor = PCI_ANY_ID,
2790 .subdevice = PCI_ANY_ID,
2791 .setup = pci_fintek_setup,
2792 .init = pci_fintek_init,
2797 .subvendor = PCI_ANY_ID,
2798 .subdevice = PCI_ANY_ID,
2799 .setup = pci_fintek_setup,
2800 .init = pci_fintek_init,
2804 * Default "match everything" terminator entry
2807 .vendor = PCI_ANY_ID,
2808 .device = PCI_ANY_ID,
2809 .subvendor = PCI_ANY_ID,
2810 .subdevice = PCI_ANY_ID,
2811 .setup = pci_default_setup,
2815 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2817 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2820 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2822 struct pci_serial_quirk *quirk;
2824 for (quirk = pci_serial_quirks; ; quirk++)
2825 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2826 quirk_id_matches(quirk->device, dev->device) &&
2827 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2828 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2833 static inline int get_pci_irq(struct pci_dev *dev,
2834 const struct pciserial_board *board)
2836 if (board->flags & FL_NOIRQ)
2843 * This is the configuration table for all of the PCI serial boards
2844 * which we support. It is directly indexed by the pci_board_num_t enum
2845 * value, which is encoded in the pci_device_id PCI probe table's
2846 * driver_data member.
2848 * The makeup of these names are:
2849 * pbn_bn{_bt}_n_baud{_offsetinhex}
2851 * bn = PCI BAR number
2852 * bt = Index using PCI BARs
2853 * n = number of serial ports
2855 * offsetinhex = offset for each sequential port (in hex)
2857 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2859 * Please note: in theory if n = 1, _bt infix should make no difference.
2860 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2862 enum pci_board_num_t {
2879 pbn_b0_2_1152000_200,
2880 pbn_b0_4_1152000_200,
2881 pbn_b0_8_1152000_200,
2886 pbn_b0_2_1843200_200,
2887 pbn_b0_4_1843200_200,
2888 pbn_b0_8_1843200_200,
2962 * Board-specific versions.
2968 pbn_endrun_2_4000000,
2970 pbn_oxsemi_1_4000000,
2971 pbn_oxsemi_2_4000000,
2972 pbn_oxsemi_4_4000000,
2973 pbn_oxsemi_8_4000000,
2988 pbn_exar_ibm_saturn,
2994 pbn_ADDIDATA_PCIe_1_3906250,
2995 pbn_ADDIDATA_PCIe_2_3906250,
2996 pbn_ADDIDATA_PCIe_4_3906250,
2997 pbn_ADDIDATA_PCIe_8_3906250,
2998 pbn_ce4100_1_115200,
3002 pbn_NETMOS9900_2s_115200,
3009 pbn_pericom_PI7C9X7951,
3010 pbn_pericom_PI7C9X7952,
3011 pbn_pericom_PI7C9X7954,
3012 pbn_pericom_PI7C9X7958,
3016 * uart_offset - the space between channels
3017 * reg_shift - describes how the UART registers are mapped
3018 * to PCI memory by the card.
3019 * For example IER register on SBS, Inc. PMC-OctPro is located at
3020 * offset 0x10 from the UART base, while UART_IER is defined as 1
3021 * in include/linux/serial_reg.h,
3022 * see first lines of serial_in() and serial_out() in 8250.c
3025 static struct pciserial_board pci_boards[] = {
3029 .base_baud = 115200,
3032 [pbn_b0_1_115200] = {
3035 .base_baud = 115200,
3038 [pbn_b0_2_115200] = {
3041 .base_baud = 115200,
3044 [pbn_b0_4_115200] = {
3047 .base_baud = 115200,
3050 [pbn_b0_5_115200] = {
3053 .base_baud = 115200,
3056 [pbn_b0_8_115200] = {
3059 .base_baud = 115200,
3062 [pbn_b0_1_921600] = {
3065 .base_baud = 921600,
3068 [pbn_b0_2_921600] = {
3071 .base_baud = 921600,
3074 [pbn_b0_4_921600] = {
3077 .base_baud = 921600,
3081 [pbn_b0_2_1130000] = {
3084 .base_baud = 1130000,
3088 [pbn_b0_4_1152000] = {
3091 .base_baud = 1152000,
3095 [pbn_b0_2_1152000_200] = {
3098 .base_baud = 1152000,
3099 .uart_offset = 0x200,
3102 [pbn_b0_4_1152000_200] = {
3105 .base_baud = 1152000,
3106 .uart_offset = 0x200,
3109 [pbn_b0_8_1152000_200] = {
3112 .base_baud = 1152000,
3113 .uart_offset = 0x200,
3116 [pbn_b0_2_1843200] = {
3119 .base_baud = 1843200,
3122 [pbn_b0_4_1843200] = {
3125 .base_baud = 1843200,
3129 [pbn_b0_2_1843200_200] = {
3132 .base_baud = 1843200,
3133 .uart_offset = 0x200,
3135 [pbn_b0_4_1843200_200] = {
3138 .base_baud = 1843200,
3139 .uart_offset = 0x200,
3141 [pbn_b0_8_1843200_200] = {
3144 .base_baud = 1843200,
3145 .uart_offset = 0x200,
3147 [pbn_b0_1_4000000] = {
3150 .base_baud = 4000000,
3154 [pbn_b0_bt_1_115200] = {
3155 .flags = FL_BASE0|FL_BASE_BARS,
3157 .base_baud = 115200,
3160 [pbn_b0_bt_2_115200] = {
3161 .flags = FL_BASE0|FL_BASE_BARS,
3163 .base_baud = 115200,
3166 [pbn_b0_bt_4_115200] = {
3167 .flags = FL_BASE0|FL_BASE_BARS,
3169 .base_baud = 115200,
3172 [pbn_b0_bt_8_115200] = {
3173 .flags = FL_BASE0|FL_BASE_BARS,
3175 .base_baud = 115200,
3179 [pbn_b0_bt_1_460800] = {
3180 .flags = FL_BASE0|FL_BASE_BARS,
3182 .base_baud = 460800,
3185 [pbn_b0_bt_2_460800] = {
3186 .flags = FL_BASE0|FL_BASE_BARS,
3188 .base_baud = 460800,
3191 [pbn_b0_bt_4_460800] = {
3192 .flags = FL_BASE0|FL_BASE_BARS,
3194 .base_baud = 460800,
3198 [pbn_b0_bt_1_921600] = {
3199 .flags = FL_BASE0|FL_BASE_BARS,
3201 .base_baud = 921600,
3204 [pbn_b0_bt_2_921600] = {
3205 .flags = FL_BASE0|FL_BASE_BARS,
3207 .base_baud = 921600,
3210 [pbn_b0_bt_4_921600] = {
3211 .flags = FL_BASE0|FL_BASE_BARS,
3213 .base_baud = 921600,
3216 [pbn_b0_bt_8_921600] = {
3217 .flags = FL_BASE0|FL_BASE_BARS,
3219 .base_baud = 921600,
3223 [pbn_b1_1_115200] = {
3226 .base_baud = 115200,
3229 [pbn_b1_2_115200] = {
3232 .base_baud = 115200,
3235 [pbn_b1_4_115200] = {
3238 .base_baud = 115200,
3241 [pbn_b1_8_115200] = {
3244 .base_baud = 115200,
3247 [pbn_b1_16_115200] = {
3250 .base_baud = 115200,
3254 [pbn_b1_1_921600] = {
3257 .base_baud = 921600,
3260 [pbn_b1_2_921600] = {
3263 .base_baud = 921600,
3266 [pbn_b1_4_921600] = {
3269 .base_baud = 921600,
3272 [pbn_b1_8_921600] = {
3275 .base_baud = 921600,
3278 [pbn_b1_2_1250000] = {
3281 .base_baud = 1250000,
3285 [pbn_b1_bt_1_115200] = {
3286 .flags = FL_BASE1|FL_BASE_BARS,
3288 .base_baud = 115200,
3291 [pbn_b1_bt_2_115200] = {
3292 .flags = FL_BASE1|FL_BASE_BARS,
3294 .base_baud = 115200,
3297 [pbn_b1_bt_4_115200] = {
3298 .flags = FL_BASE1|FL_BASE_BARS,
3300 .base_baud = 115200,
3304 [pbn_b1_bt_2_921600] = {
3305 .flags = FL_BASE1|FL_BASE_BARS,
3307 .base_baud = 921600,
3311 [pbn_b1_1_1382400] = {
3314 .base_baud = 1382400,
3317 [pbn_b1_2_1382400] = {
3320 .base_baud = 1382400,
3323 [pbn_b1_4_1382400] = {
3326 .base_baud = 1382400,
3329 [pbn_b1_8_1382400] = {
3332 .base_baud = 1382400,
3336 [pbn_b2_1_115200] = {
3339 .base_baud = 115200,
3342 [pbn_b2_2_115200] = {
3345 .base_baud = 115200,
3348 [pbn_b2_4_115200] = {
3351 .base_baud = 115200,
3354 [pbn_b2_8_115200] = {
3357 .base_baud = 115200,
3361 [pbn_b2_1_460800] = {
3364 .base_baud = 460800,
3367 [pbn_b2_4_460800] = {
3370 .base_baud = 460800,
3373 [pbn_b2_8_460800] = {
3376 .base_baud = 460800,
3379 [pbn_b2_16_460800] = {
3382 .base_baud = 460800,
3386 [pbn_b2_1_921600] = {
3389 .base_baud = 921600,
3392 [pbn_b2_4_921600] = {
3395 .base_baud = 921600,
3398 [pbn_b2_8_921600] = {
3401 .base_baud = 921600,
3405 [pbn_b2_8_1152000] = {
3408 .base_baud = 1152000,
3412 [pbn_b2_bt_1_115200] = {
3413 .flags = FL_BASE2|FL_BASE_BARS,
3415 .base_baud = 115200,
3418 [pbn_b2_bt_2_115200] = {
3419 .flags = FL_BASE2|FL_BASE_BARS,
3421 .base_baud = 115200,
3424 [pbn_b2_bt_4_115200] = {
3425 .flags = FL_BASE2|FL_BASE_BARS,
3427 .base_baud = 115200,
3431 [pbn_b2_bt_2_921600] = {
3432 .flags = FL_BASE2|FL_BASE_BARS,
3434 .base_baud = 921600,
3437 [pbn_b2_bt_4_921600] = {
3438 .flags = FL_BASE2|FL_BASE_BARS,
3440 .base_baud = 921600,
3444 [pbn_b3_2_115200] = {
3447 .base_baud = 115200,
3450 [pbn_b3_4_115200] = {
3453 .base_baud = 115200,
3456 [pbn_b3_8_115200] = {
3459 .base_baud = 115200,
3463 [pbn_b4_bt_2_921600] = {
3466 .base_baud = 921600,
3469 [pbn_b4_bt_4_921600] = {
3472 .base_baud = 921600,
3475 [pbn_b4_bt_8_921600] = {
3478 .base_baud = 921600,
3483 * Entries following this are board-specific.
3492 .base_baud = 921600,
3493 .uart_offset = 0x400,
3497 .flags = FL_BASE2|FL_BASE_BARS,
3499 .base_baud = 921600,
3500 .uart_offset = 0x400,
3504 .flags = FL_BASE2|FL_BASE_BARS,
3506 .base_baud = 921600,
3507 .uart_offset = 0x400,
3511 /* I think this entry is broken - the first_offset looks wrong --rmk */
3512 [pbn_plx_romulus] = {
3515 .base_baud = 921600,
3516 .uart_offset = 8 << 2,
3518 .first_offset = 0x03,
3522 * EndRun Technologies
3523 * Uses the size of PCI Base region 0 to
3524 * signal now many ports are available
3525 * 2 port 952 Uart support
3527 [pbn_endrun_2_4000000] = {
3530 .base_baud = 4000000,
3531 .uart_offset = 0x200,
3532 .first_offset = 0x1000,
3536 * This board uses the size of PCI Base region 0 to
3537 * signal now many ports are available
3540 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3542 .base_baud = 115200,
3545 [pbn_oxsemi_1_4000000] = {
3548 .base_baud = 4000000,
3549 .uart_offset = 0x200,
3550 .first_offset = 0x1000,
3552 [pbn_oxsemi_2_4000000] = {
3555 .base_baud = 4000000,
3556 .uart_offset = 0x200,
3557 .first_offset = 0x1000,
3559 [pbn_oxsemi_4_4000000] = {
3562 .base_baud = 4000000,
3563 .uart_offset = 0x200,
3564 .first_offset = 0x1000,
3566 [pbn_oxsemi_8_4000000] = {
3569 .base_baud = 4000000,
3570 .uart_offset = 0x200,
3571 .first_offset = 0x1000,
3576 * EKF addition for i960 Boards form EKF with serial port.
3579 [pbn_intel_i960] = {
3582 .base_baud = 921600,
3583 .uart_offset = 8 << 2,
3585 .first_offset = 0x10000,
3588 .flags = FL_BASE0|FL_NOIRQ,
3590 .base_baud = 458333,
3593 .first_offset = 0x20178,
3597 * Computone - uses IOMEM.
3599 [pbn_computone_4] = {
3602 .base_baud = 921600,
3603 .uart_offset = 0x40,
3605 .first_offset = 0x200,
3607 [pbn_computone_6] = {
3610 .base_baud = 921600,
3611 .uart_offset = 0x40,
3613 .first_offset = 0x200,
3615 [pbn_computone_8] = {
3618 .base_baud = 921600,
3619 .uart_offset = 0x40,
3621 .first_offset = 0x200,
3626 .base_baud = 460800,
3631 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3632 * Only basic 16550A support.
3633 * XR17C15[24] are not tested, but they should work.
3635 [pbn_exar_XR17C152] = {
3638 .base_baud = 921600,
3639 .uart_offset = 0x200,
3641 [pbn_exar_XR17C154] = {
3644 .base_baud = 921600,
3645 .uart_offset = 0x200,
3647 [pbn_exar_XR17C158] = {
3650 .base_baud = 921600,
3651 .uart_offset = 0x200,
3653 [pbn_exar_XR17V352] = {
3656 .base_baud = 7812500,
3657 .uart_offset = 0x400,
3661 [pbn_exar_XR17V354] = {
3664 .base_baud = 7812500,
3665 .uart_offset = 0x400,
3669 [pbn_exar_XR17V358] = {
3672 .base_baud = 7812500,
3673 .uart_offset = 0x400,
3677 [pbn_exar_XR17V4358] = {
3680 .base_baud = 7812500,
3681 .uart_offset = 0x400,
3685 [pbn_exar_XR17V8358] = {
3688 .base_baud = 7812500,
3689 .uart_offset = 0x400,
3693 [pbn_exar_ibm_saturn] = {
3696 .base_baud = 921600,
3697 .uart_offset = 0x200,
3701 * PA Semi PWRficient PA6T-1682M on-chip UART
3703 [pbn_pasemi_1682M] = {
3706 .base_baud = 8333333,
3709 * National Instruments 843x
3714 .base_baud = 3686400,
3715 .uart_offset = 0x10,
3716 .first_offset = 0x800,
3721 .base_baud = 3686400,
3722 .uart_offset = 0x10,
3723 .first_offset = 0x800,
3728 .base_baud = 3686400,
3729 .uart_offset = 0x10,
3730 .first_offset = 0x800,
3735 .base_baud = 3686400,
3736 .uart_offset = 0x10,
3737 .first_offset = 0x800,
3740 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3742 [pbn_ADDIDATA_PCIe_1_3906250] = {
3745 .base_baud = 3906250,
3746 .uart_offset = 0x200,
3747 .first_offset = 0x1000,
3749 [pbn_ADDIDATA_PCIe_2_3906250] = {
3752 .base_baud = 3906250,
3753 .uart_offset = 0x200,
3754 .first_offset = 0x1000,
3756 [pbn_ADDIDATA_PCIe_4_3906250] = {
3759 .base_baud = 3906250,
3760 .uart_offset = 0x200,
3761 .first_offset = 0x1000,
3763 [pbn_ADDIDATA_PCIe_8_3906250] = {
3766 .base_baud = 3906250,
3767 .uart_offset = 0x200,
3768 .first_offset = 0x1000,
3770 [pbn_ce4100_1_115200] = {
3771 .flags = FL_BASE_BARS,
3773 .base_baud = 921600,
3777 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3778 * but is overridden by byt_set_termios.
3783 .base_baud = 2764800,
3784 .uart_offset = 0x80,
3790 .base_baud = 2764800,
3796 .base_baud = 115200,
3797 .uart_offset = 0x200,
3799 [pbn_NETMOS9900_2s_115200] = {
3802 .base_baud = 115200,
3804 [pbn_brcm_trumanage] = {
3808 .base_baud = 115200,
3813 .base_baud = 115200,
3814 .first_offset = 0x40,
3819 .base_baud = 115200,
3820 .first_offset = 0x40,
3825 .base_baud = 115200,
3826 .first_offset = 0x40,
3831 .base_baud = 115200,
3833 .first_offset = 0xC0,
3838 .base_baud = 115200,
3840 .first_offset = 0xC0,
3843 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3845 [pbn_pericom_PI7C9X7951] = {
3848 .base_baud = 921600,
3851 [pbn_pericom_PI7C9X7952] = {
3854 .base_baud = 921600,
3857 [pbn_pericom_PI7C9X7954] = {
3860 .base_baud = 921600,
3863 [pbn_pericom_PI7C9X7958] = {
3866 .base_baud = 921600,
3871 static const struct pci_device_id blacklist[] = {
3873 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3874 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3875 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3877 /* multi-io cards handled by parport_serial */
3878 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3879 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3880 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3881 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3883 /* Intel platforms with MID UART */
3884 { PCI_VDEVICE(INTEL, 0x081b), },
3885 { PCI_VDEVICE(INTEL, 0x081c), },
3886 { PCI_VDEVICE(INTEL, 0x081d), },
3887 { PCI_VDEVICE(INTEL, 0x1191), },
3888 { PCI_VDEVICE(INTEL, 0x19d8), },
3892 * Given a complete unknown PCI device, try to use some heuristics to
3893 * guess what the configuration might be, based on the pitiful PCI
3894 * serial specs. Returns 0 on success, 1 on failure.
3897 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3899 const struct pci_device_id *bldev;
3900 int num_iomem, num_port, first_port = -1, i;
3903 * If it is not a communications device or the programming
3904 * interface is greater than 6, give up.
3906 * (Should we try to make guesses for multiport serial devices
3909 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3910 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3911 (dev->class & 0xff) > 6)
3915 * Do not access blacklisted devices that are known not to
3916 * feature serial ports or are handled by other modules.
3918 for (bldev = blacklist;
3919 bldev < blacklist + ARRAY_SIZE(blacklist);
3921 if (dev->vendor == bldev->vendor &&
3922 dev->device == bldev->device)
3926 num_iomem = num_port = 0;
3927 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3928 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3930 if (first_port == -1)
3933 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3938 * If there is 1 or 0 iomem regions, and exactly one port,
3939 * use it. We guess the number of ports based on the IO
3942 if (num_iomem <= 1 && num_port == 1) {
3943 board->flags = first_port;
3944 board->num_ports = pci_resource_len(dev, first_port) / 8;
3949 * Now guess if we've got a board which indexes by BARs.
3950 * Each IO BAR should be 8 bytes, and they should follow
3955 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3956 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3957 pci_resource_len(dev, i) == 8 &&
3958 (first_port == -1 || (first_port + num_port) == i)) {
3960 if (first_port == -1)
3966 board->flags = first_port | FL_BASE_BARS;
3967 board->num_ports = num_port;
3975 serial_pci_matches(const struct pciserial_board *board,
3976 const struct pciserial_board *guessed)
3979 board->num_ports == guessed->num_ports &&
3980 board->base_baud == guessed->base_baud &&
3981 board->uart_offset == guessed->uart_offset &&
3982 board->reg_shift == guessed->reg_shift &&
3983 board->first_offset == guessed->first_offset;
3986 struct serial_private *
3987 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3989 struct uart_8250_port uart;
3990 struct serial_private *priv;
3991 struct pci_serial_quirk *quirk;
3992 int rc, nr_ports, i;
3994 nr_ports = board->num_ports;
3997 * Find an init and setup quirks.
3999 quirk = find_quirk(dev);
4002 * Run the new-style initialization function.
4003 * The initialization function returns:
4005 * 0 - use board->num_ports
4006 * >0 - number of ports
4009 rc = quirk->init(dev);
4018 priv = kzalloc(sizeof(struct serial_private) +
4019 sizeof(unsigned int) * nr_ports,
4022 priv = ERR_PTR(-ENOMEM);
4027 priv->quirk = quirk;
4029 memset(&uart, 0, sizeof(uart));
4030 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4031 uart.port.uartclk = board->base_baud * 16;
4032 uart.port.irq = get_pci_irq(dev, board);
4033 uart.port.dev = &dev->dev;
4035 for (i = 0; i < nr_ports; i++) {
4036 if (quirk->setup(priv, board, &uart, i))
4039 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4040 uart.port.iobase, uart.port.irq, uart.port.iotype);
4042 priv->line[i] = serial8250_register_8250_port(&uart);
4043 if (priv->line[i] < 0) {
4045 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4046 uart.port.iobase, uart.port.irq,
4047 uart.port.iotype, priv->line[i]);
4060 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4062 void pciserial_remove_ports(struct serial_private *priv)
4064 struct pci_serial_quirk *quirk;
4067 for (i = 0; i < priv->nr; i++)
4068 serial8250_unregister_port(priv->line[i]);
4070 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4071 if (priv->remapped_bar[i])
4072 iounmap(priv->remapped_bar[i]);
4073 priv->remapped_bar[i] = NULL;
4077 * Find the exit quirks.
4079 quirk = find_quirk(priv->dev);
4081 quirk->exit(priv->dev);
4085 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4087 void pciserial_suspend_ports(struct serial_private *priv)
4091 for (i = 0; i < priv->nr; i++)
4092 if (priv->line[i] >= 0)
4093 serial8250_suspend_port(priv->line[i]);
4096 * Ensure that every init quirk is properly torn down
4098 if (priv->quirk->exit)
4099 priv->quirk->exit(priv->dev);
4101 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4103 void pciserial_resume_ports(struct serial_private *priv)
4108 * Ensure that the board is correctly configured.
4110 if (priv->quirk->init)
4111 priv->quirk->init(priv->dev);
4113 for (i = 0; i < priv->nr; i++)
4114 if (priv->line[i] >= 0)
4115 serial8250_resume_port(priv->line[i]);
4117 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4120 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4121 * to the arrangement of serial ports on a PCI card.
4124 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4126 struct pci_serial_quirk *quirk;
4127 struct serial_private *priv;
4128 const struct pciserial_board *board;
4129 struct pciserial_board tmp;
4132 quirk = find_quirk(dev);
4134 rc = quirk->probe(dev);
4139 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4140 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4145 board = &pci_boards[ent->driver_data];
4147 rc = pci_enable_device(dev);
4148 pci_save_state(dev);
4152 if (ent->driver_data == pbn_default) {
4154 * Use a copy of the pci_board entry for this;
4155 * avoid changing entries in the table.
4157 memcpy(&tmp, board, sizeof(struct pciserial_board));
4161 * We matched one of our class entries. Try to
4162 * determine the parameters of this board.
4164 rc = serial_pci_guess_board(dev, &tmp);
4169 * We matched an explicit entry. If we are able to
4170 * detect this boards settings with our heuristic,
4171 * then we no longer need this entry.
4173 memcpy(&tmp, &pci_boards[pbn_default],
4174 sizeof(struct pciserial_board));
4175 rc = serial_pci_guess_board(dev, &tmp);
4176 if (rc == 0 && serial_pci_matches(board, &tmp))
4177 moan_device("Redundant entry in serial pci_table.",
4181 priv = pciserial_init_ports(dev, board);
4182 if (!IS_ERR(priv)) {
4183 pci_set_drvdata(dev, priv);
4190 pci_disable_device(dev);
4194 static void pciserial_remove_one(struct pci_dev *dev)
4196 struct serial_private *priv = pci_get_drvdata(dev);
4198 pciserial_remove_ports(priv);
4200 pci_disable_device(dev);
4203 #ifdef CONFIG_PM_SLEEP
4204 static int pciserial_suspend_one(struct device *dev)
4206 struct pci_dev *pdev = to_pci_dev(dev);
4207 struct serial_private *priv = pci_get_drvdata(pdev);
4210 pciserial_suspend_ports(priv);
4215 static int pciserial_resume_one(struct device *dev)
4217 struct pci_dev *pdev = to_pci_dev(dev);
4218 struct serial_private *priv = pci_get_drvdata(pdev);
4223 * The device may have been disabled. Re-enable it.
4225 err = pci_enable_device(pdev);
4226 /* FIXME: We cannot simply error out here */
4228 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4229 pciserial_resume_ports(priv);
4235 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4236 pciserial_resume_one);
4238 static struct pci_device_id serial_pci_tbl[] = {
4239 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4240 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4241 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4243 /* Advantech also use 0x3618 and 0xf618 */
4244 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4245 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4247 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4248 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4250 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4251 PCI_SUBVENDOR_ID_CONNECT_TECH,
4252 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4254 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4255 PCI_SUBVENDOR_ID_CONNECT_TECH,
4256 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4258 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4259 PCI_SUBVENDOR_ID_CONNECT_TECH,
4260 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4262 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4263 PCI_SUBVENDOR_ID_CONNECT_TECH,
4264 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4266 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4267 PCI_SUBVENDOR_ID_CONNECT_TECH,
4268 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4270 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4271 PCI_SUBVENDOR_ID_CONNECT_TECH,
4272 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4274 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4275 PCI_SUBVENDOR_ID_CONNECT_TECH,
4276 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4278 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4279 PCI_SUBVENDOR_ID_CONNECT_TECH,
4280 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4282 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4283 PCI_SUBVENDOR_ID_CONNECT_TECH,
4284 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4286 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4287 PCI_SUBVENDOR_ID_CONNECT_TECH,
4288 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4290 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4291 PCI_SUBVENDOR_ID_CONNECT_TECH,
4292 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4294 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4295 PCI_SUBVENDOR_ID_CONNECT_TECH,
4296 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4298 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4299 PCI_SUBVENDOR_ID_CONNECT_TECH,
4300 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4302 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4303 PCI_SUBVENDOR_ID_CONNECT_TECH,
4304 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4306 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4307 PCI_SUBVENDOR_ID_CONNECT_TECH,
4308 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4310 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4311 PCI_SUBVENDOR_ID_CONNECT_TECH,
4312 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4314 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4315 PCI_SUBVENDOR_ID_CONNECT_TECH,
4316 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4318 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4319 PCI_VENDOR_ID_AFAVLAB,
4320 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4322 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4323 PCI_SUBVENDOR_ID_CONNECT_TECH,
4324 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4325 pbn_b0_2_1843200_200 },
4326 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4327 PCI_SUBVENDOR_ID_CONNECT_TECH,
4328 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4329 pbn_b0_4_1843200_200 },
4330 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4331 PCI_SUBVENDOR_ID_CONNECT_TECH,
4332 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4333 pbn_b0_8_1843200_200 },
4334 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4335 PCI_SUBVENDOR_ID_CONNECT_TECH,
4336 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4337 pbn_b0_2_1843200_200 },
4338 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4339 PCI_SUBVENDOR_ID_CONNECT_TECH,
4340 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4341 pbn_b0_4_1843200_200 },
4342 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4343 PCI_SUBVENDOR_ID_CONNECT_TECH,
4344 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4345 pbn_b0_8_1843200_200 },
4346 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4347 PCI_SUBVENDOR_ID_CONNECT_TECH,
4348 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4349 pbn_b0_2_1843200_200 },
4350 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4351 PCI_SUBVENDOR_ID_CONNECT_TECH,
4352 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4353 pbn_b0_4_1843200_200 },
4354 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4355 PCI_SUBVENDOR_ID_CONNECT_TECH,
4356 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4357 pbn_b0_8_1843200_200 },
4358 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4359 PCI_SUBVENDOR_ID_CONNECT_TECH,
4360 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4361 pbn_b0_2_1843200_200 },
4362 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4363 PCI_SUBVENDOR_ID_CONNECT_TECH,
4364 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4365 pbn_b0_4_1843200_200 },
4366 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4367 PCI_SUBVENDOR_ID_CONNECT_TECH,
4368 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4369 pbn_b0_8_1843200_200 },
4370 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4371 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4372 0, 0, pbn_exar_ibm_saturn },
4374 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4375 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4376 pbn_b2_bt_1_115200 },
4377 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4378 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4379 pbn_b2_bt_2_115200 },
4380 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4381 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4382 pbn_b2_bt_4_115200 },
4383 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4384 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4385 pbn_b2_bt_2_115200 },
4386 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4387 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4388 pbn_b2_bt_4_115200 },
4389 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4390 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4392 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4393 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4395 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4399 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4401 pbn_b2_bt_2_115200 },
4402 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4404 pbn_b2_bt_2_921600 },
4406 * VScom SPCOM800, from sl@s.pl
4408 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4411 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4414 /* Unknown card - subdevice 0x1584 */
4415 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4417 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4419 /* Unknown card - subdevice 0x1588 */
4420 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4422 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4424 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4425 PCI_SUBVENDOR_ID_KEYSPAN,
4426 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4428 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4431 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4435 PCI_VENDOR_ID_ESDGMBH,
4436 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4438 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4439 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4440 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4442 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4443 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4444 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4446 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4447 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4448 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4450 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4451 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4452 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4454 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4455 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4456 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4458 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4459 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4460 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4462 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4463 PCI_SUBVENDOR_ID_EXSYS,
4464 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4467 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4470 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4471 0x10b5, 0x106a, 0, 0,
4474 * EndRun Technologies. PCI express device range.
4475 * EndRun PTP/1588 has 2 Native UARTs.
4477 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4478 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4479 pbn_endrun_2_4000000 },
4481 * Quatech cards. These actually have configurable clocks but for
4482 * now we just use the default.
4484 * 100 series are RS232, 200 series RS422,
4486 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4489 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4492 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4495 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4498 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4501 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4504 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4517 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4519 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4522 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4526 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4528 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4531 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4534 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4537 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4540 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4545 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4548 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4549 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4552 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554 pbn_b0_bt_2_921600 },
4557 * The below card is a little controversial since it is the
4558 * subject of a PCI vendor/device ID clash. (See
4559 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4560 * For now just used the hex ID 0x950a.
4562 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4563 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4564 0, 0, pbn_b0_2_115200 },
4565 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4566 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4567 0, 0, pbn_b0_2_115200 },
4568 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4569 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4572 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4574 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4575 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4578 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4579 pbn_b0_bt_2_921600 },
4580 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4581 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4585 * Oxford Semiconductor Inc. Tornado PCI express device range.
4587 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_oxsemi_1_4000000 },
4596 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 pbn_oxsemi_1_4000000 },
4599 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_oxsemi_1_4000000 },
4608 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 pbn_oxsemi_1_4000000 },
4611 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625 pbn_oxsemi_2_4000000 },
4626 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628 pbn_oxsemi_2_4000000 },
4629 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631 pbn_oxsemi_4_4000000 },
4632 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634 pbn_oxsemi_4_4000000 },
4635 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 pbn_oxsemi_8_4000000 },
4638 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4640 pbn_oxsemi_8_4000000 },
4641 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643 pbn_oxsemi_1_4000000 },
4644 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646 pbn_oxsemi_1_4000000 },
4647 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649 pbn_oxsemi_1_4000000 },
4650 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652 pbn_oxsemi_1_4000000 },
4653 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655 pbn_oxsemi_1_4000000 },
4656 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658 pbn_oxsemi_1_4000000 },
4659 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661 pbn_oxsemi_1_4000000 },
4662 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4664 pbn_oxsemi_1_4000000 },
4665 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4666 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4667 pbn_oxsemi_1_4000000 },
4668 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4669 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4670 pbn_oxsemi_1_4000000 },
4671 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4673 pbn_oxsemi_1_4000000 },
4674 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4675 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4676 pbn_oxsemi_1_4000000 },
4677 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4678 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4679 pbn_oxsemi_1_4000000 },
4680 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4682 pbn_oxsemi_1_4000000 },
4683 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4685 pbn_oxsemi_1_4000000 },
4686 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4688 pbn_oxsemi_1_4000000 },
4689 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4691 pbn_oxsemi_1_4000000 },
4692 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4694 pbn_oxsemi_1_4000000 },
4695 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4697 pbn_oxsemi_1_4000000 },
4698 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4700 pbn_oxsemi_1_4000000 },
4701 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4703 pbn_oxsemi_1_4000000 },
4704 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4706 pbn_oxsemi_1_4000000 },
4707 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4709 pbn_oxsemi_1_4000000 },
4710 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4712 pbn_oxsemi_1_4000000 },
4713 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4715 pbn_oxsemi_1_4000000 },
4716 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4718 pbn_oxsemi_1_4000000 },
4720 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4722 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4723 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4724 pbn_oxsemi_1_4000000 },
4725 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4726 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4727 pbn_oxsemi_2_4000000 },
4728 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4729 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4730 pbn_oxsemi_4_4000000 },
4731 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4732 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4733 pbn_oxsemi_8_4000000 },
4736 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4738 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4739 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4740 pbn_oxsemi_2_4000000 },
4743 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4744 * from skokodyn@yahoo.com
4746 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4747 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4749 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4750 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4752 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4753 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4755 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4756 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4760 * Digitan DS560-558, from jimd@esoft.com
4762 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4767 * Titan Electronic cards
4768 * The 400L and 800L have a custom setup quirk.
4770 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4776 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4782 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4785 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787 pbn_b1_bt_2_921600 },
4788 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790 pbn_b0_bt_4_921600 },
4791 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793 pbn_b0_bt_8_921600 },
4794 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796 pbn_b4_bt_2_921600 },
4797 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799 pbn_b4_bt_4_921600 },
4800 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4802 pbn_b4_bt_8_921600 },
4803 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4806 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4809 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4812 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814 pbn_oxsemi_1_4000000 },
4815 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4816 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4817 pbn_oxsemi_2_4000000 },
4818 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4819 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4820 pbn_oxsemi_4_4000000 },
4821 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4822 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4823 pbn_oxsemi_8_4000000 },
4824 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4825 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4826 pbn_oxsemi_2_4000000 },
4827 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4828 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4829 pbn_oxsemi_2_4000000 },
4830 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4832 pbn_b0_bt_2_921600 },
4833 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4834 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4836 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4837 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4839 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4840 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4842 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4843 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4846 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4849 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4852 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4855 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4856 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4857 pbn_b2_bt_2_921600 },
4858 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4859 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4860 pbn_b2_bt_2_921600 },
4861 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4862 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4863 pbn_b2_bt_2_921600 },
4864 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4865 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4866 pbn_b2_bt_4_921600 },
4867 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4868 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4869 pbn_b2_bt_4_921600 },
4870 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4871 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4872 pbn_b2_bt_4_921600 },
4873 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4874 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4876 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4877 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4879 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4880 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4882 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4884 pbn_b0_bt_2_921600 },
4885 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4887 pbn_b0_bt_2_921600 },
4888 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4890 pbn_b0_bt_2_921600 },
4891 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4893 pbn_b0_bt_4_921600 },
4894 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4896 pbn_b0_bt_4_921600 },
4897 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4899 pbn_b0_bt_4_921600 },
4900 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4902 pbn_b0_bt_8_921600 },
4903 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4905 pbn_b0_bt_8_921600 },
4906 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908 pbn_b0_bt_8_921600 },
4911 * Computone devices submitted by Doug McNash dmcnash@computone.com
4913 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4914 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4915 0, 0, pbn_computone_4 },
4916 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4917 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4918 0, 0, pbn_computone_8 },
4919 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4920 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4921 0, 0, pbn_computone_6 },
4923 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4926 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4927 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4928 pbn_b0_bt_1_921600 },
4933 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4934 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4935 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4936 pbn_b0_bt_1_921600 },
4938 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4939 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4940 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4941 pbn_b0_bt_1_921600 },
4944 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4946 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4948 pbn_b0_bt_8_115200 },
4949 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4951 pbn_b0_bt_8_115200 },
4953 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4955 pbn_b0_bt_2_115200 },
4956 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4958 pbn_b0_bt_2_115200 },
4959 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4961 pbn_b0_bt_2_115200 },
4962 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4964 pbn_b0_bt_2_115200 },
4965 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4967 pbn_b0_bt_2_115200 },
4968 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4970 pbn_b0_bt_4_460800 },
4971 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4973 pbn_b0_bt_4_460800 },
4974 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4976 pbn_b0_bt_2_460800 },
4977 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4979 pbn_b0_bt_2_460800 },
4980 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4982 pbn_b0_bt_2_460800 },
4983 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4985 pbn_b0_bt_1_115200 },
4986 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4988 pbn_b0_bt_1_460800 },
4991 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4992 * Cards are identified by their subsystem vendor IDs, which
4993 * (in hex) match the model number.
4995 * Note that JC140x are RS422/485 cards which require ox950
4996 * ACR = 0x10, and as such are not currently fully supported.
4998 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4999 0x1204, 0x0004, 0, 0,
5001 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5002 0x1208, 0x0004, 0, 0,
5004 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5005 0x1402, 0x0002, 0, 0,
5006 pbn_b0_2_921600 }, */
5007 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5008 0x1404, 0x0004, 0, 0,
5009 pbn_b0_4_921600 }, */
5010 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5011 0x1208, 0x0004, 0, 0,
5014 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5015 0x1204, 0x0004, 0, 0,
5017 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5018 0x1208, 0x0004, 0, 0,
5020 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5021 0x1208, 0x0004, 0, 0,
5024 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5026 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5031 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5033 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5034 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5038 * RAStel 2 port modem, gerg@moreton.com.au
5040 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5041 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5042 pbn_b2_bt_2_115200 },
5045 * EKF addition for i960 Boards form EKF with serial port
5047 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5048 0xE4BF, PCI_ANY_ID, 0, 0,
5052 * Xircom Cardbus/Ethernet combos
5054 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5058 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5060 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5065 * Untested PCI modems, sent in from various folks...
5069 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5071 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5072 0x1048, 0x1500, 0, 0,
5075 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5082 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5083 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5085 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5086 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5088 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5089 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5092 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5095 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5098 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5103 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5105 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5106 PCI_ANY_ID, PCI_ANY_ID,
5108 0, pbn_exar_XR17C152 },
5109 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5110 PCI_ANY_ID, PCI_ANY_ID,
5112 0, pbn_exar_XR17C154 },
5113 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5114 PCI_ANY_ID, PCI_ANY_ID,
5116 0, pbn_exar_XR17C158 },
5118 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5120 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5121 PCI_ANY_ID, PCI_ANY_ID,
5123 0, pbn_exar_XR17V352 },
5124 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5125 PCI_ANY_ID, PCI_ANY_ID,
5127 0, pbn_exar_XR17V354 },
5128 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5129 PCI_ANY_ID, PCI_ANY_ID,
5131 0, pbn_exar_XR17V358 },
5132 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5133 PCI_ANY_ID, PCI_ANY_ID,
5135 0, pbn_exar_XR17V4358 },
5136 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5137 PCI_ANY_ID, PCI_ANY_ID,
5139 0, pbn_exar_XR17V8358 },
5141 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5143 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5144 PCI_ANY_ID, PCI_ANY_ID,
5146 0, pbn_pericom_PI7C9X7951 },
5147 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5148 PCI_ANY_ID, PCI_ANY_ID,
5150 0, pbn_pericom_PI7C9X7952 },
5151 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5152 PCI_ANY_ID, PCI_ANY_ID,
5154 0, pbn_pericom_PI7C9X7954 },
5155 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5156 PCI_ANY_ID, PCI_ANY_ID,
5158 0, pbn_pericom_PI7C9X7958 },
5160 * ACCES I/O Products quad
5162 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
5163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5164 pbn_pericom_PI7C9X7954 },
5165 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
5166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5167 pbn_pericom_PI7C9X7954 },
5168 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
5169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5170 pbn_pericom_PI7C9X7954 },
5171 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
5172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5173 pbn_pericom_PI7C9X7954 },
5174 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
5175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5176 pbn_pericom_PI7C9X7954 },
5177 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
5178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5179 pbn_pericom_PI7C9X7954 },
5180 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
5181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5182 pbn_pericom_PI7C9X7954 },
5183 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
5184 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5185 pbn_pericom_PI7C9X7954 },
5186 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
5187 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5188 pbn_pericom_PI7C9X7954 },
5189 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
5190 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5191 pbn_pericom_PI7C9X7954 },
5192 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
5193 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5194 pbn_pericom_PI7C9X7954 },
5195 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
5196 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5197 pbn_pericom_PI7C9X7954 },
5198 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
5199 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5200 pbn_pericom_PI7C9X7954 },
5201 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
5202 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5203 pbn_pericom_PI7C9X7954 },
5204 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
5205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5206 pbn_pericom_PI7C9X7954 },
5207 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
5208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5209 pbn_pericom_PI7C9X7954 },
5210 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
5211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5212 pbn_pericom_PI7C9X7954 },
5213 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
5214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5215 pbn_pericom_PI7C9X7954 },
5216 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
5217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5218 pbn_pericom_PI7C9X7954 },
5219 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
5220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5221 pbn_pericom_PI7C9X7954 },
5222 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
5223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5224 pbn_pericom_PI7C9X7954 },
5225 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
5226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5227 pbn_pericom_PI7C9X7954 },
5228 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
5229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5230 pbn_pericom_PI7C9X7954 },
5231 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
5232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5233 pbn_pericom_PI7C9X7954 },
5234 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
5235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5236 pbn_pericom_PI7C9X7958 },
5237 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
5238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5239 pbn_pericom_PI7C9X7958 },
5240 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
5241 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5242 pbn_pericom_PI7C9X7958 },
5243 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
5244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5245 pbn_pericom_PI7C9X7958 },
5246 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
5247 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5248 pbn_pericom_PI7C9X7958 },
5249 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
5250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5251 pbn_pericom_PI7C9X7958 },
5252 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
5253 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5254 pbn_pericom_PI7C9X7958 },
5255 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
5256 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5257 pbn_pericom_PI7C9X7958 },
5258 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
5259 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5260 pbn_pericom_PI7C9X7958 },
5262 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5264 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5265 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5270 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5271 PCI_ANY_ID, PCI_ANY_ID,
5273 pbn_b1_bt_1_115200 },
5278 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5279 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5284 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5285 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5288 * Perle PCI-RAS cards
5290 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5291 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5292 0, 0, pbn_b2_4_921600 },
5293 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5294 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5295 0, 0, pbn_b2_8_921600 },
5298 * Mainpine series cards: Fairly standard layout but fools
5299 * parts of the autodetect in some cases and uses otherwise
5300 * unmatched communications subclasses in the PCI Express case
5303 { /* RockForceDUO */
5304 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5305 PCI_VENDOR_ID_MAINPINE, 0x0200,
5306 0, 0, pbn_b0_2_115200 },
5307 { /* RockForceQUATRO */
5308 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5309 PCI_VENDOR_ID_MAINPINE, 0x0300,
5310 0, 0, pbn_b0_4_115200 },
5311 { /* RockForceDUO+ */
5312 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5313 PCI_VENDOR_ID_MAINPINE, 0x0400,
5314 0, 0, pbn_b0_2_115200 },
5315 { /* RockForceQUATRO+ */
5316 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5317 PCI_VENDOR_ID_MAINPINE, 0x0500,
5318 0, 0, pbn_b0_4_115200 },
5320 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5321 PCI_VENDOR_ID_MAINPINE, 0x0600,
5322 0, 0, pbn_b0_2_115200 },
5324 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5325 PCI_VENDOR_ID_MAINPINE, 0x0700,
5326 0, 0, pbn_b0_4_115200 },
5327 { /* RockForceOCTO+ */
5328 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5329 PCI_VENDOR_ID_MAINPINE, 0x0800,
5330 0, 0, pbn_b0_8_115200 },
5331 { /* RockForceDUO+ */
5332 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5333 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5334 0, 0, pbn_b0_2_115200 },
5335 { /* RockForceQUARTRO+ */
5336 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5337 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5338 0, 0, pbn_b0_4_115200 },
5339 { /* RockForceOCTO+ */
5340 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5341 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5342 0, 0, pbn_b0_8_115200 },
5344 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5345 PCI_VENDOR_ID_MAINPINE, 0x2000,
5346 0, 0, pbn_b0_1_115200 },
5348 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5349 PCI_VENDOR_ID_MAINPINE, 0x2100,
5350 0, 0, pbn_b0_1_115200 },
5352 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5353 PCI_VENDOR_ID_MAINPINE, 0x2200,
5354 0, 0, pbn_b0_2_115200 },
5356 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5357 PCI_VENDOR_ID_MAINPINE, 0x2300,
5358 0, 0, pbn_b0_2_115200 },
5360 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5361 PCI_VENDOR_ID_MAINPINE, 0x2400,
5362 0, 0, pbn_b0_4_115200 },
5364 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5365 PCI_VENDOR_ID_MAINPINE, 0x2500,
5366 0, 0, pbn_b0_4_115200 },
5368 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5369 PCI_VENDOR_ID_MAINPINE, 0x2600,
5370 0, 0, pbn_b0_8_115200 },
5372 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5373 PCI_VENDOR_ID_MAINPINE, 0x2700,
5374 0, 0, pbn_b0_8_115200 },
5375 { /* IQ Express D1 */
5376 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5377 PCI_VENDOR_ID_MAINPINE, 0x3000,
5378 0, 0, pbn_b0_1_115200 },
5379 { /* IQ Express F1 */
5380 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5381 PCI_VENDOR_ID_MAINPINE, 0x3100,
5382 0, 0, pbn_b0_1_115200 },
5383 { /* IQ Express D2 */
5384 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5385 PCI_VENDOR_ID_MAINPINE, 0x3200,
5386 0, 0, pbn_b0_2_115200 },
5387 { /* IQ Express F2 */
5388 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5389 PCI_VENDOR_ID_MAINPINE, 0x3300,
5390 0, 0, pbn_b0_2_115200 },
5391 { /* IQ Express D4 */
5392 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5393 PCI_VENDOR_ID_MAINPINE, 0x3400,
5394 0, 0, pbn_b0_4_115200 },
5395 { /* IQ Express F4 */
5396 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5397 PCI_VENDOR_ID_MAINPINE, 0x3500,
5398 0, 0, pbn_b0_4_115200 },
5399 { /* IQ Express D8 */
5400 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5401 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5402 0, 0, pbn_b0_8_115200 },
5403 { /* IQ Express F8 */
5404 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5405 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5406 0, 0, pbn_b0_8_115200 },
5410 * PA Semi PA6T-1682M on-chip UART
5412 { PCI_VENDOR_ID_PASEMI, 0xa004,
5413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5417 * National Instruments
5419 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5422 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5425 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5427 pbn_b1_bt_4_115200 },
5428 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5430 pbn_b1_bt_2_115200 },
5431 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5433 pbn_b1_bt_4_115200 },
5434 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5436 pbn_b1_bt_2_115200 },
5437 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5440 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5443 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5445 pbn_b1_bt_4_115200 },
5446 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5448 pbn_b1_bt_2_115200 },
5449 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5451 pbn_b1_bt_4_115200 },
5452 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5454 pbn_b1_bt_2_115200 },
5455 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5458 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5461 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5464 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5467 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5470 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5473 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5476 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5479 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5482 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5485 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5488 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5493 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5495 { PCI_VENDOR_ID_ADDIDATA,
5496 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5503 { PCI_VENDOR_ID_ADDIDATA,
5504 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5511 { PCI_VENDOR_ID_ADDIDATA,
5512 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5519 { PCI_VENDOR_ID_AMCC,
5520 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5527 { PCI_VENDOR_ID_ADDIDATA,
5528 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5535 { PCI_VENDOR_ID_ADDIDATA,
5536 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5543 { PCI_VENDOR_ID_ADDIDATA,
5544 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5551 { PCI_VENDOR_ID_ADDIDATA,
5552 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5559 { PCI_VENDOR_ID_ADDIDATA,
5560 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5567 { PCI_VENDOR_ID_ADDIDATA,
5568 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5575 { PCI_VENDOR_ID_ADDIDATA,
5576 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5583 { PCI_VENDOR_ID_ADDIDATA,
5584 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5589 pbn_ADDIDATA_PCIe_4_3906250 },
5591 { PCI_VENDOR_ID_ADDIDATA,
5592 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5597 pbn_ADDIDATA_PCIe_2_3906250 },
5599 { PCI_VENDOR_ID_ADDIDATA,
5600 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5605 pbn_ADDIDATA_PCIe_1_3906250 },
5607 { PCI_VENDOR_ID_ADDIDATA,
5608 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5613 pbn_ADDIDATA_PCIe_8_3906250 },
5615 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5616 PCI_VENDOR_ID_IBM, 0x0299,
5617 0, 0, pbn_b0_bt_2_115200 },
5620 * other NetMos 9835 devices are most likely handled by the
5621 * parport_serial driver, check drivers/parport/parport_serial.c
5622 * before adding them here.
5625 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5627 0, 0, pbn_b0_1_115200 },
5629 /* the 9901 is a rebranded 9912 */
5630 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5632 0, 0, pbn_b0_1_115200 },
5634 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5636 0, 0, pbn_b0_1_115200 },
5638 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5640 0, 0, pbn_b0_1_115200 },
5642 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5644 0, 0, pbn_b0_1_115200 },
5646 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5648 0, 0, pbn_NETMOS9900_2s_115200 },
5651 * Best Connectivity and Rosewill PCI Multi I/O cards
5654 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5656 0, 0, pbn_b0_1_115200 },
5658 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5660 0, 0, pbn_b0_bt_2_115200 },
5662 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5664 0, 0, pbn_b0_bt_4_115200 },
5666 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5667 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5668 pbn_ce4100_1_115200 },
5669 /* Intel BayTrail */
5670 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5671 PCI_ANY_ID, PCI_ANY_ID,
5672 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5674 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5675 PCI_ANY_ID, PCI_ANY_ID,
5676 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5678 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5679 PCI_ANY_ID, PCI_ANY_ID,
5680 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5682 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5683 PCI_ANY_ID, PCI_ANY_ID,
5684 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5687 /* Intel Broadwell */
5688 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1,
5689 PCI_ANY_ID, PCI_ANY_ID,
5690 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5692 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2,
5693 PCI_ANY_ID, PCI_ANY_ID,
5694 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5700 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5706 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5711 * Broadcom TruManage
5713 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5715 pbn_brcm_trumanage },
5718 * AgeStar as-prs2-009
5720 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5721 PCI_ANY_ID, PCI_ANY_ID,
5722 0, 0, pbn_b0_bt_2_115200 },
5725 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5726 * so not listed here.
5728 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5729 PCI_ANY_ID, PCI_ANY_ID,
5730 0, 0, pbn_b0_bt_4_115200 },
5732 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5733 PCI_ANY_ID, PCI_ANY_ID,
5734 0, 0, pbn_b0_bt_2_115200 },
5736 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5737 PCI_ANY_ID, PCI_ANY_ID,
5738 0, 0, pbn_wch382_2 },
5740 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5741 PCI_ANY_ID, PCI_ANY_ID,
5742 0, 0, pbn_wch384_4 },
5745 * Commtech, Inc. Fastcom adapters
5747 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5748 PCI_ANY_ID, PCI_ANY_ID,
5750 0, pbn_b0_2_1152000_200 },
5751 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5752 PCI_ANY_ID, PCI_ANY_ID,
5754 0, pbn_b0_4_1152000_200 },
5755 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5756 PCI_ANY_ID, PCI_ANY_ID,
5758 0, pbn_b0_4_1152000_200 },
5759 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5760 PCI_ANY_ID, PCI_ANY_ID,
5762 0, pbn_b0_8_1152000_200 },
5763 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5764 PCI_ANY_ID, PCI_ANY_ID,
5766 0, pbn_exar_XR17V352 },
5767 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5768 PCI_ANY_ID, PCI_ANY_ID,
5770 0, pbn_exar_XR17V354 },
5771 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5772 PCI_ANY_ID, PCI_ANY_ID,
5774 0, pbn_exar_XR17V358 },
5776 /* Fintek PCI serial cards */
5777 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5778 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5779 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5782 * These entries match devices with class COMMUNICATION_SERIAL,
5783 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5785 { PCI_ANY_ID, PCI_ANY_ID,
5786 PCI_ANY_ID, PCI_ANY_ID,
5787 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5788 0xffff00, pbn_default },
5789 { PCI_ANY_ID, PCI_ANY_ID,
5790 PCI_ANY_ID, PCI_ANY_ID,
5791 PCI_CLASS_COMMUNICATION_MODEM << 8,
5792 0xffff00, pbn_default },
5793 { PCI_ANY_ID, PCI_ANY_ID,
5794 PCI_ANY_ID, PCI_ANY_ID,
5795 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5796 0xffff00, pbn_default },
5800 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5801 pci_channel_state_t state)
5803 struct serial_private *priv = pci_get_drvdata(dev);
5805 if (state == pci_channel_io_perm_failure)
5806 return PCI_ERS_RESULT_DISCONNECT;
5809 pciserial_suspend_ports(priv);
5811 pci_disable_device(dev);
5813 return PCI_ERS_RESULT_NEED_RESET;
5816 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5820 rc = pci_enable_device(dev);
5823 return PCI_ERS_RESULT_DISCONNECT;
5825 pci_restore_state(dev);
5826 pci_save_state(dev);
5828 return PCI_ERS_RESULT_RECOVERED;
5831 static void serial8250_io_resume(struct pci_dev *dev)
5833 struct serial_private *priv = pci_get_drvdata(dev);
5836 pciserial_resume_ports(priv);
5839 static const struct pci_error_handlers serial8250_err_handler = {
5840 .error_detected = serial8250_io_error_detected,
5841 .slot_reset = serial8250_io_slot_reset,
5842 .resume = serial8250_io_resume,
5845 static struct pci_driver serial_pci_driver = {
5847 .probe = pciserial_init_one,
5848 .remove = pciserial_remove_one,
5850 .pm = &pciserial_pm_ops,
5852 .id_table = serial_pci_tbl,
5853 .err_handler = &serial8250_err_handler,
5856 module_pci_driver(serial_pci_driver);
5858 MODULE_LICENSE("GPL");
5859 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5860 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);