1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 ******************************************************************************/
15 #define _HCI_HAL_INIT_C_
17 #include <osdep_service.h>
18 #include <drv_types.h>
19 #include <rtw_efuse.h>
21 #include <HalPwrSeqCmd.h>
22 #include <Hal8723PwrSeq.h>
23 #include <rtl8723a_hal.h>
24 #include <linux/ieee80211.h>
28 static void phy_SsPwrSwitch92CU(struct rtw_adapter *Adapter,
29 enum rt_rf_power_state eRFPowerState);
32 _ConfigChipOutEP(struct rtw_adapter *pAdapter, u8 NumOutPipe)
35 struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
37 pHalData->OutEpQueueSel = 0;
38 pHalData->OutEpNumber = 0;
40 /* Normal and High queue */
41 value8 = rtl8723au_read8(pAdapter, (REG_NORMAL_SIE_EP + 1));
43 if (value8 & USB_NORMAL_SIE_EP_MASK) {
44 pHalData->OutEpQueueSel |= TX_SELE_HQ;
45 pHalData->OutEpNumber++;
48 if ((value8 >> USB_NORMAL_SIE_EP_SHIFT) & USB_NORMAL_SIE_EP_MASK) {
49 pHalData->OutEpQueueSel |= TX_SELE_NQ;
50 pHalData->OutEpNumber++;
54 value8 = rtl8723au_read8(pAdapter, (REG_NORMAL_SIE_EP + 2));
55 if (value8 & USB_NORMAL_SIE_EP_MASK) {
56 pHalData->OutEpQueueSel |= TX_SELE_LQ;
57 pHalData->OutEpNumber++;
60 /* TODO: Error recovery for this case */
61 /* RT_ASSERT((NumOutPipe == pHalData->OutEpNumber),
62 ("Out EP number isn't match! %d(Descriptor) != %d (SIE reg)\n",
63 (u32)NumOutPipe, (u32)pHalData->OutEpNumber)); */
66 bool rtl8723au_chip_configure(struct rtw_adapter *padapter)
68 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
69 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
70 u8 NumInPipe = pdvobjpriv->RtNumInPipes;
71 u8 NumOutPipe = pdvobjpriv->RtNumOutPipes;
73 _ConfigChipOutEP(padapter, NumOutPipe);
75 /* Normal chip with one IN and one OUT doesn't have interrupt IN EP. */
76 if (pHalData->OutEpNumber == 1) {
81 return Hal_MappingOutPipe23a(padapter, NumOutPipe);
84 static int _InitPowerOn(struct rtw_adapter *padapter)
89 /* RSV_CTRL 0x1C[7:0] = 0x00
90 unlock ISO/CLK/Power control register */
91 rtl8723au_write8(padapter, REG_RSV_CTRL, 0x0);
93 /* HW Power on sequence */
94 if (!HalPwrSeqCmdParsing23a(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
95 PWR_INTF_USB_MSK, rtl8723AU_card_enable_flow))
98 /* 0x04[19] = 1, suggest by Jackie 2011.05.09, reset 8051 */
99 value8 = rtl8723au_read8(padapter, REG_APS_FSMCO+2);
100 rtl8723au_write8(padapter, REG_APS_FSMCO + 2, value8 | BIT(3));
102 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
103 /* Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy.
104 Added by tynli. 2011.08.31. */
105 value16 = rtl8723au_read16(padapter, REG_CR);
106 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
107 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN |
109 rtl8723au_write16(padapter, REG_CR, value16);
111 /* for Efuse PG, suggest by Jackie 2011.11.23 */
112 PHY_SetBBReg(padapter, REG_EFUSE_CTRL, BIT(28)|BIT(29)|BIT(30), 0x06);
117 /* Shall USB interface init this? */
118 static void _InitInterrupt(struct rtw_adapter *Adapter)
122 /* HISR - turn all on */
123 value32 = 0xFFFFFFFF;
124 rtl8723au_write32(Adapter, REG_HISR, value32);
126 /* HIMR - turn all on */
127 rtl8723au_write32(Adapter, REG_HIMR, value32);
130 static void _InitQueueReservedPage(struct rtw_adapter *Adapter)
132 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
133 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
140 bool bWiFiConfig = pregistrypriv->wifi_spec;
142 /* RT_ASSERT((outEPNum>= 2), ("for WMM , number of out-ep "
143 "must more than or equal to 2!\n")); */
145 numPubQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_PUBQ : NORMAL_PAGE_NUM_PUBQ;
147 if (pHalData->OutEpQueueSel & TX_SELE_HQ) {
148 numHQ = bWiFiConfig ?
149 WMM_NORMAL_PAGE_NUM_HPQ : NORMAL_PAGE_NUM_HPQ;
152 if (pHalData->OutEpQueueSel & TX_SELE_LQ) {
153 numLQ = bWiFiConfig ?
154 WMM_NORMAL_PAGE_NUM_LPQ : NORMAL_PAGE_NUM_LPQ;
156 /* NOTE: This step shall be proceed before
157 writting REG_RQPN. */
158 if (pHalData->OutEpQueueSel & TX_SELE_NQ) {
159 numNQ = bWiFiConfig ?
160 WMM_NORMAL_PAGE_NUM_NPQ : NORMAL_PAGE_NUM_NPQ;
162 value8 = (u8)_NPQ(numNQ);
163 rtl8723au_write8(Adapter, REG_RQPN_NPQ, value8);
166 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
167 rtl8723au_write32(Adapter, REG_RQPN, value32);
170 static void _InitTxBufferBoundary(struct rtw_adapter *Adapter)
172 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
176 if (!pregistrypriv->wifi_spec)
177 txpktbuf_bndy = TX_PAGE_BOUNDARY;
179 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY;
181 rtl8723au_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
182 rtl8723au_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
183 rtl8723au_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
184 rtl8723au_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
185 rtl8723au_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
188 static void _InitPageBoundary(struct rtw_adapter *Adapter)
190 /* RX Page Boundary */
191 /* srand(static_cast<unsigned int>(time(NULL))); */
192 u16 rxff_bndy = 0x27FF;/* rand() % 1) ? 0x27FF : 0x23FF; */
194 rtl8723au_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
196 /* TODO: ?? shall we set tx boundary? */
200 _InitNormalChipRegPriority(struct rtw_adapter *Adapter, u16 beQ, u16 bkQ,
201 u16 viQ, u16 voQ, u16 mgtQ, u16 hiQ)
203 u16 value16 = rtl8723au_read16(Adapter, REG_TRXDMA_CTRL) & 0x7;
205 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
206 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
207 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
209 rtl8723au_write16(Adapter, REG_TRXDMA_CTRL, value16);
212 static void _InitNormalChipOneOutEpPriority(struct rtw_adapter *Adapter)
214 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
217 switch (pHalData->OutEpQueueSel) {
225 value = QUEUE_NORMAL;
228 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
232 _InitNormalChipRegPriority(Adapter, value, value, value,
233 value, value, value);
236 static void _InitNormalChipTwoOutEpPriority(struct rtw_adapter *Adapter)
238 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
239 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
240 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
244 switch (pHalData->OutEpQueueSel) {
245 case (TX_SELE_HQ | TX_SELE_LQ):
246 valueHi = QUEUE_HIGH;
247 valueLow = QUEUE_LOW;
249 case (TX_SELE_NQ | TX_SELE_LQ):
250 valueHi = QUEUE_NORMAL;
251 valueLow = QUEUE_LOW;
253 case (TX_SELE_HQ | TX_SELE_NQ):
254 valueHi = QUEUE_HIGH;
255 valueLow = QUEUE_NORMAL;
258 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
262 if (!pregistrypriv->wifi_spec) {
269 } else {/* for WMM , CONFIG_OUT_EP_WIFI_MODE */
278 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
281 static void _InitNormalChipThreeOutEpPriority(struct rtw_adapter *Adapter)
283 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
284 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
286 if (!pregistrypriv->wifi_spec) {/* typical setting */
293 } else {/* for WMM */
301 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
304 static void _InitQueuePriority(struct rtw_adapter *Adapter)
306 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
308 switch (pHalData->OutEpNumber) {
310 _InitNormalChipOneOutEpPriority(Adapter);
313 _InitNormalChipTwoOutEpPriority(Adapter);
316 _InitNormalChipThreeOutEpPriority(Adapter);
319 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
324 static void _InitTransferPageSize(struct rtw_adapter *Adapter)
326 /* Tx page size is always 128. */
329 value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
330 rtl8723au_write8(Adapter, REG_PBP, value8);
333 static void _InitDriverInfoSize(struct rtw_adapter *Adapter, u8 drvInfoSize)
335 rtl8723au_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
338 static void _InitWMACSetting(struct rtw_adapter *Adapter)
340 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
342 /* don't turn on AAP, it will allow all packets to driver */
343 pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB | RCR_CBSSID_DATA |
344 RCR_CBSSID_BCN | RCR_APP_ICV | RCR_AMF |
345 RCR_HTC_LOC_CTRL | RCR_APP_MIC |
348 /* some REG_RCR will be modified later by
349 phy_ConfigMACWithHeaderFile() */
350 rtl8723au_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
352 /* Accept all multicast address */
353 rtl8723au_write32(Adapter, REG_MAR, 0xFFFFFFFF);
354 rtl8723au_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
356 /* Accept all data frames */
357 /* value16 = 0xFFFF; */
358 /* rtl8723au_write16(Adapter, REG_RXFLTMAP2, value16); */
360 /* 2010.09.08 hpfan */
361 /* Since ADF is removed from RCR, ps-poll will not be indicate
363 /* RxFilterMap should mask ps-poll to gurantee AP mode can
365 /* value16 = 0x400; */
366 /* rtl8723au_write16(Adapter, REG_RXFLTMAP1, value16); */
368 /* Accept all management frames */
369 /* value16 = 0xFFFF; */
370 /* rtl8723au_write16(Adapter, REG_RXFLTMAP0, value16); */
372 /* enable RX_SHIFT bits */
373 /* rtl8723au_write8(Adapter, REG_TRXDMA_CTRL, rtl8723au_read8(Adapter,
374 REG_TRXDMA_CTRL)|BIT(1)); */
377 static void _InitAdaptiveCtrl(struct rtw_adapter *Adapter)
382 /* Response Rate Set */
383 value32 = rtl8723au_read32(Adapter, REG_RRSR);
384 value32 &= ~RATE_BITMAP_ALL;
385 value32 |= RATE_RRSR_CCK_ONLY_1M;
386 rtl8723au_write32(Adapter, REG_RRSR, value32);
388 /* CF-END Threshold */
389 /* m_spIoBase->rtl8723au_write8(REG_CFEND_TH, 0x1); */
391 /* SIFS (used in NAV) */
392 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
393 rtl8723au_write16(Adapter, REG_SPEC_SIFS, value16);
396 value16 = _LRL(0x30) | _SRL(0x30);
397 rtl8723au_write16(Adapter, REG_RL, value16);
400 static void _InitRateFallback(struct rtw_adapter *Adapter)
402 /* Set Data Auto Rate Fallback Retry Count register. */
403 rtl8723au_write32(Adapter, REG_DARFRC, 0x00000000);
404 rtl8723au_write32(Adapter, REG_DARFRC+4, 0x10080404);
405 rtl8723au_write32(Adapter, REG_RARFRC, 0x04030201);
406 rtl8723au_write32(Adapter, REG_RARFRC+4, 0x08070605);
409 static void _InitEDCA(struct rtw_adapter *Adapter)
411 /* Set Spec SIFS (used in NAV) */
412 rtl8723au_write16(Adapter, REG_SPEC_SIFS, 0x100a);
413 rtl8723au_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
415 /* Set SIFS for CCK */
416 rtl8723au_write16(Adapter, REG_SIFS_CTX, 0x100a);
418 /* Set SIFS for OFDM */
419 rtl8723au_write16(Adapter, REG_SIFS_TRX, 0x100a);
422 rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
423 rtl8723au_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
424 rtl8723au_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
425 rtl8723au_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
428 static void _InitRDGSetting(struct rtw_adapter *Adapter)
430 rtl8723au_write8(Adapter, REG_RD_CTRL, 0xFF);
431 rtl8723au_write16(Adapter, REG_RD_NAV_NXT, 0x200);
432 rtl8723au_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05);
435 static void _InitRetryFunction(struct rtw_adapter *Adapter)
439 value8 = rtl8723au_read8(Adapter, REG_FWHW_TXQ_CTRL);
440 value8 |= EN_AMPDU_RTY_NEW;
441 rtl8723au_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
443 /* Set ACK timeout */
444 rtl8723au_write8(Adapter, REG_ACKTO, 0x40);
447 static void _InitRFType(struct rtw_adapter *Adapter)
449 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
451 pHalData->rf_type = RF_1T1R;
454 /* Set CCK and OFDM Block "ON" */
455 static void _BBTurnOnBlock(struct rtw_adapter *Adapter)
457 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
458 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
461 #define MgntActSet_RF_State(...)
462 static void _RfPowerSave(struct rtw_adapter *padapter)
471 enum rt_rf_power_state RfOnOffDetect23a(struct rtw_adapter *pAdapter)
473 /* struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter); */
475 enum rt_rf_power_state rfpowerstate = rf_off;
477 rtl8723au_write8(pAdapter, REG_MAC_PINMUX_CFG,
478 rtl8723au_read8(pAdapter,
479 REG_MAC_PINMUX_CFG) & ~BIT(3));
480 val8 = rtl8723au_read8(pAdapter, REG_GPIO_IO_SEL);
481 DBG_8723A("GPIO_IN =%02x\n", val8);
482 rfpowerstate = (val8 & BIT(3)) ? rf_on : rf_off;
487 int rtl8723au_hal_init(struct rtw_adapter *Adapter)
489 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
490 struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
491 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
494 int status = _SUCCESS;
497 unsigned long init_start_time = jiffies;
499 Adapter->hw_init_completed = false;
501 if (Adapter->pwrctrlpriv.bkeepfwalive) {
502 phy_SsPwrSwitch92CU(Adapter, rf_on);
504 if (pHalData->bIQKInitialized) {
505 rtl8723a_phy_iq_calibrate(Adapter, true);
507 rtl8723a_phy_iq_calibrate(Adapter, false);
508 pHalData->bIQKInitialized = true;
510 rtl8723a_odm_check_tx_power_tracking(Adapter);
511 rtl8723a_phy_lc_calibrate(Adapter);
516 /* Check if MAC has already power on. by tynli. 2011.05.27. */
517 val8 = rtl8723au_read8(Adapter, REG_CR);
518 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
519 "%s: REG_CR 0x100 = 0x%02x\n", __func__, val8);
520 /* Fix 92DU-VC S3 hang with the reason is that secondary mac is not
522 /* 0x100 value of first mac is 0xEA while 0x100 value of secondary
528 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
529 "%s: MAC has already power on\n", __func__);
532 status = _InitPowerOn(Adapter);
533 if (status == _FAIL) {
534 RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
535 "Failed to init power on!\n");
539 if (!pregistrypriv->wifi_spec) {
540 boundary = TX_PAGE_BOUNDARY;
543 boundary = WMM_NORMAL_TX_PAGE_BOUNDARY;
547 status = InitLLTTable23a(Adapter, boundary);
548 if (status == _FAIL) {
549 RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
550 "Failed to init LLT table\n");
555 if (pHalData->bRDGEnable)
556 _InitRDGSetting(Adapter);
558 status = rtl8723a_FirmwareDownload(Adapter);
559 if (status != _SUCCESS) {
560 Adapter->bFWReady = false;
561 DBG_8723A("fw download fail!\n");
564 Adapter->bFWReady = true;
565 DBG_8723A("fw download ok!\n");
568 rtl8723a_InitializeFirmwareVars(Adapter);
570 if (pwrctrlpriv->reg_rfoff == true) {
571 pwrctrlpriv->rf_pwrstate = rf_off;
574 /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
575 /* HW GPIO pin. Before PHY_RFConfig8192C. */
576 /* HalDetectPwrDownMode(Adapter); */
577 /* 2010/08/26 MH If Efuse does not support sective suspend then disable the function. */
578 /* HalDetectSelectiveSuspendMode(Adapter); */
580 /* Set RF type for BB/RF configuration */
581 _InitRFType(Adapter);/* _ReadRFType() */
583 /* Save target channel */
584 /* <Roger_Notes> Current Channel will be updated again later. */
585 pHalData->CurrentChannel = 6;/* default set to 6 */
587 status = PHY_MACConfig8723A(Adapter);
588 if (status == _FAIL) {
589 DBG_8723A("PHY_MACConfig8723A fault !!\n");
594 /* d. Initialize BB related configurations. */
596 status = PHY_BBConfig8723A(Adapter);
597 if (status == _FAIL) {
598 DBG_8723A("PHY_BBConfig8723A fault !!\n");
602 /* Add for tx power by rate fine tune. We need to call the function after BB config. */
603 /* Because the tx power by rate table is inited in BB config. */
605 status = PHY_RF6052_Config8723A(Adapter);
606 if (status == _FAIL) {
607 DBG_8723A("PHY_RF6052_Config8723A failed!!\n");
611 /* reducing 80M spur */
612 rtl8723au_write32(Adapter, REG_AFE_XTAL_CTRL, 0x0381808d);
613 rtl8723au_write32(Adapter, REG_AFE_PLL_CTRL, 0xf0ffff83);
614 rtl8723au_write32(Adapter, REG_AFE_PLL_CTRL, 0xf0ffff82);
615 rtl8723au_write32(Adapter, REG_AFE_PLL_CTRL, 0xf0ffff83);
619 rtl8723au_write32(Adapter, rFPGA0_TxInfo, 0x00000003);
620 /* 0x870[6:5]= b'11 */
621 rtl8723au_write32(Adapter, rFPGA0_XAB_RFInterfaceSW, 0x07000760);
622 /* 0x860[6:5]= b'00 */
623 rtl8723au_write32(Adapter, rFPGA0_XA_RFInterfaceOE, 0x66F60210);
625 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
626 "%s: 0x870 = value 0x%x\n", __func__,
627 rtl8723au_read32(Adapter, 0x870));
630 /* Joseph Note: Keep RfRegChnlVal for later use. */
632 pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, RF_PATH_A,
633 RF_CHNLBW, bRFRegOffsetMask);
634 pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, RF_PATH_B,
635 RF_CHNLBW, bRFRegOffsetMask);
638 _InitQueueReservedPage(Adapter);
639 _InitTxBufferBoundary(Adapter);
641 _InitQueuePriority(Adapter);
642 _InitPageBoundary(Adapter);
643 _InitTransferPageSize(Adapter);
645 /* Get Rx PHY status in order to report RSSI and others. */
646 _InitDriverInfoSize(Adapter, DRVINFO_SZ);
648 _InitInterrupt(Adapter);
649 hw_var_set_macaddr(Adapter, Adapter->eeprompriv.mac_addr);
650 rtl8723a_set_media_status(Adapter, MSR_INFRA);
651 _InitWMACSetting(Adapter);
652 _InitAdaptiveCtrl(Adapter);
654 _InitRateFallback(Adapter);
655 _InitRetryFunction(Adapter);
656 rtl8723a_InitBeaconParameters(Adapter);
658 _BBTurnOnBlock(Adapter);
659 /* NicIFSetMacAddress(padapter, padapter->PermanentAddress); */
661 rtl8723a_cam_invalidate_all(Adapter);
663 /* 2010/12/17 MH We need to set TX power according to EFUSE content at first. */
664 PHY_SetTxPowerLevel8723A(Adapter, pHalData->CurrentChannel);
666 rtl8723a_InitAntenna_Selection(Adapter);
669 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
670 rtl8723au_write8(Adapter, REG_HWSEQ_CTRL, 0xFF);
673 /* Disable BAR, suggested by Scott */
674 /* 2010.04.09 add by hpfan */
676 rtl8723au_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
678 if (pregistrypriv->wifi_spec)
679 rtl8723au_write16(Adapter, REG_FAST_EDCA_CTRL, 0);
681 /* Move by Neo for USB SS from above setp */
682 _RfPowerSave(Adapter);
684 /* 2010/08/26 MH Merge from 8192CE. */
685 /* sherry masked that it has been done in _RfPowerSave */
687 /* recovery for 8192cu and 9723Au 20111017 */
688 if (pwrctrlpriv->rf_pwrstate == rf_on) {
689 if (pHalData->bIQKInitialized) {
690 rtl8723a_phy_iq_calibrate(Adapter, true);
692 rtl8723a_phy_iq_calibrate(Adapter, false);
693 pHalData->bIQKInitialized = true;
696 rtl8723a_odm_check_tx_power_tracking(Adapter);
698 rtl8723a_phy_lc_calibrate(Adapter);
700 rtl8723a_dual_antenna_detection(Adapter);
703 /* fixed USB interface interference issue */
704 rtl8723au_write8(Adapter, 0xfe40, 0xe0);
705 rtl8723au_write8(Adapter, 0xfe41, 0x8d);
706 rtl8723au_write8(Adapter, 0xfe42, 0x80);
707 rtl8723au_write32(Adapter, 0x20c, 0xfd0320);
708 /* Solve too many protocol error on USB bus */
709 if (!IS_81xxC_VENDOR_UMC_A_CUT(pHalData->VersionID)) {
711 rtl8723au_write8(Adapter, 0xFE40, 0xE6);
712 rtl8723au_write8(Adapter, 0xFE41, 0x94);
713 rtl8723au_write8(Adapter, 0xFE42, 0x80);
716 rtl8723au_write8(Adapter, 0xFE40, 0xE0);
717 rtl8723au_write8(Adapter, 0xFE41, 0x19);
718 rtl8723au_write8(Adapter, 0xFE42, 0x80);
721 rtl8723au_write8(Adapter, 0xFE40, 0xE5);
722 rtl8723au_write8(Adapter, 0xFE41, 0x91);
723 rtl8723au_write8(Adapter, 0xFE42, 0x80);
726 rtl8723au_write8(Adapter, 0xFE40, 0xE2);
727 rtl8723au_write8(Adapter, 0xFE41, 0x81);
728 rtl8723au_write8(Adapter, 0xFE42, 0x80);
732 /* _InitPABias(Adapter); */
734 /* Init BT hw config. */
735 rtl8723a_BT_init_hwconfig(Adapter);
737 rtl8723a_InitHalDm(Adapter);
739 val8 = (WiFiNavUpperUs + HAL_8723A_NAV_UPPER_UNIT - 1) /
740 HAL_8723A_NAV_UPPER_UNIT;
741 rtl8723au_write8(Adapter, REG_NAV_UPPER, val8);
743 /* 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, but we need to fin root cause. */
744 if (((rtl8723au_read32(Adapter, rFPGA0_RFMOD) & 0xFF000000) !=
746 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(24), 1);
747 RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
748 "%s: IQK fail recover\n", __func__);
751 /* ack for xmit mgmt frames. */
752 rtl8723au_write32(Adapter, REG_FWHW_TXQ_CTRL,
753 rtl8723au_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
756 if (status == _SUCCESS) {
757 Adapter->hw_init_completed = true;
759 if (Adapter->registrypriv.notch_filter == 1)
760 rtl8723a_notch_filter(Adapter, 1);
763 DBG_8723A("%s in %dms\n", __func__,
764 jiffies_to_msecs(jiffies - init_start_time));
768 static void phy_SsPwrSwitch92CU(struct rtw_adapter *Adapter,
769 enum rt_rf_power_state eRFPowerState)
771 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
774 sps0 = rtl8723au_read8(Adapter, REG_SPS0_CTRL);
776 switch (eRFPowerState) {
778 /* 1. Enable MAC Clock. Can not be enabled now. */
779 /* WriteXBYTE(REG_SYS_CLKR+1,
780 ReadXBYTE(REG_SYS_CLKR+1) | BIT(3)); */
782 /* 2. Force PWM, Enable SPS18_LDO_Marco_Block */
783 rtl8723au_write8(Adapter, REG_SPS0_CTRL,
784 sps0 | BIT(0) | BIT(3));
786 /* 3. restore BB, AFE control register. */
788 if (pHalData->rf_type == RF_2T2R)
789 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
792 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
794 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
795 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 0);
798 if (pHalData->rf_type == RF_2T2R)
799 rtl8723au_write32(Adapter, rRx_Wait_CCA, 0x63DB25A0);
800 else if (pHalData->rf_type == RF_1T1R)
801 rtl8723au_write32(Adapter, rRx_Wait_CCA, 0x631B25A0);
803 /* 4. issue 3-wire command that RF set to Rx idle
804 mode. This is used to re-write the RX idle mode. */
805 /* We can only prvide a usual value instead and then
806 HW will modify the value by itself. */
807 PHY_SetRFReg(Adapter, RF_PATH_A, RF_AC,
808 bRFRegOffsetMask, 0x32D95);
809 if (pHalData->rf_type == RF_2T2R) {
810 PHY_SetRFReg(Adapter, RF_PATH_B, RF_AC,
811 bRFRegOffsetMask, 0x32D95);
816 if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
819 sps0 &= ~(BIT(0) | BIT(3));
821 RT_TRACE(_module_hal_init_c_, _drv_err_, "SS LVL1\n");
822 /* Disable RF and BB only for SelectSuspend. */
824 /* 1. Set BB/RF to shutdown. */
825 /* (1) Reg878[5:3]= 0 RF rx_code for
826 preamble power saving */
827 /* (2)Reg878[21:19]= 0 Turn off RF-B */
828 /* (3) RegC04[7:4]= 0 Turn off all paths
829 for packet detection */
830 /* (4) Reg800[1] = 1 enable preamble power saving */
831 Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] =
832 rtl8723au_read32(Adapter, rFPGA0_XAB_RFParameter);
833 Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] =
834 rtl8723au_read32(Adapter, rOFDM0_TRxPathEnable);
835 Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] =
836 rtl8723au_read32(Adapter, rFPGA0_RFMOD);
837 if (pHalData->rf_type == RF_2T2R) {
838 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
840 } else if (pHalData->rf_type == RF_1T1R) {
841 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 0);
843 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
844 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 1);
846 /* 2 .AFE control register to power down. bit[30:22] */
847 Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] =
848 rtl8723au_read32(Adapter, rRx_Wait_CCA);
849 if (pHalData->rf_type == RF_2T2R)
850 rtl8723au_write32(Adapter, rRx_Wait_CCA, 0x00DB25A0);
851 else if (pHalData->rf_type == RF_1T1R)
852 rtl8723au_write32(Adapter, rRx_Wait_CCA, 0x001B25A0);
854 /* 3. issue 3-wire command that RF set to power down.*/
855 PHY_SetRFReg(Adapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0);
856 if (pHalData->rf_type == RF_2T2R)
857 PHY_SetRFReg(Adapter, RF_PATH_B, RF_AC,
858 bRFRegOffsetMask, 0);
860 /* 4. Force PFM , disable SPS18_LDO_Marco_Block */
861 rtl8723au_write8(Adapter, REG_SPS0_CTRL, sps0);
868 static void CardDisableRTL8723U(struct rtw_adapter *Adapter)
872 DBG_8723A("CardDisableRTL8723U\n");
873 /* USB-MF Card Disable Flow */
874 /* 1. Run LPS WL RFOFF flow */
875 HalPwrSeqCmdParsing23a(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
876 PWR_INTF_USB_MSK, rtl8723AU_enter_lps_flow);
878 /* 2. 0x1F[7:0] = 0 turn off RF */
879 rtl8723au_write8(Adapter, REG_RF_CTRL, 0x00);
881 /* ==== Reset digital sequence ====== */
882 if ((rtl8723au_read8(Adapter, REG_MCUFWDL) & BIT(7)) &&
883 Adapter->bFWReady) /* 8051 RAM code */
884 rtl8723a_FirmwareSelfReset(Adapter);
886 /* Reset MCU. Suggested by Filen. 2011.01.26. by tynli. */
887 u1bTmp = rtl8723au_read8(Adapter, REG_SYS_FUNC_EN+1);
888 rtl8723au_write8(Adapter, REG_SYS_FUNC_EN+1, u1bTmp & ~BIT(2));
890 /* g. MCUFWDL 0x80[1:0]= 0 reset MCU ready status */
891 rtl8723au_write8(Adapter, REG_MCUFWDL, 0x00);
893 /* ==== Reset digital sequence end ====== */
894 /* Card disable power action flow */
895 HalPwrSeqCmdParsing23a(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
897 rtl8723AU_card_disable_flow);
899 /* Reset MCU IO Wrapper, added by Roger, 2011.08.30. */
900 u1bTmp = rtl8723au_read8(Adapter, REG_RSV_CTRL + 1);
901 rtl8723au_write8(Adapter, REG_RSV_CTRL+1, u1bTmp & ~BIT(0));
902 u1bTmp = rtl8723au_read8(Adapter, REG_RSV_CTRL + 1);
903 rtl8723au_write8(Adapter, REG_RSV_CTRL+1, u1bTmp | BIT(0));
905 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */
906 rtl8723au_write8(Adapter, REG_RSV_CTRL, 0x0e);
909 int rtl8723au_hal_deinit(struct rtw_adapter *padapter)
911 DBG_8723A("==> %s\n", __func__);
913 #ifdef CONFIG_8723AU_BT_COEXIST
914 BT_HaltProcess(padapter);
916 /* 2011/02/18 To Fix RU LNA power leakage problem. We need to
917 execute below below in Adapter init and halt sequence.
918 According to EEchou's opinion, we can enable the ability for all */
919 /* IC. Accord to johnny's opinion, only RU need the support. */
920 CardDisableRTL8723U(padapter);
922 padapter->hw_init_completed = false;
927 int rtl8723au_inirp_init(struct rtw_adapter *Adapter)
930 struct recv_buf *precvbuf;
932 struct recv_priv *precvpriv = &Adapter->recvpriv;
933 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
937 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, "===> usb_inirp_init\n");
939 /* issue Rx irp to receive data */
940 precvbuf = (struct recv_buf *)precvpriv->precv_buf;
941 for (i = 0; i < NR_RECVBUFF; i++) {
942 if (rtl8723au_read_port(Adapter, 0, precvbuf) == _FAIL) {
943 RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
944 "usb_rx_init: usb_read_port error\n");
950 if (rtl8723au_read_interrupt(Adapter) == _FAIL) {
951 RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
952 "%s: usb_read_interrupt error\n", __func__);
955 pHalData->IntrMask[0] = rtl8723au_read32(Adapter, REG_USB_HIMR);
956 MSG_8723A("pHalData->IntrMask = 0x%04x\n", pHalData->IntrMask[0]);
957 pHalData->IntrMask[0] |= UHIMR_C2HCMD|UHIMR_CPWM;
958 rtl8723au_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]);
960 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
961 "<=== usb_inirp_init\n");
965 int rtl8723au_inirp_deinit(struct rtw_adapter *Adapter)
967 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
969 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
970 "===> usb_rx_deinit\n");
971 rtl8723au_read_port_cancel(Adapter);
972 pHalData->IntrMask[0] = rtl8723au_read32(Adapter, REG_USB_HIMR);
973 MSG_8723A("%s pHalData->IntrMask = 0x%04x\n", __func__,
974 pHalData->IntrMask[0]);
975 pHalData->IntrMask[0] = 0x0;
976 rtl8723au_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]);
977 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
978 "<=== usb_rx_deinit\n");
982 static void _ReadBoardType(struct rtw_adapter *Adapter, u8 *PROMContent,
985 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
986 u8 boardType = BOARD_USB_DONGLE;
989 if (IS_8723_SERIES(pHalData->VersionID))
990 pHalData->rf_type = RF_1T1R;
992 pHalData->rf_type = RF_2T2R;
993 pHalData->BoardType = boardType;
997 boardType = PROMContent[EEPROM_NORMAL_BoardType];
998 boardType &= BOARD_TYPE_NORMAL_MASK;/* bit[7:5] */
1001 pHalData->BoardType = boardType;
1002 MSG_8723A("_ReadBoardType(%x)\n", pHalData->BoardType);
1004 if (boardType == BOARD_USB_High_PA)
1005 pHalData->ExternalPA = 1;
1008 static void Hal_EfuseParseMACAddr_8723AU(struct rtw_adapter *padapter,
1009 u8 *hwinfo, bool AutoLoadFail)
1012 u8 sMacAddr[ETH_ALEN] = {0x00, 0xE0, 0x4C, 0x87, 0x23, 0x00};
1013 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1016 for (i = 0; i < 6; i++)
1017 pEEPROM->mac_addr[i] = sMacAddr[i];
1019 /* Read Permanent MAC address */
1020 memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723AU],
1024 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
1025 "Hal_EfuseParseMACAddr_8723AU: Permanent Address =%02x:%02x:%02x:%02x:%02x:%02x\n",
1026 pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
1027 pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
1028 pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]);
1031 static void readAdapterInfo(struct rtw_adapter *padapter)
1033 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1034 /* struct hal_data_8723a * pHalData = GET_HAL_DATA(padapter); */
1035 u8 hwinfo[HWSET_MAX_SIZE];
1037 Hal_InitPGData(padapter, hwinfo);
1038 Hal_EfuseParseIDCode(padapter, hwinfo);
1039 Hal_EfuseParseEEPROMVer(padapter, hwinfo,
1040 pEEPROM->bautoload_fail_flag);
1041 Hal_EfuseParseMACAddr_8723AU(padapter, hwinfo,
1042 pEEPROM->bautoload_fail_flag);
1043 Hal_EfuseParsetxpowerinfo_8723A(padapter, hwinfo,
1044 pEEPROM->bautoload_fail_flag);
1045 _ReadBoardType(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1046 Hal_EfuseParseBTCoexistInfo_8723A(padapter, hwinfo,
1047 pEEPROM->bautoload_fail_flag);
1049 rtl8723a_EfuseParseChnlPlan(padapter, hwinfo,
1050 pEEPROM->bautoload_fail_flag);
1051 Hal_EfuseParseThermalMeter_8723A(padapter, hwinfo,
1052 pEEPROM->bautoload_fail_flag);
1053 /* _ReadRFSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); */
1054 /* _ReadPSSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); */
1055 Hal_EfuseParseAntennaDiversity(padapter, hwinfo,
1056 pEEPROM->bautoload_fail_flag);
1058 Hal_EfuseParseEEPROMVer(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1059 Hal_EfuseParseCustomerID(padapter, hwinfo,
1060 pEEPROM->bautoload_fail_flag);
1061 Hal_EfuseParseRateIndicationOption(padapter, hwinfo,
1062 pEEPROM->bautoload_fail_flag);
1063 Hal_EfuseParseXtal_8723A(padapter, hwinfo,
1064 pEEPROM->bautoload_fail_flag);
1066 /* hal_CustomizedBehavior_8723U(Adapter); */
1068 /* Adapter->bDongle = (PROMContent[EEPROM_EASY_REPLACEMENT] == 1)? 0: 1; */
1069 DBG_8723A("%s(): REPLACEMENT = %x\n", __func__, padapter->bDongle);
1072 static void _ReadPROMContent(struct rtw_adapter *Adapter)
1074 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
1077 eeValue = rtl8723au_read8(Adapter, REG_9346CR);
1078 /* To check system boot selection. */
1079 pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1080 pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true;
1082 DBG_8723A("Boot from %s, Autoload %s !\n",
1083 (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1084 (pEEPROM->bautoload_fail_flag ? "Fail" : "OK"));
1086 readAdapterInfo(Adapter);
1091 /* We should set Efuse cell selection to WiFi cell in default. */
1096 /* Added by Roger, 2010.11.23. */
1098 static void hal_EfuseCellSel(struct rtw_adapter *Adapter)
1102 value32 = rtl8723au_read32(Adapter, EFUSE_TEST);
1103 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1104 rtl8723au_write32(Adapter, EFUSE_TEST, value32);
1107 void rtl8723a_read_adapter_info(struct rtw_adapter *Adapter)
1109 unsigned long start = jiffies;
1111 /* Read EEPROM size before call any EEPROM function */
1112 Adapter->EepromAddressSize = GetEEPROMSize8723A(Adapter);
1114 MSG_8723A("====> _ReadAdapterInfo8723AU\n");
1116 hal_EfuseCellSel(Adapter);
1118 _ReadPROMContent(Adapter);
1120 MSG_8723A("<==== _ReadAdapterInfo8723AU in %d ms\n",
1121 jiffies_to_msecs(jiffies - start));
1126 /* Query setting of specified variable. */
1128 int GetHalDefVar8192CUsb(struct rtw_adapter *Adapter,
1129 enum hal_def_variable eVariable, void *pValue)
1131 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1132 int bResult = _SUCCESS;
1134 switch (eVariable) {
1135 case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1136 *((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB;
1138 case HAL_DEF_IS_SUPPORT_ANT_DIV:
1140 case HAL_DEF_CURRENT_ANTENNA:
1142 case HAL_DEF_DRVINFO_SZ:
1143 *((u32 *)pValue) = DRVINFO_SZ;
1145 case HAL_DEF_MAX_RECVBUF_SZ:
1146 *((u32 *)pValue) = MAX_RECVBUF_SZ;
1148 case HAL_DEF_RX_PACKET_OFFSET:
1149 *((u32 *)pValue) = RXDESC_SIZE + DRVINFO_SZ;
1151 case HAL_DEF_DBG_DUMP_RXPKT:
1152 *((u8 *)pValue) = pHalData->bDumpRxPkt;
1154 case HAL_DEF_DBG_DM_FUNC:
1155 *((u32 *)pValue) = pHalData->odmpriv.SupportAbility;
1157 case HW_VAR_MAX_RX_AMPDU_FACTOR:
1158 *((u32 *)pValue) = IEEE80211_HT_MAX_AMPDU_64K;
1160 case HW_DEF_ODM_DBG_FLAG:
1162 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1163 printk("pDM_Odm->DebugComponents = 0x%llx\n",
1164 pDM_Odm->DebugComponents);
1175 void rtl8723a_update_ramask(struct rtw_adapter *padapter,
1176 u32 mac_id, u8 rssi_level)
1178 struct sta_info *psta;
1179 struct FW_Sta_Info *fw_sta;
1180 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1181 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1182 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
1183 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1184 struct wlan_bssid_ex *cur_network = &pmlmeinfo->network;
1185 u8 init_rate, networkType, raid, arg;
1186 u32 mask, rate_bitmap;
1187 u8 shortGIrate = false;
1190 if (mac_id >= NUM_STA) /* CAM_SIZE */
1193 psta = pmlmeinfo->FW_sta_info[mac_id].psta;
1198 case 0:/* for infra mode */
1200 rtw_get_rateset_len23a(cur_network->SupportedRates);
1201 networkType = judge_network_type23a(padapter,
1202 cur_network->SupportedRates,
1203 supportRateNum) & 0xf;
1204 /* pmlmeext->cur_wireless_mode = networkType; */
1205 raid = networktype_to_raid23a(networkType);
1207 mask = update_supported_rate23a(cur_network->SupportedRates,
1209 mask |= (pmlmeinfo->HT_enable) ?
1210 update_MSC_rate23a(&pmlmeinfo->ht_cap) : 0;
1212 if (support_short_GI23a(padapter, &pmlmeinfo->ht_cap))
1216 case 1:/* for broadcast/multicast */
1217 fw_sta = &pmlmeinfo->FW_sta_info[mac_id];
1218 supportRateNum = rtw_get_rateset_len23a(fw_sta->SupportedRates);
1219 if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
1220 networkType = WIRELESS_11B;
1222 networkType = WIRELESS_11G;
1223 raid = networktype_to_raid23a(networkType);
1225 mask = update_basic_rate23a(cur_network->SupportedRates,
1229 default: /* for each sta in IBSS */
1230 fw_sta = &pmlmeinfo->FW_sta_info[mac_id];
1231 supportRateNum = rtw_get_rateset_len23a(fw_sta->SupportedRates);
1232 networkType = judge_network_type23a(padapter,
1233 fw_sta->SupportedRates,
1234 supportRateNum) & 0xf;
1235 /* pmlmeext->cur_wireless_mode = networkType; */
1236 raid = networktype_to_raid23a(networkType);
1238 mask = update_supported_rate23a(cur_network->SupportedRates,
1241 /* todo: support HT in IBSS */
1245 /* mask &= 0x0fffffff; */
1246 rate_bitmap = ODM_Get_Rate_Bitmap23a(pHalData, mac_id, mask,
1248 DBG_8723A("%s => mac_id:%d, networkType:0x%02x, "
1249 "mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
1250 __func__, mac_id, networkType, mask, rssi_level, rate_bitmap);
1252 mask &= rate_bitmap;
1253 mask |= ((raid << 28) & 0xf0000000);
1255 init_rate = get_highest_rate_idx23a(mask) & 0x3f;
1257 arg = mac_id & 0x1f;/* MACID */
1260 if (shortGIrate == true)
1263 DBG_8723A("update raid entry, mask = 0x%x, arg = 0x%x\n", mask, arg);
1265 rtl8723a_set_raid_cmd(padapter, mask, arg);
1269 psta->init_rate = init_rate;
1271 /* set correct initial date rate for each mac_id */
1272 pdmpriv->INIDATA_RATE[mac_id] = init_rate;