2 * Copyright (c) 2003-2013 Broadcom Corporation
4 * Copyright (c) 2009-2010 Micron Technology, Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/delay.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/mtd/nand.h>
22 #include <linux/spi/spi.h>
24 #include "mt29f_spinand.h"
26 #define BUFSIZE (10 * 64 * 2048)
27 #define CACHE_BUF 2112
29 * OOB area specification layout: Total 32 available free bytes.
32 static inline struct spinand_state *mtd_to_state(struct mtd_info *mtd)
34 struct nand_chip *chip = (struct nand_chip *)mtd->priv;
35 struct spinand_info *info = (struct spinand_info *)chip->priv;
36 struct spinand_state *state = (struct spinand_state *)info->priv;
41 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
42 static int enable_hw_ecc;
43 static int enable_read_hw_ecc;
45 static struct nand_ecclayout spinand_oob_64 = {
49 17, 18, 19, 20, 21, 22,
50 33, 34, 35, 36, 37, 38,
51 49, 50, 51, 52, 53, 54, },
67 * spinand_cmd - to process a command to send to the SPI Nand
69 * Set up the command buffer to send to the SPI controller.
70 * The command buffer has to initialized to 0.
73 static int spinand_cmd(struct spi_device *spi, struct spinand_cmd *cmd)
75 struct spi_message message;
76 struct spi_transfer x[4];
79 spi_message_init(&message);
80 memset(x, 0, sizeof(x));
83 x[0].tx_buf = &cmd->cmd;
84 spi_message_add_tail(&x[0], &message);
87 x[1].len = cmd->n_addr;
88 x[1].tx_buf = cmd->addr;
89 spi_message_add_tail(&x[1], &message);
93 x[2].len = cmd->n_dummy;
95 spi_message_add_tail(&x[2], &message);
100 x[3].tx_buf = cmd->tx_buf;
101 spi_message_add_tail(&x[3], &message);
105 x[3].len = cmd->n_rx;
106 x[3].rx_buf = cmd->rx_buf;
107 spi_message_add_tail(&x[3], &message);
110 return spi_sync(spi, &message);
114 * spinand_read_id- Read SPI Nand ID
116 * Read ID: read two ID bytes from the SPI Nand device
118 static int spinand_read_id(struct spi_device *spi_nand, u8 *id)
122 struct spinand_cmd cmd = {0};
124 cmd.cmd = CMD_READ_ID;
126 cmd.rx_buf = &nand_id[0];
128 retval = spinand_cmd(spi_nand, &cmd);
130 dev_err(&spi_nand->dev, "error %d reading id\n", retval);
139 * spinand_read_status- send command 0xf to the SPI Nand status register
141 * After read, write, or erase, the Nand device is expected to set the
143 * This function is to allow reading the status of the command: read,
145 * Once the status turns to be ready, the other status bits also are
148 static int spinand_read_status(struct spi_device *spi_nand, u8 *status)
150 struct spinand_cmd cmd = {0};
153 cmd.cmd = CMD_READ_REG;
155 cmd.addr[0] = REG_STATUS;
159 ret = spinand_cmd(spi_nand, &cmd);
161 dev_err(&spi_nand->dev, "err: %d read status register\n", ret);
166 #define MAX_WAIT_JIFFIES (40 * HZ)
167 static int wait_till_ready(struct spi_device *spi_nand)
169 unsigned long deadline;
173 deadline = jiffies + MAX_WAIT_JIFFIES;
175 retval = spinand_read_status(spi_nand, &stat);
178 else if (!(stat & 0x1))
182 } while (!time_after_eq(jiffies, deadline));
184 if ((stat & 0x1) == 0)
191 * spinand_get_otp- send command 0xf to read the SPI Nand OTP register
193 * There is one bit( bit 0x10 ) to set or to clear the internal ECC.
194 * Enable chip internal ECC, set the bit to 1
195 * Disable chip internal ECC, clear the bit to 0
197 static int spinand_get_otp(struct spi_device *spi_nand, u8 *otp)
199 struct spinand_cmd cmd = {0};
202 cmd.cmd = CMD_READ_REG;
204 cmd.addr[0] = REG_OTP;
208 retval = spinand_cmd(spi_nand, &cmd);
210 dev_err(&spi_nand->dev, "error %d get otp\n", retval);
215 * spinand_set_otp- send command 0x1f to write the SPI Nand OTP register
217 * There is one bit( bit 0x10 ) to set or to clear the internal ECC.
218 * Enable chip internal ECC, set the bit to 1
219 * Disable chip internal ECC, clear the bit to 0
221 static int spinand_set_otp(struct spi_device *spi_nand, u8 *otp)
224 struct spinand_cmd cmd = {0};
226 cmd.cmd = CMD_WRITE_REG,
228 cmd.addr[0] = REG_OTP,
232 retval = spinand_cmd(spi_nand, &cmd);
234 dev_err(&spi_nand->dev, "error %d set otp\n", retval);
239 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
241 * spinand_enable_ecc- send command 0x1f to write the SPI Nand OTP register
243 * There is one bit( bit 0x10 ) to set or to clear the internal ECC.
244 * Enable chip internal ECC, set the bit to 1
245 * Disable chip internal ECC, clear the bit to 0
247 static int spinand_enable_ecc(struct spi_device *spi_nand)
252 retval = spinand_get_otp(spi_nand, &otp);
256 if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK)
259 retval = spinand_set_otp(spi_nand, &otp);
262 return spinand_get_otp(spi_nand, &otp);
266 static int spinand_disable_ecc(struct spi_device *spi_nand)
271 retval = spinand_get_otp(spi_nand, &otp);
275 if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) {
276 otp &= ~OTP_ECC_MASK;
277 retval = spinand_set_otp(spi_nand, &otp);
280 return spinand_get_otp(spi_nand, &otp);
286 * spinand_write_enable- send command 0x06 to enable write or erase the
289 * Before write and erase the Nand cells, the write enable has to be set.
290 * After the write or erase, the write enable bit is automatically
291 * cleared (status register bit 2)
292 * Set the bit 2 of the status register has the same effect
294 static int spinand_write_enable(struct spi_device *spi_nand)
296 struct spinand_cmd cmd = {0};
298 cmd.cmd = CMD_WR_ENABLE;
299 return spinand_cmd(spi_nand, &cmd);
302 static int spinand_read_page_to_cache(struct spi_device *spi_nand, u16 page_id)
304 struct spinand_cmd cmd = {0};
310 cmd.addr[1] = (u8)((row & 0xff00) >> 8);
311 cmd.addr[2] = (u8)(row & 0x00ff);
313 return spinand_cmd(spi_nand, &cmd);
317 * spinand_read_from_cache- send command 0x03 to read out the data from the
318 * cache register(2112 bytes max)
320 * The read can specify 1 to 2112 bytes of data read at the corresponding
324 static int spinand_read_from_cache(struct spi_device *spi_nand, u16 page_id,
325 u16 byte_id, u16 len, u8 *rbuf)
327 struct spinand_cmd cmd = {0};
331 cmd.cmd = CMD_READ_RDM;
333 cmd.addr[0] = (u8)((column & 0xff00) >> 8);
334 cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
335 cmd.addr[1] = (u8)(column & 0x00ff);
336 cmd.addr[2] = (u8)(0xff);
341 return spinand_cmd(spi_nand, &cmd);
345 * spinand_read_page-to read a page with:
346 * @page_id: the physical page number
347 * @offset: the location from 0 to 2111
348 * @len: number of bytes to read
349 * @rbuf: read buffer to hold @len bytes
352 * The read includes two commands to the Nand: 0x13 and 0x03 commands
353 * Poll to read status to wait for tRD time.
355 static int spinand_read_page(struct spi_device *spi_nand, u16 page_id,
356 u16 offset, u16 len, u8 *rbuf)
361 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
362 if (enable_read_hw_ecc) {
363 if (spinand_enable_ecc(spi_nand) < 0)
364 dev_err(&spi_nand->dev, "enable HW ECC failed!");
367 ret = spinand_read_page_to_cache(spi_nand, page_id);
371 if (wait_till_ready(spi_nand))
372 dev_err(&spi_nand->dev, "WAIT timedout!!!\n");
375 ret = spinand_read_status(spi_nand, &status);
377 dev_err(&spi_nand->dev,
378 "err %d read status register\n", ret);
382 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
383 if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
384 dev_err(&spi_nand->dev, "ecc error, page=%d\n",
392 ret = spinand_read_from_cache(spi_nand, page_id, offset, len, rbuf);
394 dev_err(&spi_nand->dev, "read from cache failed!!\n");
398 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
399 if (enable_read_hw_ecc) {
400 ret = spinand_disable_ecc(spi_nand);
402 dev_err(&spi_nand->dev, "disable ecc failed!!\n");
405 enable_read_hw_ecc = 0;
412 * spinand_program_data_to_cache--to write a page to cache with:
413 * @byte_id: the location to write to the cache
414 * @len: number of bytes to write
415 * @rbuf: read buffer to hold @len bytes
418 * The write command used here is 0x84--indicating that the cache is
420 * Since it is writing the data to cache, there is no tPROG time.
422 static int spinand_program_data_to_cache(struct spi_device *spi_nand,
423 u16 page_id, u16 byte_id,
426 struct spinand_cmd cmd = {0};
430 cmd.cmd = CMD_PROG_PAGE_CLRCACHE;
432 cmd.addr[0] = (u8)((column & 0xff00) >> 8);
433 cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
434 cmd.addr[1] = (u8)(column & 0x00ff);
438 return spinand_cmd(spi_nand, &cmd);
442 * spinand_program_execute--to write a page from cache to the Nand array with
443 * @page_id: the physical page location to write the page.
446 * The write command used here is 0x10--indicating the cache is writing to
448 * Need to wait for tPROG time to finish the transaction.
450 static int spinand_program_execute(struct spi_device *spi_nand, u16 page_id)
452 struct spinand_cmd cmd = {0};
456 cmd.cmd = CMD_PROG_PAGE_EXC;
458 cmd.addr[1] = (u8)((row & 0xff00) >> 8);
459 cmd.addr[2] = (u8)(row & 0x00ff);
461 return spinand_cmd(spi_nand, &cmd);
465 * spinand_program_page--to write a page with:
466 * @page_id: the physical page location to write the page.
467 * @offset: the location from the cache starting from 0 to 2111
468 * @len: the number of bytes to write
469 * @wbuf: the buffer to hold the number of bytes
472 * The commands used here are 0x06, 0x84, and 0x10--indicating that
473 * the write enable is first sent, the write cache command, and the
474 * write execute command.
475 * Poll to wait for the tPROG time to finish the transaction.
477 static int spinand_program_page(struct spi_device *spi_nand,
478 u16 page_id, u16 offset, u16 len, u8 *buf)
483 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
486 enable_read_hw_ecc = 0;
487 wbuf = devm_kzalloc(&spi_nand->dev, CACHE_BUF, GFP_KERNEL);
488 spinand_read_page(spi_nand, page_id, 0, CACHE_BUF, wbuf);
490 for (i = offset, j = 0; i < len; i++, j++)
494 retval = spinand_enable_ecc(spi_nand);
496 dev_err(&spi_nand->dev, "enable ecc failed!!\n");
503 retval = spinand_write_enable(spi_nand);
505 dev_err(&spi_nand->dev, "write enable failed!!\n");
508 if (wait_till_ready(spi_nand))
509 dev_err(&spi_nand->dev, "wait timedout!!!\n");
511 retval = spinand_program_data_to_cache(spi_nand, page_id,
515 retval = spinand_program_execute(spi_nand, page_id);
519 retval = spinand_read_status(spi_nand, &status);
521 dev_err(&spi_nand->dev,
522 "error %d reading status register\n", retval);
526 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
527 if ((status & STATUS_P_FAIL_MASK) == STATUS_P_FAIL) {
528 dev_err(&spi_nand->dev,
529 "program error, page %d\n", page_id);
535 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
537 retval = spinand_disable_ecc(spi_nand);
539 dev_err(&spi_nand->dev, "disable ecc failed!!\n");
550 * spinand_erase_block_erase--to erase a page with:
551 * @block_id: the physical block location to erase.
554 * The command used here is 0xd8--indicating an erase command to erase
555 * one block--64 pages
556 * Need to wait for tERS.
558 static int spinand_erase_block_erase(struct spi_device *spi_nand, u16 block_id)
560 struct spinand_cmd cmd = {0};
564 cmd.cmd = CMD_ERASE_BLK;
566 cmd.addr[1] = (u8)((row & 0xff00) >> 8);
567 cmd.addr[2] = (u8)(row & 0x00ff);
569 return spinand_cmd(spi_nand, &cmd);
573 * spinand_erase_block--to erase a page with:
574 * @block_id: the physical block location to erase.
577 * The commands used here are 0x06 and 0xd8--indicating an erase
578 * command to erase one block--64 pages
579 * It will first to enable the write enable bit (0x06 command),
580 * and then send the 0xd8 erase command
581 * Poll to wait for the tERS time to complete the tranaction.
583 static int spinand_erase_block(struct spi_device *spi_nand, u16 block_id)
588 retval = spinand_write_enable(spi_nand);
589 if (wait_till_ready(spi_nand))
590 dev_err(&spi_nand->dev, "wait timedout!!!\n");
592 retval = spinand_erase_block_erase(spi_nand, block_id);
594 retval = spinand_read_status(spi_nand, &status);
596 dev_err(&spi_nand->dev,
597 "error %d reading status register\n", retval);
601 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
602 if ((status & STATUS_E_FAIL_MASK) == STATUS_E_FAIL) {
603 dev_err(&spi_nand->dev,
604 "erase error, block %d\n", block_id);
613 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
614 static int spinand_write_page_hwecc(struct mtd_info *mtd,
615 struct nand_chip *chip,
616 const u8 *buf, int oob_required,
620 int eccsize = chip->ecc.size;
621 int eccsteps = chip->ecc.steps;
624 chip->write_buf(mtd, p, eccsize * eccsteps);
628 static int spinand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
629 u8 *buf, int oob_required, int page)
634 int eccsize = chip->ecc.size;
635 int eccsteps = chip->ecc.steps;
636 struct spinand_info *info = (struct spinand_info *)chip->priv;
638 enable_read_hw_ecc = 1;
640 chip->read_buf(mtd, p, eccsize * eccsteps);
642 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
645 retval = spinand_read_status(info->spi, &status);
648 "error %d reading status register\n", retval);
652 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
653 if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
654 pr_info("spinand: ECC error\n");
655 mtd->ecc_stats.failed++;
656 } else if ((status & STATUS_ECC_MASK) ==
657 STATUS_ECC_1BIT_CORRECTED)
658 mtd->ecc_stats.corrected++;
666 static void spinand_select_chip(struct mtd_info *mtd, int dev)
670 static u8 spinand_read_byte(struct mtd_info *mtd)
672 struct spinand_state *state = mtd_to_state(mtd);
675 data = state->buf[state->buf_ptr];
680 static int spinand_wait(struct mtd_info *mtd, struct nand_chip *chip)
682 struct spinand_info *info = (struct spinand_info *)chip->priv;
684 unsigned long timeo = jiffies;
685 int retval, state = chip->state;
688 if (state == FL_ERASING)
689 timeo += (HZ * 400) / 1000;
691 timeo += (HZ * 20) / 1000;
693 while (time_before(jiffies, timeo)) {
694 retval = spinand_read_status(info->spi, &status);
697 "error %d reading status register\n", retval);
701 if ((status & STATUS_OIP_MASK) == STATUS_READY)
709 static void spinand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
711 struct spinand_state *state = mtd_to_state(mtd);
713 memcpy(state->buf + state->buf_ptr, buf, len);
714 state->buf_ptr += len;
717 static void spinand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
719 struct spinand_state *state = mtd_to_state(mtd);
721 memcpy(buf, state->buf + state->buf_ptr, len);
722 state->buf_ptr += len;
726 * spinand_reset- send RESET command "0xff" to the Nand device.
728 static void spinand_reset(struct spi_device *spi_nand)
730 struct spinand_cmd cmd = {0};
734 if (spinand_cmd(spi_nand, &cmd) < 0)
735 pr_info("spinand reset failed!\n");
737 /* elapse 1ms before issuing any other command */
738 usleep_range(1000, 2000);
740 if (wait_till_ready(spi_nand))
741 dev_err(&spi_nand->dev, "wait timedout!\n");
744 static void spinand_cmdfunc(struct mtd_info *mtd, unsigned int command,
745 int column, int page)
747 struct nand_chip *chip = (struct nand_chip *)mtd->priv;
748 struct spinand_info *info = (struct spinand_info *)chip->priv;
749 struct spinand_state *state = (struct spinand_state *)info->priv;
753 * READ0 - read in first 0x800 bytes
758 spinand_read_page(info->spi, page, 0x0, 0x840, state->buf);
760 /* READOOB reads only the OOB because no ECC is performed. */
761 case NAND_CMD_READOOB:
763 spinand_read_page(info->spi, page, 0x800, 0x40, state->buf);
765 case NAND_CMD_RNDOUT:
766 state->buf_ptr = column;
768 case NAND_CMD_READID:
770 spinand_read_id(info->spi, state->buf);
775 /* ERASE1 stores the block and page address */
776 case NAND_CMD_ERASE1:
777 spinand_erase_block(info->spi, page);
779 /* ERASE2 uses the block and page address from ERASE1 */
780 case NAND_CMD_ERASE2:
782 /* SEQIN sets up the addr buffer and all registers except the length */
788 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
789 case NAND_CMD_PAGEPROG:
790 spinand_program_page(info->spi, state->row, state->col,
791 state->buf_ptr, state->buf);
793 case NAND_CMD_STATUS:
794 spinand_get_otp(info->spi, state->buf);
795 if (!(state->buf[0] & 0x80))
796 state->buf[0] = 0x80;
801 if (wait_till_ready(info->spi))
802 dev_err(&info->spi->dev, "WAIT timedout!!!\n");
803 /* a minimum of 250us must elapse before issuing RESET cmd*/
804 usleep_range(250, 1000);
805 spinand_reset(info->spi);
808 dev_err(&mtd->dev, "Unknown CMD: 0x%x\n", command);
813 * spinand_lock_block- send write register 0x1f command to the Nand device
816 * After power up, all the Nand blocks are locked. This function allows
817 * one to unlock the blocks, and so it can be written or erased.
819 static int spinand_lock_block(struct spi_device *spi_nand, u8 lock)
821 struct spinand_cmd cmd = {0};
825 ret = spinand_get_otp(spi_nand, &otp);
827 cmd.cmd = CMD_WRITE_REG;
829 cmd.addr[0] = REG_BLOCK_LOCK;
833 ret = spinand_cmd(spi_nand, &cmd);
835 dev_err(&spi_nand->dev, "error %d lock block\n", ret);
841 * spinand_probe - [spinand Interface]
842 * @spi_nand: registered device driver.
845 * To set up the device driver parameters to make the device available.
847 static int spinand_probe(struct spi_device *spi_nand)
849 struct mtd_info *mtd;
850 struct nand_chip *chip;
851 struct spinand_info *info;
852 struct spinand_state *state;
853 struct mtd_part_parser_data ppdata;
855 info = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_info),
860 info->spi = spi_nand;
862 spinand_lock_block(spi_nand, BL_ALL_UNLOCKED);
864 state = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_state),
871 state->buf = devm_kzalloc(&spi_nand->dev, BUFSIZE, GFP_KERNEL);
875 chip = devm_kzalloc(&spi_nand->dev, sizeof(struct nand_chip),
880 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
881 chip->ecc.mode = NAND_ECC_HW;
882 chip->ecc.size = 0x200;
883 chip->ecc.bytes = 0x6;
884 chip->ecc.steps = 0x4;
886 chip->ecc.strength = 1;
887 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
888 chip->ecc.layout = &spinand_oob_64;
889 chip->ecc.read_page = spinand_read_page_hwecc;
890 chip->ecc.write_page = spinand_write_page_hwecc;
892 chip->ecc.mode = NAND_ECC_SOFT;
893 if (spinand_disable_ecc(spi_nand) < 0)
894 pr_info("%s: disable ecc failed!\n", __func__);
898 chip->read_buf = spinand_read_buf;
899 chip->write_buf = spinand_write_buf;
900 chip->read_byte = spinand_read_byte;
901 chip->cmdfunc = spinand_cmdfunc;
902 chip->waitfunc = spinand_wait;
903 chip->options |= NAND_CACHEPRG;
904 chip->select_chip = spinand_select_chip;
906 mtd = devm_kzalloc(&spi_nand->dev, sizeof(struct mtd_info), GFP_KERNEL);
910 dev_set_drvdata(&spi_nand->dev, mtd);
913 mtd->dev.parent = &spi_nand->dev;
916 if (nand_scan(mtd, 1))
919 ppdata.of_node = spi_nand->dev.of_node;
920 return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
924 * spinand_remove: Remove the device driver
925 * @spi: the spi device.
928 * To remove the device driver parameters and free up allocated memories.
930 static int spinand_remove(struct spi_device *spi)
932 mtd_device_unregister(dev_get_drvdata(&spi->dev));
937 static const struct of_device_id spinand_dt[] = {
938 { .compatible = "spinand,mt29f", },
941 MODULE_DEVICE_TABLE(of, spinand_dt);
944 * Device name structure description
946 static struct spi_driver spinand_driver = {
949 .of_match_table = spinand_dt,
951 .probe = spinand_probe,
952 .remove = spinand_remove,
955 module_spi_driver(spinand_driver);
957 MODULE_DESCRIPTION("SPI NAND driver for Micron");
958 MODULE_AUTHOR("Henry Pan <hspan@micron.com>, Kamlakant Patel <kamlakant.patel@broadcom.com>");
959 MODULE_LICENSE("GPL v2");