2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
19 #include "dgnc_driver.h"
21 /************************************************************************
22 * Per channel/port NEO UART structure *
23 ************************************************************************
24 * Base Structure Entries Usage Meanings to Host *
26 * W = read write R = read only *
28 ************************************************************************/
30 struct neo_uart_struct {
31 u8 txrx; /* WR RHR/THR - Holding Reg */
32 u8 ier; /* WR IER - Interrupt Enable Reg */
33 u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
34 u8 lcr; /* WR LCR - Line Control Reg */
35 u8 mcr; /* WR MCR - Modem Control Reg */
36 u8 lsr; /* WR LSR - Line Status Reg */
37 u8 msr; /* WR MSR - Modem Status Reg */
38 u8 spr; /* WR SPR - Scratch Pad Reg */
39 u8 fctr; /* WR FCTR - Feature Control Reg */
40 u8 efr; /* WR EFR - Enhanced Function Reg */
41 u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */
42 u8 rfifo; /* WR RXCNT/RXTRG - Receive FIFO Reg */
43 u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */
44 u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */
45 u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */
46 u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */
48 u8 reserved1[0x2ff - 0x200]; /* U Reserved by Exar */
49 u8 txrxburst[64]; /* RW 64 bytes of RX/TX FIFO Data */
50 u8 reserved2[0x37f - 0x340]; /* U Reserved by Exar */
51 u8 rxburst_with_errors[64]; /* R 64 bytes of RX FIFO Data + LSR */
54 /* Where to read the extended interrupt register (32bits instead of 8bits) */
55 #define UART_17158_POLL_ADDR_OFFSET 0x80
57 /* These are the current dvid's of the Neo boards */
58 #define UART_XR17C158_DVID 0x20
59 #define UART_XR17D158_DVID 0x20
60 #define UART_XR17E158_DVID 0x40
62 #define NEO_EECK 0x10 /* Clock */
63 #define NEO_EECS 0x20 /* Chip Select */
64 #define NEO_EEDI 0x40 /* Data In is an Output Pin */
65 #define NEO_EEDO 0x80 /* Data Out is an Input Pin */
66 #define NEO_EEREG 0x8E /* offset to EEPROM control reg */
69 #define NEO_VPD_IMAGESIZE 0x40 /* size of image to read from EEPROM in words */
70 #define NEO_VPD_IMAGEBYTES (NEO_VPD_IMAGESIZE * 2)
73 * These are the redefinitions for the FCTR on the XR17C158, since
74 * Exar made them different than their earlier design. (XR16C854)
77 /* These are only applicable when table D is selected */
78 #define UART_17158_FCTR_RTS_NODELAY 0x00
79 #define UART_17158_FCTR_RTS_4DELAY 0x01
80 #define UART_17158_FCTR_RTS_6DELAY 0x02
81 #define UART_17158_FCTR_RTS_8DELAY 0x03
82 #define UART_17158_FCTR_RTS_12DELAY 0x12
83 #define UART_17158_FCTR_RTS_16DELAY 0x05
84 #define UART_17158_FCTR_RTS_20DELAY 0x13
85 #define UART_17158_FCTR_RTS_24DELAY 0x06
86 #define UART_17158_FCTR_RTS_28DELAY 0x14
87 #define UART_17158_FCTR_RTS_32DELAY 0x07
88 #define UART_17158_FCTR_RTS_36DELAY 0x16
89 #define UART_17158_FCTR_RTS_40DELAY 0x08
90 #define UART_17158_FCTR_RTS_44DELAY 0x09
91 #define UART_17158_FCTR_RTS_48DELAY 0x10
92 #define UART_17158_FCTR_RTS_52DELAY 0x11
94 #define UART_17158_FCTR_RTS_IRDA 0x10
95 #define UART_17158_FCTR_RS485 0x20
96 #define UART_17158_FCTR_TRGA 0x00
97 #define UART_17158_FCTR_TRGB 0x40
98 #define UART_17158_FCTR_TRGC 0x80
99 #define UART_17158_FCTR_TRGD 0xC0
101 /* 17158 trigger table selects.. */
102 #define UART_17158_FCTR_BIT6 0x40
103 #define UART_17158_FCTR_BIT7 0x80
105 /* 17158 TX/RX memmapped buffer offsets */
106 #define UART_17158_RX_FIFOSIZE 64
107 #define UART_17158_TX_FIFOSIZE 64
109 /* 17158 Extended IIR's */
110 #define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
111 #define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */
112 #define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */
113 #define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */
116 * These are the extended interrupts that get sent
117 * back to us from the UART's 32bit interrupt register
119 #define UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */
120 #define UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */
121 #define UART_17158_TXRDY 0x3 /* TX Ready */
122 #define UART_17158_MSR 0x4 /* Modem State Change */
123 #define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding Reg Empty */
124 #define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */
127 * These are the EXTENDED definitions for the 17C158's Interrupt
130 #define UART_17158_EFR_ECB 0x10 /* Enhanced control bit */
131 #define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
132 #define UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
133 #define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
134 #define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
136 #define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */
137 #define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */
139 #define UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */
140 #define UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */
141 #define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */
142 #define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */
145 * Our Global Variables
147 extern struct board_ops dgnc_neo_ops;