2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/sched.h> /* For jiffies, task states */
19 #include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */
20 #include <linux/delay.h> /* For udelay */
21 #include <linux/io.h> /* For read[bwl]/write[bwl] */
22 #include <linux/serial.h> /* For struct async_serial */
23 #include <linux/serial_reg.h> /* For the various UART offsets */
25 #include "dgnc_driver.h" /* Driver main header file */
26 #include "dgnc_neo.h" /* Our header file */
29 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port);
30 static inline void neo_parse_isr(struct dgnc_board *brd, uint port);
31 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch);
32 static inline void neo_clear_break(struct channel_t *ch, int force);
33 static inline void neo_set_cts_flow_control(struct channel_t *ch);
34 static inline void neo_set_rts_flow_control(struct channel_t *ch);
35 static inline void neo_set_ixon_flow_control(struct channel_t *ch);
36 static inline void neo_set_ixoff_flow_control(struct channel_t *ch);
37 static inline void neo_set_no_output_flow_control(struct channel_t *ch);
38 static inline void neo_set_no_input_flow_control(struct channel_t *ch);
39 static inline void neo_set_new_start_stop_chars(struct channel_t *ch);
40 static void neo_parse_modem(struct channel_t *ch, unsigned char signals);
41 static void neo_tasklet(unsigned long data);
42 static void neo_vpd(struct dgnc_board *brd);
43 static void neo_uart_init(struct channel_t *ch);
44 static void neo_uart_off(struct channel_t *ch);
45 static int neo_drain(struct tty_struct *tty, uint seconds);
46 static void neo_param(struct tty_struct *tty);
47 static void neo_assert_modem_signals(struct channel_t *ch);
48 static void neo_flush_uart_write(struct channel_t *ch);
49 static void neo_flush_uart_read(struct channel_t *ch);
50 static void neo_disable_receiver(struct channel_t *ch);
51 static void neo_enable_receiver(struct channel_t *ch);
52 static void neo_send_break(struct channel_t *ch, int msecs);
53 static void neo_send_start_character(struct channel_t *ch);
54 static void neo_send_stop_character(struct channel_t *ch);
55 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch);
56 static uint neo_get_uart_bytes_left(struct channel_t *ch);
57 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c);
58 static irqreturn_t neo_intr(int irq, void *voidbrd);
61 struct board_ops dgnc_neo_ops = {
62 .tasklet = neo_tasklet,
64 .uart_init = neo_uart_init,
65 .uart_off = neo_uart_off,
69 .assert_modem_signals = neo_assert_modem_signals,
70 .flush_uart_write = neo_flush_uart_write,
71 .flush_uart_read = neo_flush_uart_read,
72 .disable_receiver = neo_disable_receiver,
73 .enable_receiver = neo_enable_receiver,
74 .send_break = neo_send_break,
75 .send_start_character = neo_send_start_character,
76 .send_stop_character = neo_send_stop_character,
77 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
78 .get_uart_bytes_left = neo_get_uart_bytes_left,
79 .send_immediate_char = neo_send_immediate_char
82 static uint dgnc_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
86 * This function allows calls to ensure that all outstanding
87 * PCI writes have been completed, by doing a PCI read against
88 * a non-destructive, read-only location on the Neo card.
90 * In this case, we are reading the DVID (Read-only Device Identification)
91 * value of the Neo card.
93 static inline void neo_pci_posting_flush(struct dgnc_board *bd)
95 readb(bd->re_map_membase + 0x8D);
98 static inline void neo_set_cts_flow_control(struct channel_t *ch)
100 unsigned char ier = readb(&ch->ch_neo_uart->ier);
101 unsigned char efr = readb(&ch->ch_neo_uart->efr);
104 /* Turn on auto CTS flow control */
106 ier |= UART_17158_IER_CTSDSR;
108 ier &= ~(UART_17158_IER_CTSDSR);
111 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
113 /* Turn off auto Xon flow control */
114 efr &= ~UART_17158_EFR_IXON;
116 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
117 writeb(0, &ch->ch_neo_uart->efr);
119 /* Turn on UART enhanced bits */
120 writeb(efr, &ch->ch_neo_uart->efr);
122 /* Turn on table D, with 8 char hi/low watermarks */
123 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
125 /* Feed the UART our trigger levels */
126 writeb(8, &ch->ch_neo_uart->tfifo);
129 writeb(ier, &ch->ch_neo_uart->ier);
131 neo_pci_posting_flush(ch->ch_bd);
135 static inline void neo_set_rts_flow_control(struct channel_t *ch)
137 unsigned char ier = readb(&ch->ch_neo_uart->ier);
138 unsigned char efr = readb(&ch->ch_neo_uart->efr);
140 /* Turn on auto RTS flow control */
142 ier |= UART_17158_IER_RTSDTR;
144 ier &= ~(UART_17158_IER_RTSDTR);
146 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
148 /* Turn off auto Xoff flow control */
149 ier &= ~UART_17158_IER_XOFF;
150 efr &= ~UART_17158_EFR_IXOFF;
152 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
153 writeb(0, &ch->ch_neo_uart->efr);
155 /* Turn on UART enhanced bits */
156 writeb(efr, &ch->ch_neo_uart->efr);
158 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
159 ch->ch_r_watermark = 4;
161 writeb(32, &ch->ch_neo_uart->rfifo);
162 ch->ch_r_tlevel = 32;
164 writeb(ier, &ch->ch_neo_uart->ier);
167 * From the Neo UART spec sheet:
168 * The auto RTS/DTR function must be started by asserting
169 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
172 ch->ch_mostat |= UART_MCR_RTS;
174 neo_pci_posting_flush(ch->ch_bd);
178 static inline void neo_set_ixon_flow_control(struct channel_t *ch)
180 unsigned char ier = readb(&ch->ch_neo_uart->ier);
181 unsigned char efr = readb(&ch->ch_neo_uart->efr);
183 /* Turn off auto CTS flow control */
184 ier &= ~UART_17158_IER_CTSDSR;
185 efr &= ~UART_17158_EFR_CTSDSR;
187 /* Turn on auto Xon flow control */
188 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
190 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
191 writeb(0, &ch->ch_neo_uart->efr);
193 /* Turn on UART enhanced bits */
194 writeb(efr, &ch->ch_neo_uart->efr);
196 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
197 ch->ch_r_watermark = 4;
199 writeb(32, &ch->ch_neo_uart->rfifo);
200 ch->ch_r_tlevel = 32;
202 /* Tell UART what start/stop chars it should be looking for */
203 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
204 writeb(0, &ch->ch_neo_uart->xonchar2);
206 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
207 writeb(0, &ch->ch_neo_uart->xoffchar2);
209 writeb(ier, &ch->ch_neo_uart->ier);
211 neo_pci_posting_flush(ch->ch_bd);
215 static inline void neo_set_ixoff_flow_control(struct channel_t *ch)
217 unsigned char ier = readb(&ch->ch_neo_uart->ier);
218 unsigned char efr = readb(&ch->ch_neo_uart->efr);
220 /* Turn off auto RTS flow control */
221 ier &= ~UART_17158_IER_RTSDTR;
222 efr &= ~UART_17158_EFR_RTSDTR;
224 /* Turn on auto Xoff flow control */
225 ier |= UART_17158_IER_XOFF;
226 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
228 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
229 writeb(0, &ch->ch_neo_uart->efr);
231 /* Turn on UART enhanced bits */
232 writeb(efr, &ch->ch_neo_uart->efr);
234 /* Turn on table D, with 8 char hi/low watermarks */
235 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
237 writeb(8, &ch->ch_neo_uart->tfifo);
240 /* Tell UART what start/stop chars it should be looking for */
241 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
242 writeb(0, &ch->ch_neo_uart->xonchar2);
244 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
245 writeb(0, &ch->ch_neo_uart->xoffchar2);
247 writeb(ier, &ch->ch_neo_uart->ier);
249 neo_pci_posting_flush(ch->ch_bd);
253 static inline void neo_set_no_input_flow_control(struct channel_t *ch)
255 unsigned char ier = readb(&ch->ch_neo_uart->ier);
256 unsigned char efr = readb(&ch->ch_neo_uart->efr);
258 /* Turn off auto RTS flow control */
259 ier &= ~UART_17158_IER_RTSDTR;
260 efr &= ~UART_17158_EFR_RTSDTR;
262 /* Turn off auto Xoff flow control */
263 ier &= ~UART_17158_IER_XOFF;
264 if (ch->ch_c_iflag & IXON)
265 efr &= ~(UART_17158_EFR_IXOFF);
267 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
270 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
271 writeb(0, &ch->ch_neo_uart->efr);
273 /* Turn on UART enhanced bits */
274 writeb(efr, &ch->ch_neo_uart->efr);
276 /* Turn on table D, with 8 char hi/low watermarks */
277 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
279 ch->ch_r_watermark = 0;
281 writeb(16, &ch->ch_neo_uart->tfifo);
282 ch->ch_t_tlevel = 16;
284 writeb(16, &ch->ch_neo_uart->rfifo);
285 ch->ch_r_tlevel = 16;
287 writeb(ier, &ch->ch_neo_uart->ier);
289 neo_pci_posting_flush(ch->ch_bd);
293 static inline void neo_set_no_output_flow_control(struct channel_t *ch)
295 unsigned char ier = readb(&ch->ch_neo_uart->ier);
296 unsigned char efr = readb(&ch->ch_neo_uart->efr);
298 /* Turn off auto CTS flow control */
299 ier &= ~UART_17158_IER_CTSDSR;
300 efr &= ~UART_17158_EFR_CTSDSR;
302 /* Turn off auto Xon flow control */
303 if (ch->ch_c_iflag & IXOFF)
304 efr &= ~UART_17158_EFR_IXON;
306 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
308 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
309 writeb(0, &ch->ch_neo_uart->efr);
311 /* Turn on UART enhanced bits */
312 writeb(efr, &ch->ch_neo_uart->efr);
314 /* Turn on table D, with 8 char hi/low watermarks */
315 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
317 ch->ch_r_watermark = 0;
319 writeb(16, &ch->ch_neo_uart->tfifo);
320 ch->ch_t_tlevel = 16;
322 writeb(16, &ch->ch_neo_uart->rfifo);
323 ch->ch_r_tlevel = 16;
325 writeb(ier, &ch->ch_neo_uart->ier);
327 neo_pci_posting_flush(ch->ch_bd);
331 /* change UARTs start/stop chars */
332 static inline void neo_set_new_start_stop_chars(struct channel_t *ch)
335 /* if hardware flow control is set, then skip this whole thing */
336 if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) || ch->ch_c_cflag & CRTSCTS)
339 /* Tell UART what start/stop chars it should be looking for */
340 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
341 writeb(0, &ch->ch_neo_uart->xonchar2);
343 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
344 writeb(0, &ch->ch_neo_uart->xoffchar2);
346 neo_pci_posting_flush(ch->ch_bd);
351 * No locks are assumed to be held when calling this function.
353 static inline void neo_clear_break(struct channel_t *ch, int force)
357 spin_lock_irqsave(&ch->ch_lock, flags);
359 /* Bail if we aren't currently sending a break. */
360 if (!ch->ch_stop_sending_break) {
361 spin_unlock_irqrestore(&ch->ch_lock, flags);
365 /* Turn break off, and unset some variables */
366 if (ch->ch_flags & CH_BREAK_SENDING) {
367 if (time_after_eq(jiffies, ch->ch_stop_sending_break)
369 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
371 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
372 neo_pci_posting_flush(ch->ch_bd);
373 ch->ch_flags &= ~(CH_BREAK_SENDING);
374 ch->ch_stop_sending_break = 0;
377 spin_unlock_irqrestore(&ch->ch_lock, flags);
382 * Parse the ISR register.
384 static inline void neo_parse_isr(struct dgnc_board *brd, uint port)
386 struct channel_t *ch;
391 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
394 if (port >= brd->maxports)
397 ch = brd->channels[port];
398 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
401 /* Here we try to figure out what caused the interrupt to happen */
404 isr = readb(&ch->ch_neo_uart->isr_fcr);
406 /* Bail if no pending interrupt */
407 if (isr & UART_IIR_NO_INT)
411 * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
413 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
415 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
416 /* Read data from uart -> queue */
419 neo_copy_data_from_uart_to_queue(ch);
421 /* Call our tty layer to enforce queue flow control if needed. */
422 spin_lock_irqsave(&ch->ch_lock, flags);
423 dgnc_check_queue_flow_control(ch);
424 spin_unlock_irqrestore(&ch->ch_lock, flags);
427 if (isr & UART_IIR_THRI) {
430 /* Transfer data (if any) from Write Queue -> UART. */
431 spin_lock_irqsave(&ch->ch_lock, flags);
432 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
433 spin_unlock_irqrestore(&ch->ch_lock, flags);
434 neo_copy_data_from_queue_to_uart(ch);
437 if (isr & UART_17158_IIR_XONXOFF) {
438 cause = readb(&ch->ch_neo_uart->xoffchar1);
441 * Since the UART detected either an XON or
442 * XOFF match, we need to figure out which
443 * one it was, so we can suspend or resume data flow.
445 if (cause == UART_17158_XON_DETECT) {
446 /* Is output stopped right now, if so, resume it */
447 if (brd->channels[port]->ch_flags & CH_STOP) {
448 spin_lock_irqsave(&ch->ch_lock,
450 ch->ch_flags &= ~(CH_STOP);
451 spin_unlock_irqrestore(&ch->ch_lock,
454 } else if (cause == UART_17158_XOFF_DETECT) {
455 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
456 spin_lock_irqsave(&ch->ch_lock,
458 ch->ch_flags |= CH_STOP;
459 spin_unlock_irqrestore(&ch->ch_lock,
465 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
467 * If we get here, this means the hardware is doing auto flow control.
468 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
472 cause = readb(&ch->ch_neo_uart->mcr);
473 /* Which pin is doing auto flow? RTS or DTR? */
474 if ((cause & 0x4) == 0) {
475 if (cause & UART_MCR_RTS) {
476 spin_lock_irqsave(&ch->ch_lock,
478 ch->ch_mostat |= UART_MCR_RTS;
479 spin_unlock_irqrestore(&ch->ch_lock,
482 spin_lock_irqsave(&ch->ch_lock,
484 ch->ch_mostat &= ~(UART_MCR_RTS);
485 spin_unlock_irqrestore(&ch->ch_lock,
489 if (cause & UART_MCR_DTR) {
490 spin_lock_irqsave(&ch->ch_lock,
492 ch->ch_mostat |= UART_MCR_DTR;
493 spin_unlock_irqrestore(&ch->ch_lock,
496 spin_lock_irqsave(&ch->ch_lock,
498 ch->ch_mostat &= ~(UART_MCR_DTR);
499 spin_unlock_irqrestore(&ch->ch_lock,
505 /* Parse any modem signal changes */
506 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
511 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port)
513 struct channel_t *ch;
518 * Check to make sure it didn't receive interrupt with a null board
519 * associated or a board pointer that wasn't ours.
521 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
524 if (port >= brd->maxports)
527 ch = brd->channels[port];
528 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
531 linestatus = readb(&ch->ch_neo_uart->lsr);
533 ch->ch_cached_lsr |= linestatus;
535 if (ch->ch_cached_lsr & UART_LSR_DR) {
538 /* Read data from uart -> queue */
539 neo_copy_data_from_uart_to_queue(ch);
540 spin_lock_irqsave(&ch->ch_lock, flags);
541 dgnc_check_queue_flow_control(ch);
542 spin_unlock_irqrestore(&ch->ch_lock, flags);
546 * The next 3 tests should *NOT* happen, as the above test
547 * should encapsulate all 3... At least, thats what Exar says.
550 if (linestatus & UART_LSR_PE)
553 if (linestatus & UART_LSR_FE)
556 if (linestatus & UART_LSR_BI)
559 if (linestatus & UART_LSR_OE) {
561 * Rx Oruns. Exar says that an orun will NOT corrupt
562 * the FIFO. It will just replace the holding register
563 * with this new data byte. So basically just ignore this.
564 * Probably we should eventually have an orun stat in our driver...
566 ch->ch_err_overrun++;
569 if (linestatus & UART_LSR_THRE) {
572 spin_lock_irqsave(&ch->ch_lock, flags);
573 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
574 spin_unlock_irqrestore(&ch->ch_lock, flags);
576 /* Transfer data (if any) from Write Queue -> UART. */
577 neo_copy_data_from_queue_to_uart(ch);
578 } else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
581 spin_lock_irqsave(&ch->ch_lock, flags);
582 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
583 spin_unlock_irqrestore(&ch->ch_lock, flags);
585 /* Transfer data (if any) from Write Queue -> UART. */
586 neo_copy_data_from_queue_to_uart(ch);
593 * Send any/all changes to the line to the UART.
595 static void neo_param(struct tty_struct *tty)
597 unsigned char lcr = 0;
598 unsigned char uart_lcr = 0;
599 unsigned char ier = 0;
600 unsigned char uart_ier = 0;
603 struct dgnc_board *bd;
604 struct channel_t *ch;
607 if (!tty || tty->magic != TTY_MAGIC)
610 un = (struct un_t *) tty->driver_data;
611 if (!un || un->magic != DGNC_UNIT_MAGIC)
615 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
619 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
623 * If baud rate is zero, flush queues, and set mval to drop DTR.
625 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
633 neo_flush_uart_write(ch);
634 neo_flush_uart_read(ch);
636 /* The baudrate is B0 so all modem lines are to be dropped. */
637 ch->ch_flags |= (CH_BAUD0);
638 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
639 neo_assert_modem_signals(ch);
643 } else if (ch->ch_custom_speed) {
645 baud = ch->ch_custom_speed;
646 /* Handle transition from B0 */
647 if (ch->ch_flags & CH_BAUD0) {
648 ch->ch_flags &= ~(CH_BAUD0);
651 * Bring back up RTS and DTR...
652 * Also handle RTS or DTR toggle if set.
654 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
655 ch->ch_mostat |= (UART_MCR_RTS);
656 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
657 ch->ch_mostat |= (UART_MCR_DTR);
663 ulong bauds[4][16] = {
667 600, 1200, 1800, 2400,
668 4800, 9600, 19200, 38400 },
669 { /* slowbaud & CBAUDEX */
670 0, 57600, 115200, 230400,
671 460800, 150, 200, 921600,
672 600, 1200, 1800, 2400,
673 4800, 9600, 19200, 38400 },
675 0, 57600, 76800, 115200,
676 131657, 153600, 230400, 460800,
677 921600, 1200, 1800, 2400,
678 4800, 9600, 19200, 38400 },
679 { /* fastbaud & CBAUDEX */
680 0, 57600, 115200, 230400,
681 460800, 150, 200, 921600,
682 600, 1200, 1800, 2400,
683 4800, 9600, 19200, 38400 }
686 /* Only use the TXPrint baud rate if the terminal unit is NOT open */
687 if (!(ch->ch_tun.un_flags & UN_ISOPEN) && (un->un_type == DGNC_PRINT))
688 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
690 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
692 if (ch->ch_c_cflag & CBAUDEX)
695 if (ch->ch_digi.digi_flags & DIGI_FAST)
700 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && (jindex < 16))
701 baud = bauds[iindex][jindex];
708 /* Handle transition from B0 */
709 if (ch->ch_flags & CH_BAUD0) {
710 ch->ch_flags &= ~(CH_BAUD0);
713 * Bring back up RTS and DTR...
714 * Also handle RTS or DTR toggle if set.
716 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
717 ch->ch_mostat |= (UART_MCR_RTS);
718 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
719 ch->ch_mostat |= (UART_MCR_DTR);
723 if (ch->ch_c_cflag & PARENB)
724 lcr |= UART_LCR_PARITY;
726 if (!(ch->ch_c_cflag & PARODD))
727 lcr |= UART_LCR_EPAR;
730 * Not all platforms support mark/space parity,
731 * so this will hide behind an ifdef.
734 if (ch->ch_c_cflag & CMSPAR)
735 lcr |= UART_LCR_SPAR;
738 if (ch->ch_c_cflag & CSTOPB)
739 lcr |= UART_LCR_STOP;
741 switch (ch->ch_c_cflag & CSIZE) {
743 lcr |= UART_LCR_WLEN5;
746 lcr |= UART_LCR_WLEN6;
749 lcr |= UART_LCR_WLEN7;
753 lcr |= UART_LCR_WLEN8;
757 uart_ier = readb(&ch->ch_neo_uart->ier);
760 uart_lcr = readb(&ch->ch_neo_uart->lcr);
765 quot = ch->ch_bd->bd_dividend / baud;
767 if (quot != 0 && ch->ch_old_baud != baud) {
768 ch->ch_old_baud = baud;
769 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
770 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
771 writeb((quot >> 8), &ch->ch_neo_uart->ier);
772 writeb(lcr, &ch->ch_neo_uart->lcr);
776 writeb(lcr, &ch->ch_neo_uart->lcr);
778 if (ch->ch_c_cflag & CREAD)
779 ier |= (UART_IER_RDI | UART_IER_RLSI);
781 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
784 * Have the UART interrupt on modem signal changes ONLY when
785 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
787 if ((ch->ch_digi.digi_flags & CTSPACE) ||
788 (ch->ch_digi.digi_flags & RTSPACE) ||
789 (ch->ch_c_cflag & CRTSCTS) ||
790 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
791 !(ch->ch_c_cflag & CLOCAL))
794 ier &= ~UART_IER_MSI;
796 ier |= UART_IER_THRI;
799 writeb(ier, &ch->ch_neo_uart->ier);
801 /* Set new start/stop chars */
802 neo_set_new_start_stop_chars(ch);
804 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
805 neo_set_cts_flow_control(ch);
806 } else if (ch->ch_c_iflag & IXON) {
807 /* If start/stop is set to disable, then we should disable flow control */
808 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
809 neo_set_no_output_flow_control(ch);
811 neo_set_ixon_flow_control(ch);
813 neo_set_no_output_flow_control(ch);
816 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
817 neo_set_rts_flow_control(ch);
818 } else if (ch->ch_c_iflag & IXOFF) {
819 /* If start/stop is set to disable, then we should disable flow control */
820 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
821 neo_set_no_input_flow_control(ch);
823 neo_set_ixoff_flow_control(ch);
825 neo_set_no_input_flow_control(ch);
829 * Adjust the RX FIFO Trigger level if baud is less than 9600.
830 * Not exactly elegant, but this is needed because of the Exar chip's
831 * delay on firing off the RX FIFO interrupt on slower baud rates.
834 writeb(1, &ch->ch_neo_uart->rfifo);
838 neo_assert_modem_signals(ch);
840 /* Get current status of the modem signals now */
841 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
846 * Our board poller function.
848 static void neo_tasklet(unsigned long data)
850 struct dgnc_board *bd = (struct dgnc_board *) data;
851 struct channel_t *ch;
857 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
860 /* Cache a couple board values */
861 spin_lock_irqsave(&bd->bd_lock, flags);
864 spin_unlock_irqrestore(&bd->bd_lock, flags);
867 * Do NOT allow the interrupt routine to read the intr registers
868 * Until we release this lock.
870 spin_lock_irqsave(&bd->bd_intr_lock, flags);
873 * If board is ready, parse deeper to see if there is anything to do.
875 if ((state == BOARD_READY) && (ports > 0)) {
876 /* Loop on each port */
877 for (i = 0; i < ports; i++) {
878 ch = bd->channels[i];
880 /* Just being careful... */
881 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
885 * NOTE: Remember you CANNOT hold any channel
886 * locks when calling the input routine.
888 * During input processing, its possible we
889 * will call the Linux ld, which might in turn,
890 * do a callback right back into us, resulting
891 * in us trying to grab the channel lock twice!
896 * Channel lock is grabbed and then released
897 * inside both of these routines, but neither
898 * call anything else that could call back into us.
900 neo_copy_data_from_queue_to_uart(ch);
901 dgnc_wakeup_writes(ch);
904 * Call carrier carrier function, in case something
910 * Check to see if we need to turn off a sending break.
911 * The timing check is done inside clear_break()
913 if (ch->ch_stop_sending_break)
914 neo_clear_break(ch, 0);
918 /* Allow interrupt routine to access the interrupt register again */
919 spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
927 * Neo specific interrupt handler.
929 static irqreturn_t neo_intr(int irq, void *voidbrd)
931 struct dgnc_board *brd = voidbrd;
932 struct channel_t *ch;
939 unsigned long flags2;
942 * Check to make sure it didn't receive interrupt with a null board
943 * associated or a board pointer that wasn't ours.
945 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
950 /* Lock out the slow poller from running on this board. */
951 spin_lock_irqsave(&brd->bd_intr_lock, flags);
954 * Read in "extended" IRQ information from the 32bit Neo register.
955 * Bits 0-7: What port triggered the interrupt.
956 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
958 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
961 * If 0, no interrupts pending.
962 * This can happen if the IRQ is shared among a couple Neo/Classic boards.
965 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
969 /* At this point, we have at least SOMETHING to service, dig further... */
973 /* Loop on each port */
974 while ((uart_poll & 0xff) != 0) {
978 /* Check current port to see if it has interrupt pending */
979 if ((tmp & dgnc_offset_table[current_port]) != 0) {
981 type = tmp >> (8 + (port * 3));
988 /* Remove this port + type from uart_poll */
989 uart_poll &= ~(dgnc_offset_table[port]);
992 /* If no type, just ignore it, and move onto next port */
996 /* Switch on type of interrupt we have */
999 case UART_17158_RXRDY_TIMEOUT:
1001 * RXRDY Time-out is cleared by reading data in the
1002 * RX FIFO until it falls below the trigger level.
1005 /* Verify the port is in range. */
1006 if (port >= brd->nasync)
1009 ch = brd->channels[port];
1010 neo_copy_data_from_uart_to_queue(ch);
1012 /* Call our tty layer to enforce queue flow control if needed. */
1013 spin_lock_irqsave(&ch->ch_lock, flags2);
1014 dgnc_check_queue_flow_control(ch);
1015 spin_unlock_irqrestore(&ch->ch_lock, flags2);
1019 case UART_17158_RX_LINE_STATUS:
1021 * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1023 neo_parse_lsr(brd, port);
1026 case UART_17158_TXRDY:
1028 * TXRDY interrupt clears after reading ISR register for the UART channel.
1032 * Yes, this is odd...
1033 * Why would I check EVERY possibility of type of
1034 * interrupt, when we know its TXRDY???
1035 * Becuz for some reason, even tho we got triggered for TXRDY,
1036 * it seems to be occasionally wrong. Instead of TX, which
1037 * it should be, I was getting things like RXDY too. Weird.
1039 neo_parse_isr(brd, port);
1042 case UART_17158_MSR:
1044 * MSR or flow control was seen.
1046 neo_parse_isr(brd, port);
1051 * The UART triggered us with a bogus interrupt type.
1052 * It appears the Exar chip, when REALLY bogged down, will throw
1053 * these once and awhile.
1054 * Its harmless, just ignore it and move on.
1061 * Schedule tasklet to more in-depth servicing at a better time.
1063 tasklet_schedule(&brd->helper_tasklet);
1065 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
1072 * Neo specific way of turning off the receiver.
1073 * Used as a way to enforce queue flow control when in
1074 * hardware flow control mode.
1076 static void neo_disable_receiver(struct channel_t *ch)
1078 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
1080 tmp &= ~(UART_IER_RDI);
1081 writeb(tmp, &ch->ch_neo_uart->ier);
1082 neo_pci_posting_flush(ch->ch_bd);
1087 * Neo specific way of turning on the receiver.
1088 * Used as a way to un-enforce queue flow control when in
1089 * hardware flow control mode.
1091 static void neo_enable_receiver(struct channel_t *ch)
1093 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
1095 tmp |= (UART_IER_RDI);
1096 writeb(tmp, &ch->ch_neo_uart->ier);
1097 neo_pci_posting_flush(ch->ch_bd);
1101 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch)
1104 unsigned char linestatus = 0;
1105 unsigned char error_mask = 0;
1110 unsigned long flags;
1112 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1115 spin_lock_irqsave(&ch->ch_lock, flags);
1117 /* cache head and tail of queue */
1118 head = ch->ch_r_head & RQUEUEMASK;
1119 tail = ch->ch_r_tail & RQUEUEMASK;
1121 /* Get our cached LSR */
1122 linestatus = ch->ch_cached_lsr;
1123 ch->ch_cached_lsr = 0;
1125 /* Store how much space we have left in the queue */
1126 qleft = tail - head - 1;
1128 qleft += RQUEUEMASK + 1;
1131 * If the UART is not in FIFO mode, force the FIFO copy to
1132 * NOT be run, by setting total to 0.
1134 * On the other hand, if the UART IS in FIFO mode, then ask
1135 * the UART to give us an approximation of data it has RX'ed.
1137 if (!(ch->ch_flags & CH_FIFO_ENABLED))
1140 total = readb(&ch->ch_neo_uart->rfifo);
1143 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
1145 * This resolves a problem/bug with the Exar chip that sometimes
1146 * returns a bogus value in the rfifo register.
1147 * The count can be any where from 0-3 bytes "off".
1148 * Bizarre, but true.
1150 if ((ch->ch_bd->dvid & 0xf0) >= UART_XR17E158_DVID)
1158 * Finally, bound the copy to make sure we don't overflow
1160 * The byte by byte copy loop below this loop this will
1161 * deal with the queue overflow possibility.
1163 total = min(total, qleft);
1168 * Grab the linestatus register, we need to check
1169 * to see if there are any errors in the FIFO.
1171 linestatus = readb(&ch->ch_neo_uart->lsr);
1174 * Break out if there is a FIFO error somewhere.
1175 * This will allow us to go byte by byte down below,
1176 * finding the exact location of the error.
1178 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
1181 /* Make sure we don't go over the end of our queue */
1182 n = min(((uint) total), (RQUEUESIZE - (uint) head));
1185 * Cut down n even further if needed, this is to fix
1186 * a problem with memcpy_fromio() with the Neo on the
1187 * IBM pSeries platform.
1188 * 15 bytes max appears to be the magic number.
1190 n = min_t(uint, n, 12);
1193 * Since we are grabbing the linestatus register, which
1194 * will reset some bits after our read, we need to ensure
1195 * we don't miss our TX FIFO emptys.
1197 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
1198 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1202 /* Copy data from uart to the queue */
1203 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
1206 * Since RX_FIFO_DATA_ERROR was 0, we are guarenteed
1207 * that all the data currently in the FIFO is free of
1208 * breaks and parity/frame/orun errors.
1210 memset(ch->ch_equeue + head, 0, n);
1212 /* Add to and flip head if needed */
1213 head = (head + n) & RQUEUEMASK;
1216 ch->ch_rxcount += n;
1220 * Create a mask to determine whether we should
1221 * insert the character (if any) into our queue.
1223 if (ch->ch_c_iflag & IGNBRK)
1224 error_mask |= UART_LSR_BI;
1227 * Now cleanup any leftover bytes still in the UART.
1228 * Also deal with any possible queue overflow here as well.
1233 * Its possible we have a linestatus from the loop above
1234 * this, so we "OR" on any extra bits.
1236 linestatus |= readb(&ch->ch_neo_uart->lsr);
1239 * If the chip tells us there is no more data pending to
1240 * be read, we can then leave.
1241 * But before we do, cache the linestatus, just in case.
1243 if (!(linestatus & UART_LSR_DR)) {
1244 ch->ch_cached_lsr = linestatus;
1248 /* No need to store this bit */
1249 linestatus &= ~UART_LSR_DR;
1252 * Since we are grabbing the linestatus register, which
1253 * will reset some bits after our read, we need to ensure
1254 * we don't miss our TX FIFO emptys.
1256 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
1257 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
1258 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1262 * Discard character if we are ignoring the error mask.
1264 if (linestatus & error_mask) {
1265 unsigned char discard;
1268 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
1273 * If our queue is full, we have no choice but to drop some data.
1274 * The assumption is that HWFLOW or SWFLOW should have stopped
1275 * things way way before we got to this point.
1277 * I decided that I wanted to ditch the oldest data first,
1278 * I hope thats okay with everyone? Yes? Good.
1281 tail = (tail + 1) & RQUEUEMASK;
1282 ch->ch_r_tail = tail;
1283 ch->ch_err_overrun++;
1287 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
1288 ch->ch_equeue[head] = (unsigned char) linestatus;
1290 /* Ditch any remaining linestatus value. */
1293 /* Add to and flip head if needed */
1294 head = (head + 1) & RQUEUEMASK;
1301 * Write new final heads to channel structure.
1303 ch->ch_r_head = head & RQUEUEMASK;
1304 ch->ch_e_head = head & EQUEUEMASK;
1306 spin_unlock_irqrestore(&ch->ch_lock, flags);
1311 * This function basically goes to sleep for secs, or until
1312 * it gets signalled that the port has fully drained.
1314 static int neo_drain(struct tty_struct *tty, uint seconds)
1316 unsigned long flags;
1317 struct channel_t *ch;
1321 if (!tty || tty->magic != TTY_MAGIC)
1324 un = (struct un_t *) tty->driver_data;
1325 if (!un || un->magic != DGNC_UNIT_MAGIC)
1329 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1332 spin_lock_irqsave(&ch->ch_lock, flags);
1333 un->un_flags |= UN_EMPTY;
1334 spin_unlock_irqrestore(&ch->ch_lock, flags);
1337 * Go to sleep waiting for the tty layer to wake me back up when
1338 * the empty flag goes away.
1340 * NOTE: TODO: Do something with time passed in.
1342 rc = wait_event_interruptible(un->un_flags_wait, ((un->un_flags & UN_EMPTY) == 0));
1344 /* If ret is non-zero, user ctrl-c'ed us */
1350 * Flush the WRITE FIFO on the Neo.
1352 * NOTE: Channel lock MUST be held before calling this function!
1354 static void neo_flush_uart_write(struct channel_t *ch)
1356 unsigned char tmp = 0;
1359 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1362 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1363 neo_pci_posting_flush(ch->ch_bd);
1365 for (i = 0; i < 10; i++) {
1367 /* Check to see if the UART feels it completely flushed the FIFO. */
1368 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1375 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1380 * Flush the READ FIFO on the Neo.
1382 * NOTE: Channel lock MUST be held before calling this function!
1384 static void neo_flush_uart_read(struct channel_t *ch)
1386 unsigned char tmp = 0;
1389 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1392 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
1393 neo_pci_posting_flush(ch->ch_bd);
1395 for (i = 0; i < 10; i++) {
1397 /* Check to see if the UART feels it completely flushed the FIFO. */
1398 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1407 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch)
1414 uint len_written = 0;
1415 unsigned long flags;
1417 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1420 spin_lock_irqsave(&ch->ch_lock, flags);
1422 /* No data to write to the UART */
1423 if (ch->ch_w_tail == ch->ch_w_head)
1426 /* If port is "stopped", don't send any data to the UART */
1427 if ((ch->ch_flags & CH_FORCED_STOP) ||
1428 (ch->ch_flags & CH_BREAK_SENDING))
1432 * If FIFOs are disabled. Send data directly to txrx register
1434 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1435 unsigned char lsrbits = readb(&ch->ch_neo_uart->lsr);
1437 /* Cache the LSR bits for later parsing */
1438 ch->ch_cached_lsr |= lsrbits;
1439 if (ch->ch_cached_lsr & UART_LSR_THRE) {
1440 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
1443 * If RTS Toggle mode is on, turn on RTS now if not already set,
1444 * and make sure we get an event when the data transfer has completed.
1446 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1447 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1448 ch->ch_mostat |= (UART_MCR_RTS);
1449 neo_assert_modem_signals(ch);
1451 ch->ch_tun.un_flags |= (UN_EMPTY);
1454 * If DTR Toggle mode is on, turn on DTR now if not already set,
1455 * and make sure we get an event when the data transfer has completed.
1457 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1458 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1459 ch->ch_mostat |= (UART_MCR_DTR);
1460 neo_assert_modem_signals(ch);
1462 ch->ch_tun.un_flags |= (UN_EMPTY);
1465 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx);
1467 ch->ch_w_tail &= WQUEUEMASK;
1475 * We have to do it this way, because of the EXAR TXFIFO count bug.
1477 if ((ch->ch_bd->dvid & 0xf0) < UART_XR17E158_DVID) {
1478 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
1483 n = readb(&ch->ch_neo_uart->tfifo);
1485 if ((unsigned int) n > ch->ch_t_tlevel)
1488 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
1490 n = UART_17158_TX_FIFOSIZE - readb(&ch->ch_neo_uart->tfifo);
1493 /* cache head and tail of queue */
1494 head = ch->ch_w_head & WQUEUEMASK;
1495 tail = ch->ch_w_tail & WQUEUEMASK;
1496 qlen = (head - tail) & WQUEUEMASK;
1498 /* Find minimum of the FIFO space, versus queue length */
1503 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
1510 * If RTS Toggle mode is on, turn on RTS now if not already set,
1511 * and make sure we get an event when the data transfer has completed.
1513 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1514 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1515 ch->ch_mostat |= (UART_MCR_RTS);
1516 neo_assert_modem_signals(ch);
1518 ch->ch_tun.un_flags |= (UN_EMPTY);
1522 * If DTR Toggle mode is on, turn on DTR now if not already set,
1523 * and make sure we get an event when the data transfer has completed.
1525 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1526 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1527 ch->ch_mostat |= (UART_MCR_DTR);
1528 neo_assert_modem_signals(ch);
1530 ch->ch_tun.un_flags |= (UN_EMPTY);
1533 memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s);
1535 /* Add and flip queue if needed */
1536 tail = (tail + s) & WQUEUEMASK;
1538 ch->ch_txcount += s;
1542 /* Update the final tail */
1543 ch->ch_w_tail = tail & WQUEUEMASK;
1545 if (len_written > 0) {
1546 neo_pci_posting_flush(ch->ch_bd);
1547 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1551 spin_unlock_irqrestore(&ch->ch_lock, flags);
1555 static void neo_parse_modem(struct channel_t *ch, unsigned char signals)
1557 unsigned char msignals = signals;
1559 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1563 * Do altpin switching. Altpin switches DCD and DSR.
1564 * This prolly breaks DSRPACE, so we should be more clever here.
1566 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1567 unsigned char mswap = msignals;
1569 if (mswap & UART_MSR_DDCD) {
1570 msignals &= ~UART_MSR_DDCD;
1571 msignals |= UART_MSR_DDSR;
1573 if (mswap & UART_MSR_DDSR) {
1574 msignals &= ~UART_MSR_DDSR;
1575 msignals |= UART_MSR_DDCD;
1577 if (mswap & UART_MSR_DCD) {
1578 msignals &= ~UART_MSR_DCD;
1579 msignals |= UART_MSR_DSR;
1581 if (mswap & UART_MSR_DSR) {
1582 msignals &= ~UART_MSR_DSR;
1583 msignals |= UART_MSR_DCD;
1587 /* Scrub off lower bits. They signify delta's, which I don't care about */
1590 if (msignals & UART_MSR_DCD)
1591 ch->ch_mistat |= UART_MSR_DCD;
1593 ch->ch_mistat &= ~UART_MSR_DCD;
1595 if (msignals & UART_MSR_DSR)
1596 ch->ch_mistat |= UART_MSR_DSR;
1598 ch->ch_mistat &= ~UART_MSR_DSR;
1600 if (msignals & UART_MSR_RI)
1601 ch->ch_mistat |= UART_MSR_RI;
1603 ch->ch_mistat &= ~UART_MSR_RI;
1605 if (msignals & UART_MSR_CTS)
1606 ch->ch_mistat |= UART_MSR_CTS;
1608 ch->ch_mistat &= ~UART_MSR_CTS;
1612 /* Make the UART raise any of the output signals we want up */
1613 static void neo_assert_modem_signals(struct channel_t *ch)
1617 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1620 out = ch->ch_mostat;
1622 if (ch->ch_flags & CH_LOOPBACK)
1623 out |= UART_MCR_LOOP;
1625 writeb(out, &ch->ch_neo_uart->mcr);
1626 neo_pci_posting_flush(ch->ch_bd);
1628 /* Give time for the UART to actually raise/drop the signals */
1633 static void neo_send_start_character(struct channel_t *ch)
1635 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1638 if (ch->ch_startc != _POSIX_VDISABLE) {
1640 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1641 neo_pci_posting_flush(ch->ch_bd);
1647 static void neo_send_stop_character(struct channel_t *ch)
1649 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1652 if (ch->ch_stopc != _POSIX_VDISABLE) {
1653 ch->ch_xoff_sends++;
1654 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1655 neo_pci_posting_flush(ch->ch_bd);
1664 static void neo_uart_init(struct channel_t *ch)
1667 writeb(0, &ch->ch_neo_uart->ier);
1668 writeb(0, &ch->ch_neo_uart->efr);
1669 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1672 /* Clear out UART and FIFO */
1673 readb(&ch->ch_neo_uart->txrx);
1674 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1675 readb(&ch->ch_neo_uart->lsr);
1676 readb(&ch->ch_neo_uart->msr);
1678 ch->ch_flags |= CH_FIFO_ENABLED;
1680 /* Assert any signals we want up */
1681 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1682 neo_pci_posting_flush(ch->ch_bd);
1687 * Make the UART completely turn off.
1689 static void neo_uart_off(struct channel_t *ch)
1691 /* Turn off UART enhanced bits */
1692 writeb(0, &ch->ch_neo_uart->efr);
1694 /* Stop all interrupts from occurring. */
1695 writeb(0, &ch->ch_neo_uart->ier);
1696 neo_pci_posting_flush(ch->ch_bd);
1700 static uint neo_get_uart_bytes_left(struct channel_t *ch)
1702 unsigned char left = 0;
1703 unsigned char lsr = readb(&ch->ch_neo_uart->lsr);
1705 /* We must cache the LSR as some of the bits get reset once read... */
1706 ch->ch_cached_lsr |= lsr;
1708 /* Determine whether the Transmitter is empty or not */
1709 if (!(lsr & UART_LSR_TEMT)) {
1710 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1711 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1714 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1722 /* Channel lock MUST be held by the calling function! */
1723 static void neo_send_break(struct channel_t *ch, int msecs)
1726 * If we receive a time of 0, this means turn off the break.
1729 if (ch->ch_flags & CH_BREAK_SENDING) {
1730 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1732 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1733 neo_pci_posting_flush(ch->ch_bd);
1734 ch->ch_flags &= ~(CH_BREAK_SENDING);
1735 ch->ch_stop_sending_break = 0;
1741 * Set the time we should stop sending the break.
1742 * If we are already sending a break, toss away the existing
1743 * time to stop, and use this new value instead.
1745 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1747 /* Tell the UART to start sending the break */
1748 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1749 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1751 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1752 neo_pci_posting_flush(ch->ch_bd);
1753 ch->ch_flags |= (CH_BREAK_SENDING);
1759 * neo_send_immediate_char.
1761 * Sends a specific character as soon as possible to the UART,
1762 * jumping over any bytes that might be in the write queue.
1764 * The channel lock MUST be held by the calling function.
1766 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c)
1768 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1771 writeb(c, &ch->ch_neo_uart->txrx);
1772 neo_pci_posting_flush(ch->ch_bd);
1776 static unsigned int neo_read_eeprom(unsigned char __iomem *base, unsigned int address)
1778 unsigned int enable;
1780 unsigned int databit;
1783 /* enable chip select */
1784 writeb(NEO_EECS, base + NEO_EEREG);
1786 enable = (address | 0x180);
1788 for (bits = 9; bits--; ) {
1789 databit = (enable & (1 << bits)) ? NEO_EEDI : 0;
1790 /* Set read address */
1791 writeb(databit | NEO_EECS, base + NEO_EEREG);
1792 writeb(databit | NEO_EECS | NEO_EECK, base + NEO_EEREG);
1797 for (bits = 17; bits--; ) {
1798 /* clock to EEPROM */
1799 writeb(NEO_EECS, base + NEO_EEREG);
1800 writeb(NEO_EECS | NEO_EECK, base + NEO_EEREG);
1803 if (readb(base + NEO_EEREG) & NEO_EEDO)
1807 /* clock falling edge */
1808 writeb(NEO_EECS, base + NEO_EEREG);
1810 /* drop chip select */
1811 writeb(0x00, base + NEO_EEREG);
1817 static void neo_vpd(struct dgnc_board *brd)
1822 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
1825 if (!brd->re_map_membase)
1828 /* Store the VPD into our buffer */
1829 for (i = 0; i < NEO_VPD_IMAGESIZE; i++) {
1830 a = neo_read_eeprom(brd->re_map_membase, i);
1831 brd->vpd[i*2] = a & 0xff;
1832 brd->vpd[(i*2)+1] = (a >> 8) & 0xff;
1835 if (((brd->vpd[0x08] != 0x82) /* long resource name tag */
1836 && (brd->vpd[0x10] != 0x82)) /* long resource name tag (PCI-66 files)*/
1837 || (brd->vpd[0x7F] != 0x78)) { /* small resource end tag */
1839 memset(brd->vpd, '\0', NEO_VPD_IMAGESIZE);
1841 /* Search for the serial number */
1842 for (i = 0; i < NEO_VPD_IMAGEBYTES - 3; i++)
1843 if (brd->vpd[i] == 'S' && brd->vpd[i + 1] == 'N')
1844 strncpy(brd->serial_num, &(brd->vpd[i + 3]), 9);