2 comedi/drivers/ni_atmio16d.c
3 Hardware driver for National Instruments AT-MIO16D board
4 Copyright (C) 2000 Chris R. Baugher <baugher@enteract.com>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
18 Description: National Instruments AT-MIO-16D
19 Author: Chris R. Baugher <baugher@enteract.com>
21 Devices: [National Instruments] AT-MIO-16 (atmio16), AT-MIO-16D (atmio16d)
24 * I must give credit here to Michal Dobes <dobes@tesnet.cz> who
25 * wrote the driver for Advantec's pcl812 boards. I used the interrupt
26 * handling code from his driver as an example for this one.
33 #include <linux/module.h>
34 #include <linux/interrupt.h>
35 #include "../comedidev.h"
39 /* Configuration and Status Registers */
40 #define COM_REG_1 0x00 /* wo 16 */
41 #define STAT_REG 0x00 /* ro 16 */
42 #define COM_REG_2 0x02 /* wo 16 */
43 /* Event Strobe Registers */
44 #define START_CONVERT_REG 0x08 /* wo 16 */
45 #define START_DAQ_REG 0x0A /* wo 16 */
46 #define AD_CLEAR_REG 0x0C /* wo 16 */
47 #define EXT_STROBE_REG 0x0E /* wo 16 */
48 /* Analog Output Registers */
49 #define DAC0_REG 0x10 /* wo 16 */
50 #define DAC1_REG 0x12 /* wo 16 */
51 #define INT2CLR_REG 0x14 /* wo 16 */
52 /* Analog Input Registers */
53 #define MUX_CNTR_REG 0x04 /* wo 16 */
54 #define MUX_GAIN_REG 0x06 /* wo 16 */
55 #define AD_FIFO_REG 0x16 /* ro 16 */
56 #define DMA_TC_INT_CLR_REG 0x16 /* wo 16 */
57 /* AM9513A Counter/Timer Registers */
58 #define AM9513A_DATA_REG 0x18 /* rw 16 */
59 #define AM9513A_COM_REG 0x1A /* wo 16 */
60 #define AM9513A_STAT_REG 0x1A /* ro 16 */
61 /* MIO-16 Digital I/O Registers */
62 #define MIO_16_DIG_IN_REG 0x1C /* ro 16 */
63 #define MIO_16_DIG_OUT_REG 0x1C /* wo 16 */
64 /* RTSI Switch Registers */
65 #define RTSI_SW_SHIFT_REG 0x1E /* wo 8 */
66 #define RTSI_SW_STROBE_REG 0x1F /* wo 8 */
67 /* DIO-24 Registers */
68 #define DIO_24_PORTA_REG 0x00 /* rw 8 */
69 #define DIO_24_PORTB_REG 0x01 /* rw 8 */
70 #define DIO_24_PORTC_REG 0x02 /* rw 8 */
71 #define DIO_24_CNFG_REG 0x03 /* wo 8 */
73 /* Command Register bits */
74 #define COMREG1_2SCADC 0x0001
75 #define COMREG1_1632CNT 0x0002
76 #define COMREG1_SCANEN 0x0008
77 #define COMREG1_DAQEN 0x0010
78 #define COMREG1_DMAEN 0x0020
79 #define COMREG1_CONVINTEN 0x0080
80 #define COMREG2_SCN2 0x0010
81 #define COMREG2_INTEN 0x0080
82 #define COMREG2_DOUTEN0 0x0100
83 #define COMREG2_DOUTEN1 0x0200
84 /* Status Register bits */
85 #define STAT_AD_OVERRUN 0x0100
86 #define STAT_AD_OVERFLOW 0x0200
87 #define STAT_AD_DAQPROG 0x0800
88 #define STAT_AD_CONVAVAIL 0x2000
89 #define STAT_AD_DAQSTOPINT 0x4000
90 /* AM9513A Counter/Timer defines */
91 #define CLOCK_1_MHZ 0x8B25
92 #define CLOCK_100_KHZ 0x8C25
93 #define CLOCK_10_KHZ 0x8D25
94 #define CLOCK_1_KHZ 0x8E25
95 #define CLOCK_100_HZ 0x8F25
97 struct atmio16_board_t {
103 static const struct comedi_lrange range_atmio16d_ai_10_bipolar = {
112 static const struct comedi_lrange range_atmio16d_ai_5_bipolar = {
121 static const struct comedi_lrange range_atmio16d_ai_unipolar = {
130 /* private data struct */
131 struct atmio16d_private {
132 enum { adc_diff, adc_singleended } adc_mux;
133 enum { adc_bipolar10, adc_bipolar5, adc_unipolar10 } adc_range;
134 enum { adc_2comp, adc_straight } adc_coding;
135 enum { dac_bipolar, dac_unipolar } dac0_range, dac1_range;
136 enum { dac_internal, dac_external } dac0_reference, dac1_reference;
137 enum { dac_2comp, dac_straight } dac0_coding, dac1_coding;
138 const struct comedi_lrange *ao_range_type_list[2];
139 unsigned int com_reg_1_state; /* current state of command register 1 */
140 unsigned int com_reg_2_state; /* current state of command register 2 */
143 static void reset_counters(struct comedi_device *dev)
146 outw(0xFFC2, dev->iobase + AM9513A_COM_REG);
147 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
148 outw(0x4, dev->iobase + AM9513A_DATA_REG);
149 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
150 outw(0x3, dev->iobase + AM9513A_DATA_REG);
151 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
152 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
154 outw(0xFFC4, dev->iobase + AM9513A_COM_REG);
155 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
156 outw(0x4, dev->iobase + AM9513A_DATA_REG);
157 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
158 outw(0x3, dev->iobase + AM9513A_DATA_REG);
159 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
160 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
162 outw(0xFFC8, dev->iobase + AM9513A_COM_REG);
163 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
164 outw(0x4, dev->iobase + AM9513A_DATA_REG);
165 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
166 outw(0x3, dev->iobase + AM9513A_DATA_REG);
167 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
168 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
170 outw(0xFFD0, dev->iobase + AM9513A_COM_REG);
171 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
172 outw(0x4, dev->iobase + AM9513A_DATA_REG);
173 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
174 outw(0x3, dev->iobase + AM9513A_DATA_REG);
175 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
176 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
178 outw(0, dev->iobase + AD_CLEAR_REG);
181 static void reset_atmio16d(struct comedi_device *dev)
183 struct atmio16d_private *devpriv = dev->private;
186 /* now we need to initialize the board */
187 outw(0, dev->iobase + COM_REG_1);
188 outw(0, dev->iobase + COM_REG_2);
189 outw(0, dev->iobase + MUX_GAIN_REG);
190 /* init AM9513A timer */
191 outw(0xFFFF, dev->iobase + AM9513A_COM_REG);
192 outw(0xFFEF, dev->iobase + AM9513A_COM_REG);
193 outw(0xFF17, dev->iobase + AM9513A_COM_REG);
194 outw(0xF000, dev->iobase + AM9513A_DATA_REG);
195 for (i = 1; i <= 5; ++i) {
196 outw(0xFF00 + i, dev->iobase + AM9513A_COM_REG);
197 outw(0x0004, dev->iobase + AM9513A_DATA_REG);
198 outw(0xFF08 + i, dev->iobase + AM9513A_COM_REG);
199 outw(0x3, dev->iobase + AM9513A_DATA_REG);
201 outw(0xFF5F, dev->iobase + AM9513A_COM_REG);
202 /* timer init done */
203 outw(0, dev->iobase + AD_CLEAR_REG);
204 outw(0, dev->iobase + INT2CLR_REG);
205 /* select straight binary mode for Analog Input */
206 devpriv->com_reg_1_state |= 1;
207 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
208 devpriv->adc_coding = adc_straight;
209 /* zero the analog outputs */
210 outw(2048, dev->iobase + DAC0_REG);
211 outw(2048, dev->iobase + DAC1_REG);
214 static irqreturn_t atmio16d_interrupt(int irq, void *d)
216 struct comedi_device *dev = d;
217 struct comedi_subdevice *s = dev->read_subdev;
220 val = inw(dev->iobase + AD_FIFO_REG);
221 comedi_buf_write_samples(s, &val, 1);
222 comedi_handle_events(dev, s);
227 static int atmio16d_ai_cmdtest(struct comedi_device *dev,
228 struct comedi_subdevice *s,
229 struct comedi_cmd *cmd)
233 /* Step 1 : check if triggers are trivially valid */
235 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
236 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
237 TRIG_FOLLOW | TRIG_TIMER);
238 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_TIMER);
239 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
240 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
245 /* Step 2a : make sure trigger sources are unique */
247 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
248 err |= comedi_check_trigger_is_unique(cmd->stop_src);
250 /* Step 2b : and mutually compatible */
255 /* Step 3: check if arguments are trivially valid */
257 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
259 if (cmd->scan_begin_src == TRIG_FOLLOW) {
260 /* internal trigger */
261 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
264 /* external trigger */
265 /* should be level/edge, hi/lo specification here */
266 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
270 err |= comedi_check_trigger_arg_min(&cmd->convert_arg, 10000);
272 err |= comedi_check_trigger_arg_max(&cmd->convert_arg, SLOWEST_TIMER);
275 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
278 if (cmd->stop_src == TRIG_COUNT)
279 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
281 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
289 static int atmio16d_ai_cmd(struct comedi_device *dev,
290 struct comedi_subdevice *s)
292 struct atmio16d_private *devpriv = dev->private;
293 struct comedi_cmd *cmd = &s->async->cmd;
294 unsigned int timer, base_clock;
295 unsigned int sample_count, tmp, chan, gain;
298 /* This is slowly becoming a working command interface. *
299 * It is still uber-experimental */
303 /* check if scanning multiple channels */
304 if (cmd->chanlist_len < 2) {
305 devpriv->com_reg_1_state &= ~COMREG1_SCANEN;
306 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
308 devpriv->com_reg_1_state |= COMREG1_SCANEN;
309 devpriv->com_reg_2_state |= COMREG2_SCN2;
310 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
311 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
314 /* Setup the Mux-Gain Counter */
315 for (i = 0; i < cmd->chanlist_len; ++i) {
316 chan = CR_CHAN(cmd->chanlist[i]);
317 gain = CR_RANGE(cmd->chanlist[i]);
318 outw(i, dev->iobase + MUX_CNTR_REG);
319 tmp = chan | (gain << 6);
320 if (i == cmd->scan_end_arg - 1)
321 tmp |= 0x0010; /* set LASTONE bit */
322 outw(tmp, dev->iobase + MUX_GAIN_REG);
325 /* Now program the sample interval timer */
326 /* Figure out which clock to use then get an
327 * appropriate timer value */
328 if (cmd->convert_arg < 65536000) {
329 base_clock = CLOCK_1_MHZ;
330 timer = cmd->convert_arg / 1000;
331 } else if (cmd->convert_arg < 655360000) {
332 base_clock = CLOCK_100_KHZ;
333 timer = cmd->convert_arg / 10000;
334 } else /* cmd->convert_arg < 6553600000 */ {
335 base_clock = CLOCK_10_KHZ;
336 timer = cmd->convert_arg / 100000;
338 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
339 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
340 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
341 outw(0x2, dev->iobase + AM9513A_DATA_REG);
342 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
343 outw(0xFFF3, dev->iobase + AM9513A_COM_REG);
344 outw(timer, dev->iobase + AM9513A_DATA_REG);
345 outw(0xFF24, dev->iobase + AM9513A_COM_REG);
347 /* Now figure out how many samples to get */
348 /* and program the sample counter */
349 sample_count = cmd->stop_arg * cmd->scan_end_arg;
350 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
351 outw(0x1025, dev->iobase + AM9513A_DATA_REG);
352 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
353 if (sample_count < 65536) {
354 /* use only Counter 4 */
355 outw(sample_count, dev->iobase + AM9513A_DATA_REG);
356 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
357 outw(0xFFF4, dev->iobase + AM9513A_COM_REG);
358 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
359 devpriv->com_reg_1_state &= ~COMREG1_1632CNT;
360 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
362 /* Counter 4 and 5 are needed */
364 tmp = sample_count & 0xFFFF;
366 outw(tmp - 1, dev->iobase + AM9513A_DATA_REG);
368 outw(0xFFFF, dev->iobase + AM9513A_DATA_REG);
370 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
371 outw(0, dev->iobase + AM9513A_DATA_REG);
372 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
373 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
374 outw(0x25, dev->iobase + AM9513A_DATA_REG);
375 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
376 tmp = sample_count & 0xFFFF;
377 if ((tmp == 0) || (tmp == 1)) {
378 outw((sample_count >> 16) & 0xFFFF,
379 dev->iobase + AM9513A_DATA_REG);
381 outw(((sample_count >> 16) & 0xFFFF) + 1,
382 dev->iobase + AM9513A_DATA_REG);
384 outw(0xFF70, dev->iobase + AM9513A_COM_REG);
385 devpriv->com_reg_1_state |= COMREG1_1632CNT;
386 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
389 /* Program the scan interval timer ONLY IF SCANNING IS ENABLED */
390 /* Figure out which clock to use then get an
391 * appropriate timer value */
392 if (cmd->chanlist_len > 1) {
393 if (cmd->scan_begin_arg < 65536000) {
394 base_clock = CLOCK_1_MHZ;
395 timer = cmd->scan_begin_arg / 1000;
396 } else if (cmd->scan_begin_arg < 655360000) {
397 base_clock = CLOCK_100_KHZ;
398 timer = cmd->scan_begin_arg / 10000;
399 } else /* cmd->scan_begin_arg < 6553600000 */ {
400 base_clock = CLOCK_10_KHZ;
401 timer = cmd->scan_begin_arg / 100000;
403 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
404 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
405 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
406 outw(0x2, dev->iobase + AM9513A_DATA_REG);
407 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
408 outw(0xFFF2, dev->iobase + AM9513A_COM_REG);
409 outw(timer, dev->iobase + AM9513A_DATA_REG);
410 outw(0xFF22, dev->iobase + AM9513A_COM_REG);
413 /* Clear the A/D FIFO and reset the MUX counter */
414 outw(0, dev->iobase + AD_CLEAR_REG);
415 outw(0, dev->iobase + MUX_CNTR_REG);
416 outw(0, dev->iobase + INT2CLR_REG);
417 /* enable this acquisition operation */
418 devpriv->com_reg_1_state |= COMREG1_DAQEN;
419 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
420 /* enable interrupts for conversion completion */
421 devpriv->com_reg_1_state |= COMREG1_CONVINTEN;
422 devpriv->com_reg_2_state |= COMREG2_INTEN;
423 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
424 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
425 /* apply a trigger. this starts the counters! */
426 outw(0, dev->iobase + START_DAQ_REG);
431 /* This will cancel a running acquisition operation */
432 static int atmio16d_ai_cancel(struct comedi_device *dev,
433 struct comedi_subdevice *s)
440 static int atmio16d_ai_eoc(struct comedi_device *dev,
441 struct comedi_subdevice *s,
442 struct comedi_insn *insn,
443 unsigned long context)
447 status = inw(dev->iobase + STAT_REG);
448 if (status & STAT_AD_CONVAVAIL)
450 if (status & STAT_AD_OVERFLOW) {
451 outw(0, dev->iobase + AD_CLEAR_REG);
457 static int atmio16d_ai_insn_read(struct comedi_device *dev,
458 struct comedi_subdevice *s,
459 struct comedi_insn *insn, unsigned int *data)
461 struct atmio16d_private *devpriv = dev->private;
467 chan = CR_CHAN(insn->chanspec);
468 gain = CR_RANGE(insn->chanspec);
470 /* reset the Analog input circuitry */
471 /* outw( 0, dev->iobase+AD_CLEAR_REG ); */
472 /* reset the Analog Input MUX Counter to 0 */
473 /* outw( 0, dev->iobase+MUX_CNTR_REG ); */
475 /* set the Input MUX gain */
476 outw(chan | (gain << 6), dev->iobase + MUX_GAIN_REG);
478 for (i = 0; i < insn->n; i++) {
479 /* start the conversion */
480 outw(0, dev->iobase + START_CONVERT_REG);
482 /* wait for it to finish */
483 ret = comedi_timeout(dev, s, insn, atmio16d_ai_eoc, 0);
487 /* read the data now */
488 data[i] = inw(dev->iobase + AD_FIFO_REG);
489 /* change to two's complement if need be */
490 if (devpriv->adc_coding == adc_2comp)
497 static int atmio16d_ao_insn_write(struct comedi_device *dev,
498 struct comedi_subdevice *s,
499 struct comedi_insn *insn,
502 struct atmio16d_private *devpriv = dev->private;
503 unsigned int chan = CR_CHAN(insn->chanspec);
504 unsigned int reg = (chan) ? DAC1_REG : DAC0_REG;
508 if (chan == 0 && devpriv->dac0_coding == dac_2comp)
510 if (chan == 1 && devpriv->dac1_coding == dac_2comp)
513 for (i = 0; i < insn->n; i++) {
514 unsigned int val = data[i];
516 s->readback[chan] = val;
521 outw(val, dev->iobase + reg);
527 static int atmio16d_dio_insn_bits(struct comedi_device *dev,
528 struct comedi_subdevice *s,
529 struct comedi_insn *insn,
532 if (comedi_dio_update_state(s, data))
533 outw(s->state, dev->iobase + MIO_16_DIG_OUT_REG);
535 data[1] = inw(dev->iobase + MIO_16_DIG_IN_REG);
540 static int atmio16d_dio_insn_config(struct comedi_device *dev,
541 struct comedi_subdevice *s,
542 struct comedi_insn *insn,
545 struct atmio16d_private *devpriv = dev->private;
546 unsigned int chan = CR_CHAN(insn->chanspec);
555 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
559 devpriv->com_reg_2_state &= ~(COMREG2_DOUTEN0 | COMREG2_DOUTEN1);
560 if (s->io_bits & 0x0f)
561 devpriv->com_reg_2_state |= COMREG2_DOUTEN0;
562 if (s->io_bits & 0xf0)
563 devpriv->com_reg_2_state |= COMREG2_DOUTEN1;
564 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
570 options[0] - I/O port
573 N == irq N {3,4,5,6,7,9,10,11,12,14,15}
576 N == irq N {3,4,5,6,7,9}
577 options[3] - DMA1 channel
580 options[4] - DMA2 channel
585 0=differential, 1=single
586 options[6] - a/d range
587 0=bipolar10, 1=bipolar5, 2=unipolar10
589 options[7] - dac0 range
590 0=bipolar, 1=unipolar
591 options[8] - dac0 reference
592 0=internal, 1=external
593 options[9] - dac0 coding
594 0=2's comp, 1=straight binary
596 options[10] - dac1 range
597 options[11] - dac1 reference
598 options[12] - dac1 coding
601 static int atmio16d_attach(struct comedi_device *dev,
602 struct comedi_devconfig *it)
604 const struct atmio16_board_t *board = dev->board_ptr;
605 struct atmio16d_private *devpriv;
606 struct comedi_subdevice *s;
609 ret = comedi_request_region(dev, it->options[0], 0x20);
613 ret = comedi_alloc_subdevices(dev, 4);
617 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
621 /* reset the atmio16d hardware */
624 if (it->options[1]) {
625 ret = request_irq(it->options[1], atmio16d_interrupt, 0,
626 dev->board_name, dev);
628 dev->irq = it->options[1];
631 /* set device options */
632 devpriv->adc_mux = it->options[5];
633 devpriv->adc_range = it->options[6];
635 devpriv->dac0_range = it->options[7];
636 devpriv->dac0_reference = it->options[8];
637 devpriv->dac0_coding = it->options[9];
638 devpriv->dac1_range = it->options[10];
639 devpriv->dac1_reference = it->options[11];
640 devpriv->dac1_coding = it->options[12];
642 /* setup sub-devices */
643 s = &dev->subdevices[0];
645 s->type = COMEDI_SUBD_AI;
646 s->subdev_flags = SDF_READABLE | SDF_GROUND;
647 s->n_chan = (devpriv->adc_mux ? 16 : 8);
648 s->insn_read = atmio16d_ai_insn_read;
649 s->maxdata = 0xfff; /* 4095 decimal */
650 switch (devpriv->adc_range) {
652 s->range_table = &range_atmio16d_ai_10_bipolar;
655 s->range_table = &range_atmio16d_ai_5_bipolar;
658 s->range_table = &range_atmio16d_ai_unipolar;
662 dev->read_subdev = s;
663 s->subdev_flags |= SDF_CMD_READ;
664 s->len_chanlist = 16;
665 s->do_cmdtest = atmio16d_ai_cmdtest;
666 s->do_cmd = atmio16d_ai_cmd;
667 s->cancel = atmio16d_ai_cancel;
671 s = &dev->subdevices[1];
672 s->type = COMEDI_SUBD_AO;
673 s->subdev_flags = SDF_WRITABLE;
675 s->maxdata = 0xfff; /* 4095 decimal */
676 s->range_table_list = devpriv->ao_range_type_list;
677 switch (devpriv->dac0_range) {
679 devpriv->ao_range_type_list[0] = &range_bipolar10;
682 devpriv->ao_range_type_list[0] = &range_unipolar10;
685 switch (devpriv->dac1_range) {
687 devpriv->ao_range_type_list[1] = &range_bipolar10;
690 devpriv->ao_range_type_list[1] = &range_unipolar10;
693 s->insn_write = atmio16d_ao_insn_write;
695 ret = comedi_alloc_subdev_readback(s);
700 s = &dev->subdevices[2];
701 s->type = COMEDI_SUBD_DIO;
702 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
704 s->insn_bits = atmio16d_dio_insn_bits;
705 s->insn_config = atmio16d_dio_insn_config;
707 s->range_table = &range_digital;
710 s = &dev->subdevices[3];
711 if (board->has_8255) {
712 ret = subdev_8255_init(dev, s, NULL, 0x00);
716 s->type = COMEDI_SUBD_UNUSED;
719 /* don't yet know how to deal with counter/timers */
721 s = &dev->subdevices[4];
723 s->type = COMEDI_SUBD_TIMER;
731 static void atmio16d_detach(struct comedi_device *dev)
734 comedi_legacy_detach(dev);
737 static const struct atmio16_board_t atmio16_boards[] = {
747 static struct comedi_driver atmio16d_driver = {
748 .driver_name = "atmio16",
749 .module = THIS_MODULE,
750 .attach = atmio16d_attach,
751 .detach = atmio16d_detach,
752 .board_name = &atmio16_boards[0].name,
753 .num_names = ARRAY_SIZE(atmio16_boards),
754 .offset = sizeof(struct atmio16_board_t),
756 module_comedi_driver(atmio16d_driver);
758 MODULE_AUTHOR("Comedi http://www.comedi.org");
759 MODULE_DESCRIPTION("Comedi low-level driver");
760 MODULE_LICENSE("GPL");