2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/bitops.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/ioport.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/pci.h>
26 #include <linux/platform_device.h>
27 #include <linux/spi/pxa2xx_spi.h>
28 #include <linux/spi/spi.h>
29 #include <linux/delay.h>
30 #include <linux/gpio.h>
31 #include <linux/slab.h>
32 #include <linux/clk.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/acpi.h>
36 #include "spi-pxa2xx.h"
38 MODULE_AUTHOR("Stephen Street");
39 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
40 MODULE_LICENSE("GPL");
41 MODULE_ALIAS("platform:pxa2xx-spi");
43 #define TIMOUT_DFLT 1000
46 * for testing SSCR1 changes that require SSP restart, basically
47 * everything except the service and interrupt enables, the pxa270 developer
48 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
49 * list, but the PXA255 dev man says all bits without really meaning the
50 * service and interrupt enables
52 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
53 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
54 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
55 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
56 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
57 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
59 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
60 | QUARK_X1000_SSCR1_EFWR \
61 | QUARK_X1000_SSCR1_RFT \
62 | QUARK_X1000_SSCR1_TFT \
63 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
65 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
66 #define LPSS_CS_CONTROL_SW_MODE BIT(0)
67 #define LPSS_CS_CONTROL_CS_HIGH BIT(1)
68 #define LPSS_CS_CONTROL_CS_SEL_SHIFT 8
69 #define LPSS_CS_CONTROL_CS_SEL_MASK (3 << LPSS_CS_CONTROL_CS_SEL_SHIFT)
70 #define LPSS_CAPS_CS_EN_SHIFT 9
71 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
74 /* LPSS offset from drv_data->ioaddr */
76 /* Register offsets from drv_data->lpss_base or -1 */
87 /* Keep these sorted with enum pxa_ssp_type */
88 static const struct lpss_config lpss_platforms[] = {
94 .reg_capabilities = -1,
96 .tx_threshold_lo = 160,
97 .tx_threshold_hi = 224,
104 .reg_capabilities = -1,
106 .tx_threshold_lo = 160,
107 .tx_threshold_hi = 224,
114 .reg_capabilities = -1,
116 .tx_threshold_lo = 32,
117 .tx_threshold_hi = 56,
124 .reg_capabilities = 0xfc,
126 .tx_threshold_lo = 16,
127 .tx_threshold_hi = 48,
131 static inline const struct lpss_config
132 *lpss_get_config(const struct driver_data *drv_data)
134 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
137 static bool is_lpss_ssp(const struct driver_data *drv_data)
139 switch (drv_data->ssp_type) {
150 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
152 return drv_data->ssp_type == QUARK_X1000_SSP;
155 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
157 switch (drv_data->ssp_type) {
158 case QUARK_X1000_SSP:
159 return QUARK_X1000_SSCR1_CHANGE_MASK;
161 return SSCR1_CHANGE_MASK;
166 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
168 switch (drv_data->ssp_type) {
169 case QUARK_X1000_SSP:
170 return RX_THRESH_QUARK_X1000_DFLT;
172 return RX_THRESH_DFLT;
176 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
180 switch (drv_data->ssp_type) {
181 case QUARK_X1000_SSP:
182 mask = QUARK_X1000_SSSR_TFL_MASK;
185 mask = SSSR_TFL_MASK;
189 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
192 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
197 switch (drv_data->ssp_type) {
198 case QUARK_X1000_SSP:
199 mask = QUARK_X1000_SSCR1_RFT;
208 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
209 u32 *sccr1_reg, u32 threshold)
211 switch (drv_data->ssp_type) {
212 case QUARK_X1000_SSP:
213 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
216 *sccr1_reg |= SSCR1_RxTresh(threshold);
221 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
222 u32 clk_div, u8 bits)
224 switch (drv_data->ssp_type) {
225 case QUARK_X1000_SSP:
227 | QUARK_X1000_SSCR0_Motorola
228 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
233 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
235 | (bits > 16 ? SSCR0_EDSS : 0);
240 * Read and write LPSS SSP private registers. Caller must first check that
241 * is_lpss_ssp() returns true before these can be called.
243 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
245 WARN_ON(!drv_data->lpss_base);
246 return readl(drv_data->lpss_base + offset);
249 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
250 unsigned offset, u32 value)
252 WARN_ON(!drv_data->lpss_base);
253 writel(value, drv_data->lpss_base + offset);
257 * lpss_ssp_setup - perform LPSS SSP specific setup
258 * @drv_data: pointer to the driver private data
260 * Perform LPSS SSP specific setup. This function must be called first if
261 * one is going to use LPSS SSP private registers.
263 static void lpss_ssp_setup(struct driver_data *drv_data)
265 const struct lpss_config *config;
268 config = lpss_get_config(drv_data);
269 drv_data->lpss_base = drv_data->ioaddr + config->offset;
271 /* Enable software chip select control */
272 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
273 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
274 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
275 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
277 /* Enable multiblock DMA transfers */
278 if (drv_data->master_info->enable_dma) {
279 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
281 if (config->reg_general >= 0) {
282 value = __lpss_ssp_read_priv(drv_data,
283 config->reg_general);
284 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
285 __lpss_ssp_write_priv(drv_data,
286 config->reg_general, value);
291 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
293 const struct lpss_config *config;
296 config = lpss_get_config(drv_data);
298 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
300 cs = drv_data->cur_msg->spi->chip_select;
301 cs <<= LPSS_CS_CONTROL_CS_SEL_SHIFT;
302 if (cs != (value & LPSS_CS_CONTROL_CS_SEL_MASK)) {
304 * When switching another chip select output active
305 * the output must be selected first and wait 2 ssp_clk
306 * cycles before changing state to active. Otherwise
307 * a short glitch will occur on the previous chip
308 * select since output select is latched but state
311 value &= ~LPSS_CS_CONTROL_CS_SEL_MASK;
313 __lpss_ssp_write_priv(drv_data,
314 config->reg_cs_ctrl, value);
316 (drv_data->master->max_speed_hz / 2));
318 value &= ~LPSS_CS_CONTROL_CS_HIGH;
320 value |= LPSS_CS_CONTROL_CS_HIGH;
322 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
325 static void cs_assert(struct driver_data *drv_data)
327 struct chip_data *chip = drv_data->cur_chip;
329 if (drv_data->ssp_type == CE4100_SSP) {
330 pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
334 if (chip->cs_control) {
335 chip->cs_control(PXA2XX_CS_ASSERT);
339 if (gpio_is_valid(chip->gpio_cs)) {
340 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
344 if (is_lpss_ssp(drv_data))
345 lpss_ssp_cs_control(drv_data, true);
348 static void cs_deassert(struct driver_data *drv_data)
350 struct chip_data *chip = drv_data->cur_chip;
352 if (drv_data->ssp_type == CE4100_SSP)
355 if (chip->cs_control) {
356 chip->cs_control(PXA2XX_CS_DEASSERT);
360 if (gpio_is_valid(chip->gpio_cs)) {
361 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
365 if (is_lpss_ssp(drv_data))
366 lpss_ssp_cs_control(drv_data, false);
369 int pxa2xx_spi_flush(struct driver_data *drv_data)
371 unsigned long limit = loops_per_jiffy << 1;
374 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
375 pxa2xx_spi_read(drv_data, SSDR);
376 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
377 write_SSSR_CS(drv_data, SSSR_ROR);
382 static int null_writer(struct driver_data *drv_data)
384 u8 n_bytes = drv_data->n_bytes;
386 if (pxa2xx_spi_txfifo_full(drv_data)
387 || (drv_data->tx == drv_data->tx_end))
390 pxa2xx_spi_write(drv_data, SSDR, 0);
391 drv_data->tx += n_bytes;
396 static int null_reader(struct driver_data *drv_data)
398 u8 n_bytes = drv_data->n_bytes;
400 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
401 && (drv_data->rx < drv_data->rx_end)) {
402 pxa2xx_spi_read(drv_data, SSDR);
403 drv_data->rx += n_bytes;
406 return drv_data->rx == drv_data->rx_end;
409 static int u8_writer(struct driver_data *drv_data)
411 if (pxa2xx_spi_txfifo_full(drv_data)
412 || (drv_data->tx == drv_data->tx_end))
415 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
421 static int u8_reader(struct driver_data *drv_data)
423 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
424 && (drv_data->rx < drv_data->rx_end)) {
425 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
429 return drv_data->rx == drv_data->rx_end;
432 static int u16_writer(struct driver_data *drv_data)
434 if (pxa2xx_spi_txfifo_full(drv_data)
435 || (drv_data->tx == drv_data->tx_end))
438 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
444 static int u16_reader(struct driver_data *drv_data)
446 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
447 && (drv_data->rx < drv_data->rx_end)) {
448 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
452 return drv_data->rx == drv_data->rx_end;
455 static int u32_writer(struct driver_data *drv_data)
457 if (pxa2xx_spi_txfifo_full(drv_data)
458 || (drv_data->tx == drv_data->tx_end))
461 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
467 static int u32_reader(struct driver_data *drv_data)
469 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
470 && (drv_data->rx < drv_data->rx_end)) {
471 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
475 return drv_data->rx == drv_data->rx_end;
478 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
480 struct spi_message *msg = drv_data->cur_msg;
481 struct spi_transfer *trans = drv_data->cur_transfer;
483 /* Move to next transfer */
484 if (trans->transfer_list.next != &msg->transfers) {
485 drv_data->cur_transfer =
486 list_entry(trans->transfer_list.next,
489 return RUNNING_STATE;
494 /* caller already set message->status; dma and pio irqs are blocked */
495 static void giveback(struct driver_data *drv_data)
497 struct spi_transfer* last_transfer;
498 struct spi_message *msg;
500 msg = drv_data->cur_msg;
501 drv_data->cur_msg = NULL;
502 drv_data->cur_transfer = NULL;
504 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
507 /* Delay if requested before any change in chip select */
508 if (last_transfer->delay_usecs)
509 udelay(last_transfer->delay_usecs);
511 /* Drop chip select UNLESS cs_change is true or we are returning
512 * a message with an error, or next message is for another chip
514 if (!last_transfer->cs_change)
515 cs_deassert(drv_data);
517 struct spi_message *next_msg;
519 /* Holding of cs was hinted, but we need to make sure
520 * the next message is for the same chip. Don't waste
521 * time with the following tests unless this was hinted.
523 * We cannot postpone this until pump_messages, because
524 * after calling msg->complete (below) the driver that
525 * sent the current message could be unloaded, which
526 * could invalidate the cs_control() callback...
529 /* get a pointer to the next message, if any */
530 next_msg = spi_get_next_queued_message(drv_data->master);
532 /* see if the next and current messages point
535 if (next_msg && next_msg->spi != msg->spi)
537 if (!next_msg || msg->state == ERROR_STATE)
538 cs_deassert(drv_data);
541 drv_data->cur_chip = NULL;
542 spi_finalize_current_message(drv_data->master);
545 static void reset_sccr1(struct driver_data *drv_data)
547 struct chip_data *chip = drv_data->cur_chip;
550 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
551 switch (drv_data->ssp_type) {
552 case QUARK_X1000_SSP:
553 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
556 sccr1_reg &= ~SSCR1_RFT;
559 sccr1_reg |= chip->threshold;
560 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
563 static void int_error_stop(struct driver_data *drv_data, const char* msg)
565 /* Stop and reset SSP */
566 write_SSSR_CS(drv_data, drv_data->clear_sr);
567 reset_sccr1(drv_data);
568 if (!pxa25x_ssp_comp(drv_data))
569 pxa2xx_spi_write(drv_data, SSTO, 0);
570 pxa2xx_spi_flush(drv_data);
571 pxa2xx_spi_write(drv_data, SSCR0,
572 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
574 dev_err(&drv_data->pdev->dev, "%s\n", msg);
576 drv_data->cur_msg->state = ERROR_STATE;
577 tasklet_schedule(&drv_data->pump_transfers);
580 static void int_transfer_complete(struct driver_data *drv_data)
583 write_SSSR_CS(drv_data, drv_data->clear_sr);
584 reset_sccr1(drv_data);
585 if (!pxa25x_ssp_comp(drv_data))
586 pxa2xx_spi_write(drv_data, SSTO, 0);
588 /* Update total byte transferred return count actual bytes read */
589 drv_data->cur_msg->actual_length += drv_data->len -
590 (drv_data->rx_end - drv_data->rx);
592 /* Transfer delays and chip select release are
593 * handled in pump_transfers or giveback
596 /* Move to next transfer */
597 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
599 /* Schedule transfer tasklet */
600 tasklet_schedule(&drv_data->pump_transfers);
603 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
605 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
606 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
608 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
610 if (irq_status & SSSR_ROR) {
611 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
615 if (irq_status & SSSR_TINT) {
616 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
617 if (drv_data->read(drv_data)) {
618 int_transfer_complete(drv_data);
623 /* Drain rx fifo, Fill tx fifo and prevent overruns */
625 if (drv_data->read(drv_data)) {
626 int_transfer_complete(drv_data);
629 } while (drv_data->write(drv_data));
631 if (drv_data->read(drv_data)) {
632 int_transfer_complete(drv_data);
636 if (drv_data->tx == drv_data->tx_end) {
640 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
641 sccr1_reg &= ~SSCR1_TIE;
644 * PXA25x_SSP has no timeout, set up rx threshould for the
645 * remaining RX bytes.
647 if (pxa25x_ssp_comp(drv_data)) {
650 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
652 bytes_left = drv_data->rx_end - drv_data->rx;
653 switch (drv_data->n_bytes) {
660 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
661 if (rx_thre > bytes_left)
662 rx_thre = bytes_left;
664 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
666 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
669 /* We did something */
673 static irqreturn_t ssp_int(int irq, void *dev_id)
675 struct driver_data *drv_data = dev_id;
677 u32 mask = drv_data->mask_sr;
681 * The IRQ might be shared with other peripherals so we must first
682 * check that are we RPM suspended or not. If we are we assume that
683 * the IRQ was not for us (we shouldn't be RPM suspended when the
684 * interrupt is enabled).
686 if (pm_runtime_suspended(&drv_data->pdev->dev))
690 * If the device is not yet in RPM suspended state and we get an
691 * interrupt that is meant for another device, check if status bits
692 * are all set to one. That means that the device is already
695 status = pxa2xx_spi_read(drv_data, SSSR);
699 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
701 /* Ignore possible writes if we don't need to write */
702 if (!(sccr1_reg & SSCR1_TIE))
705 /* Ignore RX timeout interrupt if it is disabled */
706 if (!(sccr1_reg & SSCR1_TINTE))
709 if (!(status & mask))
712 if (!drv_data->cur_msg) {
714 pxa2xx_spi_write(drv_data, SSCR0,
715 pxa2xx_spi_read(drv_data, SSCR0)
717 pxa2xx_spi_write(drv_data, SSCR1,
718 pxa2xx_spi_read(drv_data, SSCR1)
719 & ~drv_data->int_cr1);
720 if (!pxa25x_ssp_comp(drv_data))
721 pxa2xx_spi_write(drv_data, SSTO, 0);
722 write_SSSR_CS(drv_data, drv_data->clear_sr);
724 dev_err(&drv_data->pdev->dev,
725 "bad message state in interrupt handler\n");
731 return drv_data->transfer_handler(drv_data);
735 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
736 * input frequency by fractions of 2^24. It also has a divider by 5.
738 * There are formulas to get baud rate value for given input frequency and
739 * divider parameters, such as DDS_CLK_RATE and SCR:
743 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
744 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
746 * DDS_CLK_RATE either 2^n or 2^n / 5.
747 * SCR is in range 0 .. 255
749 * Divisor = 5^i * 2^j * 2 * k
750 * i = [0, 1] i = 1 iff j = 0 or j > 3
751 * j = [0, 23] j = 0 iff i = 1
753 * Special case: j = 0, i = 1: Divisor = 2 / 5
755 * Accordingly to the specification the recommended values for DDS_CLK_RATE
757 * Case 1: 2^n, n = [0, 23]
758 * Case 2: 2^24 * 2 / 5 (0x666666)
759 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
761 * In all cases the lowest possible value is better.
763 * The function calculates parameters for all cases and chooses the one closest
764 * to the asked baud rate.
766 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
768 unsigned long xtal = 200000000;
769 unsigned long fref = xtal / 2; /* mandatory division by 2,
772 unsigned long fref1 = fref / 2; /* case 1 */
773 unsigned long fref2 = fref * 2 / 5; /* case 2 */
775 unsigned long q, q1, q2;
781 /* Set initial value for DDS_CLK_RATE */
782 mul = (1 << 24) >> 1;
784 /* Calculate initial quot */
785 q1 = DIV_ROUND_UP(fref1, rate);
787 /* Scale q1 if it's too big */
789 /* Scale q1 to range [1, 512] */
790 scale = fls_long(q1 - 1);
796 /* Round the result if we have a remainder */
800 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
805 /* Get the remainder */
806 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
810 q2 = DIV_ROUND_UP(fref2, rate);
811 r2 = abs(fref2 / q2 - rate);
814 * Choose the best between two: less remainder we have the better. We
815 * can't go case 2 if q2 is greater than 256 since SCR register can
816 * hold only values 0 .. 255.
818 if (r2 >= r1 || q2 > 256) {
819 /* case 1 is better */
823 /* case 2 is better */
826 mul = (1 << 24) * 2 / 5;
829 /* Check case 3 only if the divisor is big enough */
830 if (fref / rate >= 80) {
834 /* Calculate initial quot */
835 q1 = DIV_ROUND_UP(fref, rate);
838 /* Get the remainder */
839 fssp = (u64)fref * m;
840 do_div(fssp, 1 << 24);
841 r1 = abs(fssp - rate);
843 /* Choose this one if it suits better */
845 /* case 3 is better */
855 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
857 unsigned long ssp_clk = drv_data->master->max_speed_hz;
858 const struct ssp_device *ssp = drv_data->ssp;
860 rate = min_t(int, ssp_clk, rate);
862 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
863 return (ssp_clk / (2 * rate) - 1) & 0xff;
865 return (ssp_clk / rate - 1) & 0xfff;
868 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
871 struct chip_data *chip = drv_data->cur_chip;
872 unsigned int clk_div;
874 switch (drv_data->ssp_type) {
875 case QUARK_X1000_SSP:
876 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
879 clk_div = ssp_get_clk_div(drv_data, rate);
885 static void pump_transfers(unsigned long data)
887 struct driver_data *drv_data = (struct driver_data *)data;
888 struct spi_message *message = NULL;
889 struct spi_transfer *transfer = NULL;
890 struct spi_transfer *previous = NULL;
891 struct chip_data *chip = NULL;
897 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
898 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
899 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
901 /* Get current state information */
902 message = drv_data->cur_msg;
903 transfer = drv_data->cur_transfer;
904 chip = drv_data->cur_chip;
906 /* Handle for abort */
907 if (message->state == ERROR_STATE) {
908 message->status = -EIO;
913 /* Handle end of message */
914 if (message->state == DONE_STATE) {
920 /* Delay if requested at end of transfer before CS change */
921 if (message->state == RUNNING_STATE) {
922 previous = list_entry(transfer->transfer_list.prev,
925 if (previous->delay_usecs)
926 udelay(previous->delay_usecs);
928 /* Drop chip select only if cs_change is requested */
929 if (previous->cs_change)
930 cs_deassert(drv_data);
933 /* Check if we can DMA this transfer */
934 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
936 /* reject already-mapped transfers; PIO won't always work */
937 if (message->is_dma_mapped
938 || transfer->rx_dma || transfer->tx_dma) {
939 dev_err(&drv_data->pdev->dev,
940 "pump_transfers: mapped transfer length of "
941 "%u is greater than %d\n",
942 transfer->len, MAX_DMA_LEN);
943 message->status = -EINVAL;
948 /* warn ... we force this to PIO mode */
949 dev_warn_ratelimited(&message->spi->dev,
950 "pump_transfers: DMA disabled for transfer length %ld "
952 (long)drv_data->len, MAX_DMA_LEN);
955 /* Setup the transfer state based on the type of transfer */
956 if (pxa2xx_spi_flush(drv_data) == 0) {
957 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
958 message->status = -EIO;
962 drv_data->n_bytes = chip->n_bytes;
963 drv_data->tx = (void *)transfer->tx_buf;
964 drv_data->tx_end = drv_data->tx + transfer->len;
965 drv_data->rx = transfer->rx_buf;
966 drv_data->rx_end = drv_data->rx + transfer->len;
967 drv_data->rx_dma = transfer->rx_dma;
968 drv_data->tx_dma = transfer->tx_dma;
969 drv_data->len = transfer->len;
970 drv_data->write = drv_data->tx ? chip->write : null_writer;
971 drv_data->read = drv_data->rx ? chip->read : null_reader;
973 /* Change speed and bit per word on a per transfer */
974 bits = transfer->bits_per_word;
975 speed = transfer->speed_hz;
977 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
980 drv_data->n_bytes = 1;
981 drv_data->read = drv_data->read != null_reader ?
982 u8_reader : null_reader;
983 drv_data->write = drv_data->write != null_writer ?
984 u8_writer : null_writer;
985 } else if (bits <= 16) {
986 drv_data->n_bytes = 2;
987 drv_data->read = drv_data->read != null_reader ?
988 u16_reader : null_reader;
989 drv_data->write = drv_data->write != null_writer ?
990 u16_writer : null_writer;
991 } else if (bits <= 32) {
992 drv_data->n_bytes = 4;
993 drv_data->read = drv_data->read != null_reader ?
994 u32_reader : null_reader;
995 drv_data->write = drv_data->write != null_writer ?
996 u32_writer : null_writer;
999 * if bits/word is changed in dma mode, then must check the
1000 * thresholds and burst also
1002 if (chip->enable_dma) {
1003 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1007 dev_warn_ratelimited(&message->spi->dev,
1008 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
1011 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1012 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1013 if (!pxa25x_ssp_comp(drv_data))
1014 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1015 drv_data->master->max_speed_hz
1016 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1017 chip->enable_dma ? "DMA" : "PIO");
1019 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1020 drv_data->master->max_speed_hz / 2
1021 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1022 chip->enable_dma ? "DMA" : "PIO");
1024 message->state = RUNNING_STATE;
1026 drv_data->dma_mapped = 0;
1027 if (pxa2xx_spi_dma_is_possible(drv_data->len))
1028 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
1029 if (drv_data->dma_mapped) {
1031 /* Ensure we have the correct interrupt handler */
1032 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1034 pxa2xx_spi_dma_prepare(drv_data, dma_burst);
1036 /* Clear status and start DMA engine */
1037 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1038 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1040 pxa2xx_spi_dma_start(drv_data);
1042 /* Ensure we have the correct interrupt handler */
1043 drv_data->transfer_handler = interrupt_transfer;
1046 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1047 write_SSSR_CS(drv_data, drv_data->clear_sr);
1050 if (is_lpss_ssp(drv_data)) {
1051 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1052 != chip->lpss_rx_threshold)
1053 pxa2xx_spi_write(drv_data, SSIRF,
1054 chip->lpss_rx_threshold);
1055 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1056 != chip->lpss_tx_threshold)
1057 pxa2xx_spi_write(drv_data, SSITF,
1058 chip->lpss_tx_threshold);
1061 if (is_quark_x1000_ssp(drv_data) &&
1062 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1063 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1065 /* see if we need to reload the config registers */
1066 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1067 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1068 != (cr1 & change_mask)) {
1069 /* stop the SSP, and update the other bits */
1070 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1071 if (!pxa25x_ssp_comp(drv_data))
1072 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1073 /* first set CR1 without interrupt and service enables */
1074 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1075 /* restart the SSP */
1076 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1079 if (!pxa25x_ssp_comp(drv_data))
1080 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1083 cs_assert(drv_data);
1085 /* after chip select, release the data by enabling service
1086 * requests and interrupts, without changing any mode bits */
1087 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1090 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
1091 struct spi_message *msg)
1093 struct driver_data *drv_data = spi_master_get_devdata(master);
1095 drv_data->cur_msg = msg;
1096 /* Initial message state*/
1097 drv_data->cur_msg->state = START_STATE;
1098 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1099 struct spi_transfer,
1102 /* prepare to setup the SSP, in pump_transfers, using the per
1103 * chip configuration */
1104 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1106 /* Mark as busy and launch transfers */
1107 tasklet_schedule(&drv_data->pump_transfers);
1111 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1113 struct driver_data *drv_data = spi_master_get_devdata(master);
1115 /* Disable the SSP now */
1116 pxa2xx_spi_write(drv_data, SSCR0,
1117 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1122 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1123 struct pxa2xx_spi_chip *chip_info)
1127 if (chip == NULL || chip_info == NULL)
1130 /* NOTE: setup() can be called multiple times, possibly with
1131 * different chip_info, release previously requested GPIO
1133 if (gpio_is_valid(chip->gpio_cs))
1134 gpio_free(chip->gpio_cs);
1136 /* If (*cs_control) is provided, ignore GPIO chip select */
1137 if (chip_info->cs_control) {
1138 chip->cs_control = chip_info->cs_control;
1142 if (gpio_is_valid(chip_info->gpio_cs)) {
1143 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1145 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1146 chip_info->gpio_cs);
1150 chip->gpio_cs = chip_info->gpio_cs;
1151 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1153 err = gpio_direction_output(chip->gpio_cs,
1154 !chip->gpio_cs_inverted);
1160 static int setup(struct spi_device *spi)
1162 struct pxa2xx_spi_chip *chip_info = NULL;
1163 struct chip_data *chip;
1164 const struct lpss_config *config;
1165 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1166 uint tx_thres, tx_hi_thres, rx_thres;
1168 switch (drv_data->ssp_type) {
1169 case QUARK_X1000_SSP:
1170 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1172 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1178 config = lpss_get_config(drv_data);
1179 tx_thres = config->tx_threshold_lo;
1180 tx_hi_thres = config->tx_threshold_hi;
1181 rx_thres = config->rx_threshold;
1184 tx_thres = TX_THRESH_DFLT;
1186 rx_thres = RX_THRESH_DFLT;
1190 /* Only alloc on first setup */
1191 chip = spi_get_ctldata(spi);
1193 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1197 if (drv_data->ssp_type == CE4100_SSP) {
1198 if (spi->chip_select > 4) {
1200 "failed setup: cs number must not be > 4.\n");
1205 chip->frm = spi->chip_select;
1208 chip->enable_dma = 0;
1209 chip->timeout = TIMOUT_DFLT;
1212 /* protocol drivers may change the chip settings, so...
1213 * if chip_info exists, use it */
1214 chip_info = spi->controller_data;
1216 /* chip_info isn't always needed */
1219 if (chip_info->timeout)
1220 chip->timeout = chip_info->timeout;
1221 if (chip_info->tx_threshold)
1222 tx_thres = chip_info->tx_threshold;
1223 if (chip_info->tx_hi_threshold)
1224 tx_hi_thres = chip_info->tx_hi_threshold;
1225 if (chip_info->rx_threshold)
1226 rx_thres = chip_info->rx_threshold;
1227 chip->enable_dma = drv_data->master_info->enable_dma;
1228 chip->dma_threshold = 0;
1229 if (chip_info->enable_loopback)
1230 chip->cr1 = SSCR1_LBM;
1231 } else if (ACPI_HANDLE(&spi->dev)) {
1233 * Slave devices enumerated from ACPI namespace don't
1234 * usually have chip_info but we still might want to use
1237 chip->enable_dma = drv_data->master_info->enable_dma;
1240 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1241 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1242 | SSITF_TxHiThresh(tx_hi_thres);
1244 /* set dma burst and threshold outside of chip_info path so that if
1245 * chip_info goes away after setting chip->enable_dma, the
1246 * burst and threshold can still respond to changes in bits_per_word */
1247 if (chip->enable_dma) {
1248 /* set up legal burst and threshold for dma */
1249 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1251 &chip->dma_burst_size,
1252 &chip->dma_threshold)) {
1254 "in setup: DMA burst size reduced to match bits_per_word\n");
1258 switch (drv_data->ssp_type) {
1259 case QUARK_X1000_SSP:
1260 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1261 & QUARK_X1000_SSCR1_RFT)
1262 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1263 & QUARK_X1000_SSCR1_TFT);
1266 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1267 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1271 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1272 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1273 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1275 if (spi->mode & SPI_LOOP)
1276 chip->cr1 |= SSCR1_LBM;
1278 if (spi->bits_per_word <= 8) {
1280 chip->read = u8_reader;
1281 chip->write = u8_writer;
1282 } else if (spi->bits_per_word <= 16) {
1284 chip->read = u16_reader;
1285 chip->write = u16_writer;
1286 } else if (spi->bits_per_word <= 32) {
1288 chip->read = u32_reader;
1289 chip->write = u32_writer;
1292 spi_set_ctldata(spi, chip);
1294 if (drv_data->ssp_type == CE4100_SSP)
1297 return setup_cs(spi, chip, chip_info);
1300 static void cleanup(struct spi_device *spi)
1302 struct chip_data *chip = spi_get_ctldata(spi);
1303 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1308 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1309 gpio_free(chip->gpio_cs);
1317 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1318 { "INT33C0", LPSS_LPT_SSP },
1319 { "INT33C1", LPSS_LPT_SSP },
1320 { "INT3430", LPSS_LPT_SSP },
1321 { "INT3431", LPSS_LPT_SSP },
1322 { "80860F0E", LPSS_BYT_SSP },
1323 { "8086228E", LPSS_BYT_SSP },
1326 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1328 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1333 if (adev && adev->pnp.unique_id &&
1334 !kstrtouint(adev->pnp.unique_id, 0, &devid))
1338 #else /* !CONFIG_ACPI */
1339 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1346 * PCI IDs of compound devices that integrate both host controller and private
1347 * integrated DMA engine. Please note these are not used in module
1348 * autoloading and probing in this module but matching the LPSS SSP type.
1350 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1352 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1353 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1355 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1356 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1358 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1359 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1360 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1362 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1363 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1364 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1368 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1370 struct device *dev = param;
1372 if (dev != chan->device->dev->parent)
1378 static struct pxa2xx_spi_master *
1379 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1381 struct pxa2xx_spi_master *pdata;
1382 struct acpi_device *adev;
1383 struct ssp_device *ssp;
1384 struct resource *res;
1385 const struct acpi_device_id *adev_id = NULL;
1386 const struct pci_device_id *pcidev_id = NULL;
1389 adev = ACPI_COMPANION(&pdev->dev);
1391 if (dev_is_pci(pdev->dev.parent))
1392 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1393 to_pci_dev(pdev->dev.parent));
1395 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1401 type = (int)adev_id->driver_data;
1403 type = (int)pcidev_id->driver_data;
1407 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1411 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1417 ssp->phys_base = res->start;
1418 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1419 if (IS_ERR(ssp->mmio_base))
1423 pdata->tx_param = pdev->dev.parent;
1424 pdata->rx_param = pdev->dev.parent;
1425 pdata->dma_filter = pxa2xx_spi_idma_filter;
1428 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1429 ssp->irq = platform_get_irq(pdev, 0);
1432 ssp->port_id = pxa2xx_spi_get_port_id(adev);
1434 pdata->num_chipselect = 1;
1435 pdata->enable_dma = true;
1440 #else /* !CONFIG_PCI */
1441 static inline struct pxa2xx_spi_master *
1442 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1448 static int pxa2xx_spi_probe(struct platform_device *pdev)
1450 struct device *dev = &pdev->dev;
1451 struct pxa2xx_spi_master *platform_info;
1452 struct spi_master *master;
1453 struct driver_data *drv_data;
1454 struct ssp_device *ssp;
1455 const struct lpss_config *config;
1459 platform_info = dev_get_platdata(dev);
1460 if (!platform_info) {
1461 platform_info = pxa2xx_spi_init_pdata(pdev);
1462 if (!platform_info) {
1463 dev_err(&pdev->dev, "missing platform data\n");
1468 ssp = pxa_ssp_request(pdev->id, pdev->name);
1470 ssp = &platform_info->ssp;
1472 if (!ssp->mmio_base) {
1473 dev_err(&pdev->dev, "failed to get ssp\n");
1477 master = spi_alloc_master(dev, sizeof(struct driver_data));
1479 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1483 drv_data = spi_master_get_devdata(master);
1484 drv_data->master = master;
1485 drv_data->master_info = platform_info;
1486 drv_data->pdev = pdev;
1487 drv_data->ssp = ssp;
1489 master->dev.parent = &pdev->dev;
1490 master->dev.of_node = pdev->dev.of_node;
1491 /* the spi->mode bits understood by this driver: */
1492 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1494 master->bus_num = ssp->port_id;
1495 master->dma_alignment = DMA_ALIGNMENT;
1496 master->cleanup = cleanup;
1497 master->setup = setup;
1498 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1499 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1500 master->auto_runtime_pm = true;
1502 drv_data->ssp_type = ssp->type;
1504 drv_data->ioaddr = ssp->mmio_base;
1505 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1506 if (pxa25x_ssp_comp(drv_data)) {
1507 switch (drv_data->ssp_type) {
1508 case QUARK_X1000_SSP:
1509 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1512 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1516 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1517 drv_data->dma_cr1 = 0;
1518 drv_data->clear_sr = SSSR_ROR;
1519 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1521 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1522 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1523 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1524 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1525 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1528 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1531 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1532 goto out_error_master_alloc;
1535 /* Setup DMA if requested */
1536 if (platform_info->enable_dma) {
1537 status = pxa2xx_spi_dma_setup(drv_data);
1539 dev_dbg(dev, "no DMA channels available, using PIO\n");
1540 platform_info->enable_dma = false;
1544 /* Enable SOC clock */
1545 clk_prepare_enable(ssp->clk);
1547 master->max_speed_hz = clk_get_rate(ssp->clk);
1549 /* Load default SSP configuration */
1550 pxa2xx_spi_write(drv_data, SSCR0, 0);
1551 switch (drv_data->ssp_type) {
1552 case QUARK_X1000_SSP:
1553 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
1554 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1555 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1557 /* using the Motorola SPI protocol and use 8 bit frame */
1558 pxa2xx_spi_write(drv_data, SSCR0,
1559 QUARK_X1000_SSCR0_Motorola
1560 | QUARK_X1000_SSCR0_DataSize(8));
1563 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1564 SSCR1_TxTresh(TX_THRESH_DFLT);
1565 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1566 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1567 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1571 if (!pxa25x_ssp_comp(drv_data))
1572 pxa2xx_spi_write(drv_data, SSTO, 0);
1574 if (!is_quark_x1000_ssp(drv_data))
1575 pxa2xx_spi_write(drv_data, SSPSP, 0);
1577 if (is_lpss_ssp(drv_data))
1578 lpss_ssp_setup(drv_data);
1580 if (is_lpss_ssp(drv_data)) {
1581 lpss_ssp_setup(drv_data);
1582 config = lpss_get_config(drv_data);
1583 if (config->reg_capabilities >= 0) {
1584 tmp = __lpss_ssp_read_priv(drv_data,
1585 config->reg_capabilities);
1586 tmp &= LPSS_CAPS_CS_EN_MASK;
1587 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1588 platform_info->num_chipselect = ffz(tmp);
1591 master->num_chipselect = platform_info->num_chipselect;
1593 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1594 (unsigned long)drv_data);
1596 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1597 pm_runtime_use_autosuspend(&pdev->dev);
1598 pm_runtime_set_active(&pdev->dev);
1599 pm_runtime_enable(&pdev->dev);
1601 /* Register with the SPI framework */
1602 platform_set_drvdata(pdev, drv_data);
1603 status = devm_spi_register_master(&pdev->dev, master);
1605 dev_err(&pdev->dev, "problem registering spi master\n");
1606 goto out_error_clock_enabled;
1611 out_error_clock_enabled:
1612 clk_disable_unprepare(ssp->clk);
1613 pxa2xx_spi_dma_release(drv_data);
1614 free_irq(ssp->irq, drv_data);
1616 out_error_master_alloc:
1617 spi_master_put(master);
1622 static int pxa2xx_spi_remove(struct platform_device *pdev)
1624 struct driver_data *drv_data = platform_get_drvdata(pdev);
1625 struct ssp_device *ssp;
1629 ssp = drv_data->ssp;
1631 pm_runtime_get_sync(&pdev->dev);
1633 /* Disable the SSP at the peripheral and SOC level */
1634 pxa2xx_spi_write(drv_data, SSCR0, 0);
1635 clk_disable_unprepare(ssp->clk);
1638 if (drv_data->master_info->enable_dma)
1639 pxa2xx_spi_dma_release(drv_data);
1641 pm_runtime_put_noidle(&pdev->dev);
1642 pm_runtime_disable(&pdev->dev);
1645 free_irq(ssp->irq, drv_data);
1653 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1657 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1658 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1661 #ifdef CONFIG_PM_SLEEP
1662 static int pxa2xx_spi_suspend(struct device *dev)
1664 struct driver_data *drv_data = dev_get_drvdata(dev);
1665 struct ssp_device *ssp = drv_data->ssp;
1668 status = spi_master_suspend(drv_data->master);
1671 pxa2xx_spi_write(drv_data, SSCR0, 0);
1673 if (!pm_runtime_suspended(dev))
1674 clk_disable_unprepare(ssp->clk);
1679 static int pxa2xx_spi_resume(struct device *dev)
1681 struct driver_data *drv_data = dev_get_drvdata(dev);
1682 struct ssp_device *ssp = drv_data->ssp;
1685 /* Enable the SSP clock */
1686 if (!pm_runtime_suspended(dev))
1687 clk_prepare_enable(ssp->clk);
1689 /* Restore LPSS private register bits */
1690 if (is_lpss_ssp(drv_data))
1691 lpss_ssp_setup(drv_data);
1693 /* Start the queue running */
1694 status = spi_master_resume(drv_data->master);
1696 dev_err(dev, "problem starting queue (%d)\n", status);
1705 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1707 struct driver_data *drv_data = dev_get_drvdata(dev);
1709 clk_disable_unprepare(drv_data->ssp->clk);
1713 static int pxa2xx_spi_runtime_resume(struct device *dev)
1715 struct driver_data *drv_data = dev_get_drvdata(dev);
1717 clk_prepare_enable(drv_data->ssp->clk);
1722 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1723 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1724 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1725 pxa2xx_spi_runtime_resume, NULL)
1728 static struct platform_driver driver = {
1730 .name = "pxa2xx-spi",
1731 .pm = &pxa2xx_spi_pm_ops,
1732 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1734 .probe = pxa2xx_spi_probe,
1735 .remove = pxa2xx_spi_remove,
1736 .shutdown = pxa2xx_spi_shutdown,
1739 static int __init pxa2xx_spi_init(void)
1741 return platform_driver_register(&driver);
1743 subsys_initcall(pxa2xx_spi_init);
1745 static void __exit pxa2xx_spi_exit(void)
1747 platform_driver_unregister(&driver);
1749 module_exit(pxa2xx_spi_exit);