2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39 #include <linux/slab.h>
44 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
46 return ctrl->pcie->port;
49 static irqreturn_t pcie_isr(int irq, void *dev_id);
50 static void start_int_poll_timer(struct controller *ctrl, int sec);
52 /* This is the interrupt polling timeout function. */
53 static void int_poll_timeout(unsigned long data)
55 struct controller *ctrl = (struct controller *)data;
57 /* Poll for interrupt events. regs == NULL => polling */
60 init_timer(&ctrl->poll_timer);
61 if (!pciehp_poll_time)
62 pciehp_poll_time = 2; /* default polling interval is 2 sec */
64 start_int_poll_timer(ctrl, pciehp_poll_time);
67 /* This function starts the interrupt polling timer. */
68 static void start_int_poll_timer(struct controller *ctrl, int sec)
70 /* Clamp to sane value */
71 if ((sec <= 0) || (sec > 60))
74 ctrl->poll_timer.function = &int_poll_timeout;
75 ctrl->poll_timer.data = (unsigned long)ctrl;
76 ctrl->poll_timer.expires = jiffies + sec * HZ;
77 add_timer(&ctrl->poll_timer);
80 static inline int pciehp_request_irq(struct controller *ctrl)
82 int retval, irq = ctrl->pcie->irq;
84 /* Install interrupt polling timer. Start with 10 sec delay */
85 if (pciehp_poll_mode) {
86 init_timer(&ctrl->poll_timer);
87 start_int_poll_timer(ctrl, 10);
91 /* Installs the interrupt handler */
92 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
94 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
99 static inline void pciehp_free_irq(struct controller *ctrl)
101 if (pciehp_poll_mode)
102 del_timer_sync(&ctrl->poll_timer);
104 free_irq(ctrl->pcie->irq, ctrl);
107 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
109 struct pci_dev *pdev = ctrl_dev(ctrl);
112 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
113 if (slot_status & PCI_EXP_SLTSTA_CC) {
114 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
118 while (timeout > 0) {
121 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
122 if (slot_status & PCI_EXP_SLTSTA_CC) {
123 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
128 return 0; /* timeout */
131 static void pcie_wait_cmd(struct controller *ctrl)
133 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
134 unsigned long duration = msecs_to_jiffies(msecs);
135 unsigned long cmd_timeout = ctrl->cmd_started + duration;
136 unsigned long now, timeout;
140 * If the controller does not generate notifications for command
141 * completions, we never need to wait between writes.
143 if (NO_CMD_CMPL(ctrl))
150 * Even if the command has already timed out, we want to call
151 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
154 if (time_before_eq(cmd_timeout, now))
157 timeout = cmd_timeout - now;
159 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
160 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
161 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
163 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
166 * Controllers with errata like Intel CF118 don't generate
167 * completion notifications unless the power/indicator/interlock
168 * control bits are changed. On such controllers, we'll emit this
169 * timeout message when we wait for completion of commands that
170 * don't change those bits, e.g., commands that merely enable
174 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
176 jiffies_to_msecs(jiffies - ctrl->cmd_started));
179 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
182 struct pci_dev *pdev = ctrl_dev(ctrl);
185 mutex_lock(&ctrl->ctrl_lock);
188 * Always wait for any previous command that might still be in progress
192 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
194 slot_ctrl |= (cmd & mask);
197 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
198 ctrl->cmd_started = jiffies;
199 ctrl->slot_ctrl = slot_ctrl;
202 * Optionally wait for the hardware to be ready for a new command,
203 * indicating completion of the above issued command.
208 mutex_unlock(&ctrl->ctrl_lock);
212 * pcie_write_cmd - Issue controller command
213 * @ctrl: controller to which the command is issued
214 * @cmd: command value written to slot control register
215 * @mask: bitmask of slot control register to be modified
217 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
219 pcie_do_write_cmd(ctrl, cmd, mask, true);
222 /* Same as above without waiting for the hardware to latch */
223 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
225 pcie_do_write_cmd(ctrl, cmd, mask, false);
228 bool pciehp_check_link_active(struct controller *ctrl)
230 struct pci_dev *pdev = ctrl_dev(ctrl);
234 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
235 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
238 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
243 static void __pcie_wait_link_active(struct controller *ctrl, bool active)
247 if (pciehp_check_link_active(ctrl) == active)
249 while (timeout > 0) {
252 if (pciehp_check_link_active(ctrl) == active)
255 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
256 active ? "set" : "cleared");
259 static void pcie_wait_link_active(struct controller *ctrl)
261 __pcie_wait_link_active(ctrl, true);
264 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
268 int delay = 1000, step = 20;
272 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
282 if (count > 1 && pciehp_debug)
283 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
284 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
285 PCI_FUNC(devfn), count, step, l);
290 int pciehp_check_link_status(struct controller *ctrl)
292 struct pci_dev *pdev = ctrl_dev(ctrl);
297 * Data Link Layer Link Active Reporting must be capable for
298 * hot-plug capable downstream port. But old controller might
299 * not implement it. In this case, we wait for 1000 ms.
301 if (ctrl->link_active_reporting)
302 pcie_wait_link_active(ctrl);
306 /* wait 100ms before read pci conf, and try in 1s */
308 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
311 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
312 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
313 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
314 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
315 ctrl_err(ctrl, "Link Training Error occurs\n");
319 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
327 static int __pciehp_link_set(struct controller *ctrl, bool enable)
329 struct pci_dev *pdev = ctrl_dev(ctrl);
332 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
335 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
337 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
339 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
340 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
344 static int pciehp_link_enable(struct controller *ctrl)
346 return __pciehp_link_set(ctrl, true);
349 void pciehp_get_attention_status(struct slot *slot, u8 *status)
351 struct controller *ctrl = slot->ctrl;
352 struct pci_dev *pdev = ctrl_dev(ctrl);
355 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
356 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
357 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
359 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
360 case PCI_EXP_SLTCTL_ATTN_IND_ON:
361 *status = 1; /* On */
363 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
364 *status = 2; /* Blink */
366 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
367 *status = 0; /* Off */
375 void pciehp_get_power_status(struct slot *slot, u8 *status)
377 struct controller *ctrl = slot->ctrl;
378 struct pci_dev *pdev = ctrl_dev(ctrl);
381 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
382 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
383 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
385 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
386 case PCI_EXP_SLTCTL_PWR_ON:
387 *status = 1; /* On */
389 case PCI_EXP_SLTCTL_PWR_OFF:
390 *status = 0; /* Off */
398 void pciehp_get_latch_status(struct slot *slot, u8 *status)
400 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
403 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
404 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
407 void pciehp_get_adapter_status(struct slot *slot, u8 *status)
409 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
412 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
413 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
416 int pciehp_query_power_fault(struct slot *slot)
418 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
421 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
422 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
425 void pciehp_set_attention_status(struct slot *slot, u8 value)
427 struct controller *ctrl = slot->ctrl;
434 case 0: /* turn off */
435 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
437 case 1: /* turn on */
438 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
440 case 2: /* turn blink */
441 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
446 pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
447 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
448 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
451 void pciehp_green_led_on(struct slot *slot)
453 struct controller *ctrl = slot->ctrl;
458 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
460 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
461 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
462 PCI_EXP_SLTCTL_PWR_IND_ON);
465 void pciehp_green_led_off(struct slot *slot)
467 struct controller *ctrl = slot->ctrl;
472 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
474 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
475 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
476 PCI_EXP_SLTCTL_PWR_IND_OFF);
479 void pciehp_green_led_blink(struct slot *slot)
481 struct controller *ctrl = slot->ctrl;
486 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
488 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
489 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
490 PCI_EXP_SLTCTL_PWR_IND_BLINK);
493 int pciehp_power_on_slot(struct slot *slot)
495 struct controller *ctrl = slot->ctrl;
496 struct pci_dev *pdev = ctrl_dev(ctrl);
500 /* Clear sticky power-fault bit from previous power failures */
501 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
502 if (slot_status & PCI_EXP_SLTSTA_PFD)
503 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
505 ctrl->power_fault_detected = 0;
507 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
508 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
509 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
510 PCI_EXP_SLTCTL_PWR_ON);
512 retval = pciehp_link_enable(ctrl);
514 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
519 void pciehp_power_off_slot(struct slot *slot)
521 struct controller *ctrl = slot->ctrl;
523 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
524 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
525 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
526 PCI_EXP_SLTCTL_PWR_OFF);
529 static irqreturn_t pcie_isr(int irq, void *dev_id)
531 struct controller *ctrl = (struct controller *)dev_id;
532 struct pci_dev *pdev = ctrl_dev(ctrl);
533 struct pci_bus *subordinate = pdev->subordinate;
535 struct slot *slot = ctrl->slot;
536 u16 detected, intr_loc;
539 * In order to guarantee that all interrupt events are
540 * serviced, we need to re-inspect Slot Status register after
541 * clearing what is presumed to be the last pending interrupt.
545 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
547 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
548 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
549 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
550 detected &= ~intr_loc;
551 intr_loc |= detected;
555 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
559 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
561 /* Check Command Complete Interrupt Pending */
562 if (intr_loc & PCI_EXP_SLTSTA_CC) {
565 wake_up(&ctrl->queue);
569 list_for_each_entry(dev, &subordinate->devices, bus_list) {
570 if (dev->ignore_hotplug) {
571 ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n",
572 intr_loc, pci_name(dev));
578 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
581 /* Check MRL Sensor Changed */
582 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
583 pciehp_handle_switch_change(slot);
585 /* Check Attention Button Pressed */
586 if (intr_loc & PCI_EXP_SLTSTA_ABP)
587 pciehp_handle_attention_button(slot);
589 /* Check Presence Detect Changed */
590 if (intr_loc & PCI_EXP_SLTSTA_PDC)
591 pciehp_handle_presence_change(slot);
593 /* Check Power Fault Detected */
594 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
595 ctrl->power_fault_detected = 1;
596 pciehp_handle_power_fault(slot);
599 if (intr_loc & PCI_EXP_SLTSTA_DLLSC)
600 pciehp_handle_linkstate_change(slot);
605 void pcie_enable_notification(struct controller *ctrl)
610 * TBD: Power fault detected software notification support.
612 * Power fault detected software notification is not enabled
613 * now, because it caused power fault detected interrupt storm
614 * on some machines. On those machines, power fault detected
615 * bit in the slot status register was set again immediately
616 * when it is cleared in the interrupt service routine, and
617 * next power fault detected interrupt was notified again.
621 * Always enable link events: thus link-up and link-down shall
622 * always be treated as hotplug and unplug respectively. Enable
623 * presence detect only if Attention Button is not present.
625 cmd = PCI_EXP_SLTCTL_DLLSCE;
626 if (ATTN_BUTTN(ctrl))
627 cmd |= PCI_EXP_SLTCTL_ABPE;
629 cmd |= PCI_EXP_SLTCTL_PDCE;
631 cmd |= PCI_EXP_SLTCTL_MRLSCE;
632 if (!pciehp_poll_mode)
633 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
635 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
636 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
637 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
638 PCI_EXP_SLTCTL_DLLSCE);
640 pcie_write_cmd_nowait(ctrl, cmd, mask);
641 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
642 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
645 static void pcie_disable_notification(struct controller *ctrl)
649 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
650 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
651 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
652 PCI_EXP_SLTCTL_DLLSCE);
653 pcie_write_cmd(ctrl, 0, mask);
654 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
655 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
659 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
660 * bus reset of the bridge, but at the same time we want to ensure that it is
661 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
662 * disable link state notification and presence detection change notification
663 * momentarily, if we see that they could interfere. Also, clear any spurious
666 int pciehp_reset_slot(struct slot *slot, int probe)
668 struct controller *ctrl = slot->ctrl;
669 struct pci_dev *pdev = ctrl_dev(ctrl);
670 u16 stat_mask = 0, ctrl_mask = 0;
675 if (!ATTN_BUTTN(ctrl)) {
676 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
677 stat_mask |= PCI_EXP_SLTSTA_PDC;
679 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
680 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
682 pcie_write_cmd(ctrl, 0, ctrl_mask);
683 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
684 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
685 if (pciehp_poll_mode)
686 del_timer_sync(&ctrl->poll_timer);
688 pci_reset_bridge_secondary_bus(ctrl->pcie->port);
690 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
691 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
692 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
693 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
694 if (pciehp_poll_mode)
695 int_poll_timeout(ctrl->poll_timer.data);
700 int pcie_init_notification(struct controller *ctrl)
702 if (pciehp_request_irq(ctrl))
704 pcie_enable_notification(ctrl);
705 ctrl->notification_enabled = 1;
709 static void pcie_shutdown_notification(struct controller *ctrl)
711 if (ctrl->notification_enabled) {
712 pcie_disable_notification(ctrl);
713 pciehp_free_irq(ctrl);
714 ctrl->notification_enabled = 0;
718 static int pcie_init_slot(struct controller *ctrl)
722 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
726 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
731 mutex_init(&slot->lock);
732 mutex_init(&slot->hotplug_lock);
733 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
741 static void pcie_cleanup_slot(struct controller *ctrl)
743 struct slot *slot = ctrl->slot;
744 cancel_delayed_work(&slot->work);
745 destroy_workqueue(slot->wq);
749 static inline void dbg_ctrl(struct controller *ctrl)
753 struct pci_dev *pdev = ctrl->pcie->port;
758 ctrl_info(ctrl, "Hotplug Controller:\n");
759 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
760 pci_name(pdev), pdev->irq);
761 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
762 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
763 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
764 pdev->subsystem_device);
765 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
766 pdev->subsystem_vendor);
767 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
769 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
770 if (!pci_resource_len(pdev, i))
772 ctrl_info(ctrl, " PCI resource [%d] : %pR\n",
773 i, &pdev->resource[i]);
775 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
776 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
777 ctrl_info(ctrl, " Attention Button : %3s\n",
778 ATTN_BUTTN(ctrl) ? "yes" : "no");
779 ctrl_info(ctrl, " Power Controller : %3s\n",
780 POWER_CTRL(ctrl) ? "yes" : "no");
781 ctrl_info(ctrl, " MRL Sensor : %3s\n",
782 MRL_SENS(ctrl) ? "yes" : "no");
783 ctrl_info(ctrl, " Attention Indicator : %3s\n",
784 ATTN_LED(ctrl) ? "yes" : "no");
785 ctrl_info(ctrl, " Power Indicator : %3s\n",
786 PWR_LED(ctrl) ? "yes" : "no");
787 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
788 HP_SUPR_RM(ctrl) ? "yes" : "no");
789 ctrl_info(ctrl, " EMI Present : %3s\n",
790 EMI(ctrl) ? "yes" : "no");
791 ctrl_info(ctrl, " Command Completed : %3s\n",
792 NO_CMD_CMPL(ctrl) ? "no" : "yes");
793 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
794 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
795 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
796 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
799 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
801 struct controller *pcie_init(struct pcie_device *dev)
803 struct controller *ctrl;
804 u32 slot_cap, link_cap;
805 struct pci_dev *pdev = dev->port;
807 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
809 dev_err(&dev->device, "%s: Out of memory\n", __func__);
813 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
814 ctrl->slot_cap = slot_cap;
815 mutex_init(&ctrl->ctrl_lock);
816 init_waitqueue_head(&ctrl->queue);
819 /* Check if Data Link Layer Link Active Reporting is implemented */
820 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
821 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
822 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
823 ctrl->link_active_reporting = 1;
826 /* Clear all remaining event bits in Slot Status register */
827 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
828 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
829 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
830 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
832 ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n",
833 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
834 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
835 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
836 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
837 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
838 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
839 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
840 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
841 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
843 if (pcie_init_slot(ctrl))
854 void pciehp_release_ctrl(struct controller *ctrl)
856 pcie_shutdown_notification(ctrl);
857 pcie_cleanup_slot(ctrl);