1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
33 static bool _rtl8723e_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
35 void rtl8723e_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
37 struct rtl_priv *rtlpriv = rtl_priv(hw);
38 struct rtl_phy *rtlphy = &rtlpriv->phy;
41 case HT_CHANNEL_WIDTH_20:
42 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
43 0xfffff3ff) | 0x0400);
44 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
45 rtlphy->rfreg_chnlval[0]);
47 case HT_CHANNEL_WIDTH_20_40:
48 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
50 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
51 rtlphy->rfreg_chnlval[0]);
54 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
55 "unknown bandwidth: %#X\n", bandwidth);
60 void rtl8723e_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
63 struct rtl_priv *rtlpriv = rtl_priv(hw);
64 struct rtl_phy *rtlphy = &rtlpriv->phy;
65 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
66 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
67 u32 tx_agc[2] = {0, 0}, tmpval;
68 bool turbo_scanoff = false;
72 if (rtlefuse->eeprom_regulatory != 0)
75 if (mac->act_scanning == true) {
76 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
77 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
80 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B;
82 tx_agc[idx1] = ppowerlevel[idx1] |
83 (ppowerlevel[idx1] << 8) |
84 (ppowerlevel[idx1] << 16) |
85 (ppowerlevel[idx1] << 24);
89 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
90 tx_agc[idx1] = ppowerlevel[idx1] |
91 (ppowerlevel[idx1] << 8) |
92 (ppowerlevel[idx1] << 16) |
93 (ppowerlevel[idx1] << 24);
96 if (rtlefuse->eeprom_regulatory == 0) {
98 (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
99 (rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
101 tx_agc[RF90_PATH_A] += tmpval;
103 tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
104 (rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
106 tx_agc[RF90_PATH_B] += tmpval;
110 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
111 ptr = (u8 *)&tx_agc[idx1];
112 for (idx2 = 0; idx2 < 4; idx2++) {
113 if (*ptr > RF6052_MAX_TX_PWR)
114 *ptr = RF6052_MAX_TX_PWR;
119 tmpval = tx_agc[RF90_PATH_A] & 0xff;
120 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
122 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
123 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
124 RTXAGC_A_CCK1_MCS32);
126 tmpval = tx_agc[RF90_PATH_A] >> 8;
128 tmpval = tmpval & 0xff00ffff;
130 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
132 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
133 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
134 RTXAGC_B_CCK11_A_CCK2_11);
136 tmpval = tx_agc[RF90_PATH_B] >> 24;
137 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
139 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
140 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
141 RTXAGC_B_CCK11_A_CCK2_11);
143 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
144 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
146 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
147 "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
148 RTXAGC_B_CCK1_55_MCS32);
151 static void rtl8723e_phy_get_power_base(struct ieee80211_hw *hw,
152 u8 *ppowerlevel, u8 channel,
153 u32 *ofdmbase, u32 *mcsbase)
155 struct rtl_priv *rtlpriv = rtl_priv(hw);
156 struct rtl_phy *rtlphy = &rtlpriv->phy;
157 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
158 u32 powerbase0, powerbase1;
159 u8 legacy_pwrdiff, ht20_pwrdiff;
162 for (i = 0; i < 2; i++) {
163 powerlevel[i] = ppowerlevel[i];
164 legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
165 powerbase0 = powerlevel[i] + legacy_pwrdiff;
167 powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
168 (powerbase0 << 8) | powerbase0;
169 *(ofdmbase + i) = powerbase0;
170 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
171 " [OFDM power base index rf(%c) = 0x%x]\n",
172 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
175 for (i = 0; i < 2; i++) {
176 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
178 rtlefuse->txpwr_ht20diff[i][channel - 1];
179 powerlevel[i] += ht20_pwrdiff;
181 powerbase1 = powerlevel[i];
182 powerbase1 = (powerbase1 << 24) |
183 (powerbase1 << 16) | (powerbase1 << 8) | powerbase1;
185 *(mcsbase + i) = powerbase1;
187 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
188 " [MCS power base index rf(%c) = 0x%x]\n",
189 ((i == 0) ? 'A' : 'B'), *(mcsbase + i));
193 static void get_txpower_writeval_by_reg(struct ieee80211_hw *hw,
194 u8 channel, u8 index,
199 struct rtl_priv *rtlpriv = rtl_priv(hw);
200 struct rtl_phy *rtlphy = &rtlpriv->phy;
201 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
202 u8 i, chnlgroup = 0, pwr_diff_limit[4];
203 u32 writeval, customer_limit, rf;
205 for (rf = 0; rf < 2; rf++) {
206 switch (rtlefuse->eeprom_regulatory) {
211 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
213 + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
215 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
216 "RTK better performance, writeval(%c) = 0x%x\n",
217 ((rf == 0) ? 'A' : 'B'), writeval);
220 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
221 writeval = ((index < 2) ? powerbase0[rf] :
224 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
225 "Realtek regulatory, 40MHz, writeval(%c) = 0x%x\n",
226 ((rf == 0) ? 'A' : 'B'), writeval);
228 if (rtlphy->pwrgroup_cnt == 1)
230 if (rtlphy->pwrgroup_cnt >= 3) {
233 else if (channel >= 4 && channel <= 9)
235 else if (channel > 9)
237 if (rtlphy->current_chan_bw ==
245 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
246 [index + (rf ? 8 : 0)] + ((index < 2) ?
250 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
251 "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
252 ((rf == 0) ? 'A' : 'B'), writeval);
257 ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
259 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
260 "Better regulatory, writeval(%c) = 0x%x\n",
261 ((rf == 0) ? 'A' : 'B'), writeval);
266 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
267 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
268 "customer's limit, 40MHz rf(%c) = 0x%x\n",
269 ((rf == 0) ? 'A' : 'B'),
270 rtlefuse->pwrgroup_ht40[rf][channel -
273 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
274 "customer's limit, 20MHz rf(%c) = 0x%x\n",
275 ((rf == 0) ? 'A' : 'B'),
276 rtlefuse->pwrgroup_ht20[rf][channel -
279 for (i = 0; i < 4; i++) {
281 (u8)((rtlphy->mcs_txpwrlevel_origoffset
283 (rf ? 8 : 0)] & (0x7f <<
284 (i * 8))) >> (i * 8));
286 if (rtlphy->current_chan_bw ==
287 HT_CHANNEL_WIDTH_20_40) {
288 if (pwr_diff_limit[i] >
290 pwrgroup_ht40[rf][channel - 1])
292 rtlefuse->pwrgroup_ht40[rf]
295 if (pwr_diff_limit[i] >
297 pwrgroup_ht20[rf][channel - 1])
299 rtlefuse->pwrgroup_ht20[rf]
304 customer_limit = (pwr_diff_limit[3] << 24) |
305 (pwr_diff_limit[2] << 16) |
306 (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
308 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
309 "Customer's limit rf(%c) = 0x%x\n",
310 ((rf == 0) ? 'A' : 'B'), customer_limit);
312 writeval = customer_limit +
313 ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
315 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
316 "Customer, writeval rf(%c)= 0x%x\n",
317 ((rf == 0) ? 'A' : 'B'), writeval);
322 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
323 [index + (rf ? 8 : 0)]
324 + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
326 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
327 "RTK better performance, writeval rf(%c) = 0x%x\n",
328 ((rf == 0) ? 'A' : 'B'), writeval);
332 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
333 writeval = writeval - 0x06060606;
334 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
336 writeval = writeval - 0x0c0c0c0c;
337 *(p_outwriteval + rf) = writeval;
341 static void _rtl8723e_write_ofdm_power_reg(struct ieee80211_hw *hw,
342 u8 index, u32 *pvalue)
344 struct rtl_priv *rtlpriv = rtl_priv(hw);
345 struct rtl_phy *rtlphy = &rtlpriv->phy;
347 u16 regoffset_a[6] = {
348 RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
349 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
350 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
352 u16 regoffset_b[6] = {
353 RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
354 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
355 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
357 u8 i, rf, pwr_val[4];
361 for (rf = 0; rf < 2; rf++) {
362 writeval = pvalue[rf];
363 for (i = 0; i < 4; i++) {
364 pwr_val[i] = (u8)((writeval & (0x7f <<
365 (i * 8))) >> (i * 8));
367 if (pwr_val[i] > RF6052_MAX_TX_PWR)
368 pwr_val[i] = RF6052_MAX_TX_PWR;
370 writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
371 (pwr_val[1] << 8) | pwr_val[0];
374 regoffset = regoffset_a[index];
376 regoffset = regoffset_b[index];
377 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
379 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
380 "Set 0x%x = %08x\n", regoffset, writeval);
382 if (((get_rf_type(rtlphy) == RF_2T2R) &&
383 (regoffset == RTXAGC_A_MCS15_MCS12 ||
384 regoffset == RTXAGC_B_MCS15_MCS12)) ||
385 ((get_rf_type(rtlphy) != RF_2T2R) &&
386 (regoffset == RTXAGC_A_MCS07_MCS04 ||
387 regoffset == RTXAGC_B_MCS07_MCS04))) {
389 writeval = pwr_val[3];
390 if (regoffset == RTXAGC_A_MCS15_MCS12 ||
391 regoffset == RTXAGC_A_MCS07_MCS04)
393 if (regoffset == RTXAGC_B_MCS15_MCS12 ||
394 regoffset == RTXAGC_B_MCS07_MCS04)
397 for (i = 0; i < 3; i++) {
398 writeval = (writeval > 6) ? (writeval - 6) : 0;
399 rtl_write_byte(rtlpriv, (u32) (regoffset + i),
406 void rtl8723e_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
407 u8 *ppowerlevel, u8 channel)
409 u32 writeval[2], powerbase0[2], powerbase1[2];
412 rtl8723e_phy_get_power_base(hw, ppowerlevel,
413 channel, &powerbase0[0], &powerbase1[0]);
415 for (index = 0; index < 6; index++) {
416 get_txpower_writeval_by_reg(hw, channel, index, &powerbase0[0],
420 _rtl8723e_write_ofdm_power_reg(hw, index, &writeval[0]);
424 bool rtl8723e_phy_rf6052_config(struct ieee80211_hw *hw)
426 struct rtl_priv *rtlpriv = rtl_priv(hw);
427 struct rtl_phy *rtlphy = &rtlpriv->phy;
429 if (rtlphy->rf_type == RF_1T1R)
430 rtlphy->num_total_rfpath = 1;
432 rtlphy->num_total_rfpath = 2;
434 return _rtl8723e_phy_rf6052_config_parafile(hw);
437 static bool _rtl8723e_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
439 struct rtl_priv *rtlpriv = rtl_priv(hw);
440 struct rtl_phy *rtlphy = &rtlpriv->phy;
443 bool rtstatus = true;
444 struct bb_reg_def *pphyreg;
446 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
448 pphyreg = &rtlphy->phyreg_def[rfpath];
453 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
458 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
463 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
466 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
469 rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
470 B3WIREADDREAALENGTH, 0x0);
473 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
478 rtstatus = rtl8723e_phy_config_rf_with_headerfile(hw,
479 (enum radio_path)rfpath);
483 rtl8723e_phy_config_rf_with_headerfile(hw,
484 (enum radio_path)rfpath);
495 rtl_set_bbreg(hw, pphyreg->rfintfs,
496 BRFSI_RFENV, u4_regvalue);
500 rtl_set_bbreg(hw, pphyreg->rfintfs,
501 BRFSI_RFENV << 16, u4_regvalue);
505 if (rtstatus != true) {
506 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
507 "Radio[%d] Fail!!", rfpath);
512 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");