1 /******************************************************************************
3 * Copyright(c) 2009-2014 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
40 #include "../pwrseqcmd.h"
45 static void _rtl92ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
46 u8 set_bits, u8 clear_bits)
48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
49 struct rtl_priv *rtlpriv = rtl_priv(hw);
51 rtlpci->reg_bcn_ctrl_val |= set_bits;
52 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
54 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
57 static void _rtl92ee_stop_tx_beacon(struct ieee80211_hw *hw)
59 struct rtl_priv *rtlpriv = rtl_priv(hw);
62 tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
63 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp & (~BIT(6)));
64 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
65 tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
67 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp);
70 static void _rtl92ee_resume_tx_beacon(struct ieee80211_hw *hw)
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
75 tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
76 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp | BIT(6));
77 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
78 tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
80 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp);
83 static void _rtl92ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
85 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
88 static void _rtl92ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
90 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
93 static void _rtl92ee_set_fw_clock_on(struct ieee80211_hw *hw,
94 u8 rpwm_val, bool b_need_turn_off_ckk)
96 struct rtl_priv *rtlpriv = rtl_priv(hw);
97 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
98 bool b_support_remote_wake_up;
99 u32 count = 0, isr_regaddr, content;
100 bool b_schedule_timer = b_need_turn_off_ckk;
102 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
103 (u8 *)(&b_support_remote_wake_up));
105 if (!rtlhal->fw_ready)
107 if (!rtlpriv->psc.fw_current_inpsmode)
111 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
112 if (rtlhal->fw_clk_change_in_progress) {
113 while (rtlhal->fw_clk_change_in_progress) {
114 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
119 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
121 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
123 rtlhal->fw_clk_change_in_progress = false;
124 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
129 if (IS_IN_LOW_POWER_STATE_92E(rtlhal->fw_ps_state)) {
130 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
132 if (FW_PS_IS_ACK(rpwm_val)) {
133 isr_regaddr = REG_HISR;
134 content = rtl_read_dword(rtlpriv, isr_regaddr);
135 while (!(content & IMR_CPWM) && (count < 500)) {
138 content = rtl_read_dword(rtlpriv, isr_regaddr);
141 if (content & IMR_CPWM) {
142 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
143 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_92E;
144 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
145 "Receive CPWM INT!!! PSState = %X\n",
146 rtlhal->fw_ps_state);
150 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
151 rtlhal->fw_clk_change_in_progress = false;
152 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
153 if (b_schedule_timer) {
154 mod_timer(&rtlpriv->works.fw_clockoff_timer,
155 jiffies + MSECS(10));
158 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
159 rtlhal->fw_clk_change_in_progress = false;
160 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
164 static void _rtl92ee_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
166 struct rtl_priv *rtlpriv = rtl_priv(hw);
167 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
168 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
169 struct rtl8192_tx_ring *ring;
170 enum rf_pwrstate rtstate;
171 bool b_schedule_timer = false;
174 if (!rtlhal->fw_ready)
176 if (!rtlpriv->psc.fw_current_inpsmode)
178 if (!rtlhal->allow_sw_to_change_hwclc)
181 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
182 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
185 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
186 ring = &rtlpci->tx_ring[queue];
187 if (skb_queue_len(&ring->queue)) {
188 b_schedule_timer = true;
193 if (b_schedule_timer) {
194 mod_timer(&rtlpriv->works.fw_clockoff_timer,
195 jiffies + MSECS(10));
199 if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
200 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
201 if (!rtlhal->fw_clk_change_in_progress) {
202 rtlhal->fw_clk_change_in_progress = true;
203 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
204 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
205 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
206 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
208 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
209 rtlhal->fw_clk_change_in_progress = false;
210 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
212 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
213 mod_timer(&rtlpriv->works.fw_clockoff_timer,
214 jiffies + MSECS(10));
219 static void _rtl92ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
223 rpwm_val |= (FW_PS_STATE_RF_OFF_92E | FW_PS_ACK);
224 _rtl92ee_set_fw_clock_on(hw, rpwm_val, true);
227 static void _rtl92ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
231 rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR;
232 _rtl92ee_set_fw_clock_off(hw, rpwm_val);
235 void rtl92ee_fw_clk_off_timer_callback(unsigned long data)
237 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
239 _rtl92ee_set_fw_ps_rf_off_low_power(hw);
242 static void _rtl92ee_fwlps_leave(struct ieee80211_hw *hw)
244 struct rtl_priv *rtlpriv = rtl_priv(hw);
245 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
246 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
247 bool fw_current_inps = false;
248 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
250 if (ppsc->low_power_enable) {
251 rpwm_val = (FW_PS_STATE_ALL_ON_92E | FW_PS_ACK);/* RF on */
252 _rtl92ee_set_fw_clock_on(hw, rpwm_val, false);
253 rtlhal->allow_sw_to_change_hwclc = false;
254 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
255 (u8 *)(&fw_pwrmode));
256 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
257 (u8 *)(&fw_current_inps));
259 rpwm_val = FW_PS_STATE_ALL_ON_92E; /* RF on */
260 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
263 (u8 *)(&fw_pwrmode));
264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
265 (u8 *)(&fw_current_inps));
269 static void _rtl92ee_fwlps_enter(struct ieee80211_hw *hw)
271 struct rtl_priv *rtlpriv = rtl_priv(hw);
272 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
273 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
274 bool fw_current_inps = true;
277 if (ppsc->low_power_enable) {
278 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR; /* RF off */
279 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
280 (u8 *)(&fw_current_inps));
281 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
282 (u8 *)(&ppsc->fwctrl_psmode));
283 rtlhal->allow_sw_to_change_hwclc = true;
284 _rtl92ee_set_fw_clock_off(hw, rpwm_val);
286 rpwm_val = FW_PS_STATE_RF_OFF_92E; /* RF off */
287 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
288 (u8 *)(&fw_current_inps));
289 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
290 (u8 *)(&ppsc->fwctrl_psmode));
291 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
296 void rtl92ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
298 struct rtl_priv *rtlpriv = rtl_priv(hw);
299 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
300 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
304 *((u32 *)(val)) = rtlpci->receive_config;
306 case HW_VAR_RF_STATE:
307 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
309 case HW_VAR_FWLPS_RF_ON:{
310 enum rf_pwrstate rfstate;
313 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
315 if (rfstate == ERFOFF) {
316 *((bool *)(val)) = true;
318 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
319 val_rcr &= 0x00070000;
321 *((bool *)(val)) = false;
323 *((bool *)(val)) = true;
327 case HW_VAR_FW_PSMODE_STATUS:
328 *((bool *)(val)) = ppsc->fw_current_inpsmode;
330 case HW_VAR_CORRECT_TSF:{
332 u32 *ptsf_low = (u32 *)&tsf;
333 u32 *ptsf_high = ((u32 *)&tsf) + 1;
335 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
336 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
338 *((u64 *)(val)) = tsf;
342 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
343 "switch case not process %x\n", variable);
348 static void _rtl92ee_download_rsvd_page(struct ieee80211_hw *hw)
350 struct rtl_priv *rtlpriv = rtl_priv(hw);
351 u8 tmp_regcr, tmp_reg422;
352 u8 bcnvalid_reg, txbc_reg;
353 u8 count = 0, dlbcn_count = 0;
354 bool b_recover = false;
356 /*Set REG_CR bit 8. DMA beacon by SW.*/
357 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
358 rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr | BIT(0));
360 /* Disable Hw protection for a time which revserd for Hw sending beacon.
361 * Fix download reserved page packet fail
362 * that access collision with the protection time.
363 * 2010.05.11. Added by tynli.
365 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
366 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
368 /* Set FWHW_TXQ_CTRL 0x422[6]=0 to
369 * tell Hw the packet is not a real beacon frame.
371 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
372 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));
374 if (tmp_reg422 & BIT(6))
378 /* Clear beacon valid check bit */
379 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2);
380 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2,
381 bcnvalid_reg | BIT(0));
383 /* download rsvd page */
384 rtl92ee_set_fw_rsvdpagepkt(hw, false);
386 txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3);
388 while ((txbc_reg & BIT(4)) && count < 20) {
391 txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3);
393 rtl_write_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3,
396 /* check rsvd page download OK. */
397 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2);
399 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
402 bcnvalid_reg = rtl_read_byte(rtlpriv,
403 REG_DWBCN0_CTRL + 2);
406 if (bcnvalid_reg & BIT(0))
407 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2, BIT(0));
410 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
412 if (!(bcnvalid_reg & BIT(0)))
413 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
414 "Download RSVD page failed!\n");
417 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
418 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
421 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
423 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
424 rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr & (~BIT(0)));
427 void rtl92ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
429 struct rtl_priv *rtlpriv = rtl_priv(hw);
430 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
431 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
432 struct rtl_efuse *efuse = rtl_efuse(rtl_priv(hw));
433 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
437 case HW_VAR_ETHER_ADDR:
438 for (idx = 0; idx < ETH_ALEN; idx++)
439 rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
441 case HW_VAR_BASIC_RATE:{
442 u16 b_rate_cfg = ((u16 *)val)[0];
444 b_rate_cfg = b_rate_cfg & 0x15f;
446 b_rate_cfg = (b_rate_cfg | 0xd) & (~BIT(1));
447 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
448 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);
451 for (idx = 0; idx < ETH_ALEN; idx++)
452 rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
455 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
456 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
458 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
459 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
462 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
464 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
467 case HW_VAR_SLOT_TIME:{
470 RT_TRACE(rtlpriv, COMP_MLME, DBG_TRACE,
471 "HW_VAR_SLOT_TIME %x\n", val[0]);
473 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
475 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
476 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
480 case HW_VAR_ACK_PREAMBLE:{
482 u8 short_preamble = (bool)(*(u8 *)val);
484 reg_tmp = (rtlpriv->mac80211.cur_40_prime_sc) << 5;
487 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
488 rtlpriv->mac80211.short_preamble = short_preamble;
491 case HW_VAR_WPA_CONFIG:
492 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
494 case HW_VAR_AMPDU_FACTOR:{
495 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
500 reg = regtoset_normal;
504 fac = (1 << (fac + 2));
507 for (i = 0; i < 4; i++) {
508 if ((reg[i] & 0xf0) > (fac << 4))
509 reg[i] = (reg[i] & 0x0f) |
511 if ((reg[i] & 0x0f) > fac)
512 reg[i] = (reg[i] & 0xf0) | fac;
513 rtl_write_byte(rtlpriv,
514 (REG_AGGLEN_LMT + i),
517 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
518 "Set HW_VAR_AMPDU_FACTOR:%#x\n", fac);
522 case HW_VAR_AC_PARAM:{
523 u8 e_aci = *((u8 *)val);
525 if (rtlpci->acm_method != EACMWAY2_SW)
526 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
530 case HW_VAR_ACM_CTRL:{
531 u8 e_aci = *((u8 *)val);
532 union aci_aifsn *aifs = (union aci_aifsn *)(&mac->ac[0].aifs);
534 u8 acm = aifs->f.acm;
535 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
537 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
542 acm_ctrl |= ACMHW_BEQEN;
545 acm_ctrl |= ACMHW_VIQEN;
548 acm_ctrl |= ACMHW_VOQEN;
551 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
552 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
559 acm_ctrl &= (~ACMHW_BEQEN);
562 acm_ctrl &= (~ACMHW_VIQEN);
565 acm_ctrl &= (~ACMHW_VOQEN);
568 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
569 "switch case not process\n");
574 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
575 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
577 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
581 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
582 rtlpci->receive_config = ((u32 *)(val))[0];
585 case HW_VAR_RETRY_LIMIT:{
586 u8 retry_limit = ((u8 *)(val))[0];
588 rtl_write_word(rtlpriv, REG_RETRY_LIMIT,
589 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
590 retry_limit << RETRY_LIMIT_LONG_SHIFT);
593 case HW_VAR_DUAL_TSF_RST:
594 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
596 case HW_VAR_EFUSE_BYTES:
597 efuse->efuse_usedbytes = *((u16 *)val);
599 case HW_VAR_EFUSE_USAGE:
600 efuse->efuse_usedpercentage = *((u8 *)val);
603 rtl92ee_phy_set_io_cmd(hw, (*(enum io_type *)val));
605 case HW_VAR_SET_RPWM:{
608 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
611 if (rpwm_val & BIT(7)) {
612 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));
614 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
615 ((*(u8 *)val) | BIT(7)));
619 case HW_VAR_H2C_FW_PWRMODE:
620 rtl92ee_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
622 case HW_VAR_FW_PSMODE_STATUS:
623 ppsc->fw_current_inpsmode = *((bool *)val);
625 case HW_VAR_RESUME_CLK_ON:
626 _rtl92ee_set_fw_ps_rf_on(hw);
628 case HW_VAR_FW_LPS_ACTION:{
629 bool b_enter_fwlps = *((bool *)val);
632 _rtl92ee_fwlps_enter(hw);
634 _rtl92ee_fwlps_leave(hw);
637 case HW_VAR_H2C_FW_JOINBSSRPT:{
638 u8 mstatus = (*(u8 *)val);
640 if (mstatus == RT_MEDIA_CONNECT) {
641 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
642 _rtl92ee_download_rsvd_page(hw);
644 rtl92ee_set_fw_media_status_rpt_cmd(hw, mstatus);
647 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
648 rtl92ee_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
653 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
655 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
656 (u2btmp | mac->assoc_id));
659 case HW_VAR_CORRECT_TSF:{
660 u8 btype_ibss = ((u8 *)(val))[0];
663 _rtl92ee_stop_tx_beacon(hw);
665 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
667 rtl_write_dword(rtlpriv, REG_TSFTR,
668 (u32)(mac->tsf & 0xffffffff));
669 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
670 (u32)((mac->tsf >> 32) & 0xffffffff));
672 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
675 _rtl92ee_resume_tx_beacon(hw);
678 case HW_VAR_KEEP_ALIVE: {
682 array[1] = *((u8 *)val);
683 rtl92ee_fill_h2c_cmd(hw, H2C_92E_KEEP_ALIVE_CTRL, 2, array);
687 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
688 "switch case not process %x\n", variable);
693 static bool _rtl92ee_llt_table_init(struct ieee80211_hw *hw)
695 struct rtl_priv *rtlpriv = rtl_priv(hw);
697 u8 u8tmp, testcnt = 0;
699 txpktbuf_bndy = 0xFA;
701 rtl_write_dword(rtlpriv, REG_RQPN, 0x80E90808);
703 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
704 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x3d00 - 1);
706 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 1, txpktbuf_bndy);
707 rtl_write_byte(rtlpriv, REG_DWBCN1_CTRL + 1, txpktbuf_bndy);
709 rtl_write_byte(rtlpriv, REG_BCNQ_BDNY, txpktbuf_bndy);
710 rtl_write_byte(rtlpriv, REG_BCNQ1_BDNY, txpktbuf_bndy);
712 rtl_write_byte(rtlpriv, REG_MGQ_BDNY, txpktbuf_bndy);
713 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
715 rtl_write_byte(rtlpriv, REG_PBP, 0x31);
716 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
718 u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2);
719 rtl_write_byte(rtlpriv, REG_AUTO_LLT + 2, u8tmp | BIT(0));
721 while (u8tmp & BIT(0)) {
722 u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2);
732 static void _rtl92ee_gen_refresh_led_state(struct ieee80211_hw *hw)
734 struct rtl_priv *rtlpriv = rtl_priv(hw);
735 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
736 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
737 struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0;
739 if (rtlpriv->rtlhal.up_first_time)
742 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
743 rtl92ee_sw_led_on(hw, pled0);
744 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
745 rtl92ee_sw_led_on(hw, pled0);
747 rtl92ee_sw_led_off(hw, pled0);
750 static bool _rtl92ee_init_mac(struct ieee80211_hw *hw)
752 struct rtl_priv *rtlpriv = rtl_priv(hw);
753 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
754 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
760 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
762 dwordtmp = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
763 if (dwordtmp & BIT(24)) {
764 rtl_write_byte(rtlpriv, 0x7c, 0xc3);
766 bytetmp = rtl_read_byte(rtlpriv, 0x16);
767 rtl_write_byte(rtlpriv, 0x16, bytetmp | BIT(4) | BIT(6));
768 rtl_write_byte(rtlpriv, 0x7c, 0x83);
770 /* 1. 40Mhz crystal source*/
771 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2);
773 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp);
775 dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4);
776 dwordtmp &= 0xfffffc7f;
777 rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp);
779 /* 2. 92E AFE parameter
780 * MP chip then check version
782 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2);
784 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp);
786 dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4);
787 dwordtmp &= 0xffdfffff;
788 rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp);
790 /* HW Power on sequence */
791 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
793 RTL8192E_NIC_ENABLE_FLOW)) {
794 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
795 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
799 /* Release MAC IO register reset */
800 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
802 rtl_write_byte(rtlpriv, REG_CR, bytetmp);
805 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
808 /* Add for wakeup online */
809 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
810 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));
811 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
812 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));
813 /* Release MAC IO register reset */
814 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
816 if (!rtlhal->mac_func_enable) {
817 if (_rtl92ee_llt_table_init(hw) == false) {
818 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
819 "LLT table init fail\n");
824 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
825 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
827 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
830 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
831 /* Reported Tx status from HW for rate adaptive.*/
832 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
834 /* Set RCR register */
835 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
836 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
838 /* Set TCR register */
839 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
841 /* Set TX/RX descriptor physical address(from OS API). */
842 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
843 ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) &
845 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
846 (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma &
848 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
849 (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma &
851 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
852 (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma &
855 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
856 (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma &
859 dwordtmp = rtl_read_dword(rtlpriv, REG_BEQ_DESA);
861 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
862 (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma &
864 rtl_write_dword(rtlpriv, REG_HQ0_DESA,
865 (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma &
868 rtl_write_dword(rtlpriv, REG_RX_DESA,
869 (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
872 /* if we want to support 64 bit DMA, we should set it here,
873 * but now we do not support 64 bit DMA
876 rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0x3fffffff);
878 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);
879 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0xF7);
881 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
883 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
885 rtl_write_word(rtlpriv, REG_MGQ_TXBD_NUM,
886 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
887 rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM,
888 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
889 rtl_write_word(rtlpriv, REG_VIQ_TXBD_NUM,
890 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
891 rtl_write_word(rtlpriv, REG_BEQ_TXBD_NUM,
892 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
893 rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM,
894 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
895 rtl_write_word(rtlpriv, REG_BKQ_TXBD_NUM,
896 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
897 rtl_write_word(rtlpriv, REG_HI0Q_TXBD_NUM,
898 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
899 rtl_write_word(rtlpriv, REG_HI1Q_TXBD_NUM,
900 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
901 rtl_write_word(rtlpriv, REG_HI2Q_TXBD_NUM,
902 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
903 rtl_write_word(rtlpriv, REG_HI3Q_TXBD_NUM,
904 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
905 rtl_write_word(rtlpriv, REG_HI4Q_TXBD_NUM,
906 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
907 rtl_write_word(rtlpriv, REG_HI5Q_TXBD_NUM,
908 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
909 rtl_write_word(rtlpriv, REG_HI6Q_TXBD_NUM,
910 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
911 rtl_write_word(rtlpriv, REG_HI7Q_TXBD_NUM,
912 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
914 #if (DMA_IS_64BIT == 1)
915 rtl_write_word(rtlpriv, REG_RX_RXBD_NUM,
917 ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x8000);
919 rtl_write_word(rtlpriv, REG_RX_RXBD_NUM,
921 ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x0000);
924 rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0XFFFFFFFF);
926 _rtl92ee_gen_refresh_led_state(hw);
930 static void _rtl92ee_hw_configure(struct ieee80211_hw *hw)
932 struct rtl_priv *rtlpriv = rtl_priv(hw);
933 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
936 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
937 /* Init value for RRSR. */
938 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
940 /* ARFB table 9 for 11ac 5G 2SS */
941 rtl_write_dword(rtlpriv, REG_ARFR0, 0x00000010);
942 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0x3e0ff000);
944 /* ARFB table 10 for 11ac 5G 1SS */
945 rtl_write_dword(rtlpriv, REG_ARFR1, 0x00000010);
946 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x000ff000);
949 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
951 /* CF-End setting. */
952 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
954 /* Set retry limit */
955 rtl_write_word(rtlpriv, REG_RETRY_LIMIT, 0x0707);
958 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x0201ffff);
960 /* Set Data / Response auto rate fallack retry count */
961 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
962 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
963 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
964 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
966 /* Beacon related, for rate adaptive */
967 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
968 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
970 rtlpci->reg_bcn_ctrl_val = 0x1d;
971 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
973 /* Marked out by Bruce, 2010-09-09.
974 * This register is configured for the 2nd Beacon (multiple BSSID).
975 * We shall disable this register if we only support 1 BSSID.
976 * vivi guess 92d also need this, also 92d now doesnot set this reg
978 rtl_write_byte(rtlpriv, REG_BCN_CTRL_1, 0);
980 /* TBTT prohibit hold time. Suggested by designer TimChen. */
981 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */
983 rtl_write_byte(rtlpriv, REG_PIFS, 0);
984 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
986 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
987 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x08ff);
989 /* For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
990 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
992 /* ACKTO for IOT issue. */
993 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
995 /* Set Spec SIFS (used in NAV) */
996 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x100a);
997 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x100a);
999 /* Set SIFS for CCK */
1000 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x100a);
1002 /* Set SIFS for OFDM */
1003 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x100a);
1005 /* Note Data sheet don't define */
1006 rtl_write_word(rtlpriv, 0x4C7, 0x80);
1008 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1010 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1717);
1012 /* Set Multicast Address. 2009.01.07. by tynli. */
1013 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
1014 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
1017 static void _rtl92ee_enable_aspm_back_door(struct ieee80211_hw *hw)
1019 struct rtl_priv *rtlpriv = rtl_priv(hw);
1020 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1021 u32 tmp32 = 0, count = 0;
1024 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x78);
1025 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1026 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1028 while (tmp8 && count < 20) {
1030 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1035 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1036 if ((tmp32 & 0xff00) != 0x2000) {
1037 tmp32 &= 0xffff00ff;
1038 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1040 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf078);
1041 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1043 tmp8 = rtl_read_byte(rtlpriv,
1044 REG_BACKDOOR_DBI_DATA + 2);
1046 while (tmp8 && count < 20) {
1048 tmp8 = rtl_read_byte(rtlpriv,
1049 REG_BACKDOOR_DBI_DATA + 2);
1055 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x70c);
1056 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1057 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1059 while (tmp8 && count < 20) {
1061 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1065 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1066 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1068 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf70c);
1069 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1072 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1074 while (tmp8 && count < 20) {
1076 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1080 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x718);
1081 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1082 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1084 while (tmp8 && count < 20) {
1086 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1089 if (ppsc->support_backdoor || (0 == tmp8)) {
1090 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1091 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1092 tmp32 | BIT(11) | BIT(12));
1093 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf718);
1094 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1096 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1098 while (tmp8 && count < 20) {
1100 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1105 void rtl92ee_enable_hw_security_config(struct ieee80211_hw *hw)
1107 struct rtl_priv *rtlpriv = rtl_priv(hw);
1111 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1112 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1113 rtlpriv->sec.pairwise_enc_algorithm,
1114 rtlpriv->sec.group_enc_algorithm);
1116 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1117 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1118 "not open hw encryption\n");
1122 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1124 if (rtlpriv->sec.use_defaultkey) {
1125 sec_reg_value |= SCR_TXUSEDK;
1126 sec_reg_value |= SCR_RXUSEDK;
1129 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1131 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1132 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1134 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1135 "The SECR-value %x\n", sec_reg_value);
1137 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1140 static bool _rtl8192ee_check_pcie_dma_hang(struct rtl_priv *rtlpriv)
1144 /* write reg 0x350 Bit[26]=1. Enable debug port. */
1145 tmp = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3);
1146 if (!(tmp & BIT(2))) {
1147 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3,
1149 mdelay(100); /* Suggested by DD Justin_tsai. */
1152 /* read reg 0x350 Bit[25] if 1 : RX hang
1153 * read reg 0x350 Bit[24] if 1 : TX hang
1155 tmp = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3);
1156 if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1157 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1158 "CheckPcieDMAHang8192EE(): true!!\n");
1164 static void _rtl8192ee_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,
1168 bool release_mac_rx_pause;
1169 u8 backup_pcie_dma_pause;
1171 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1172 "ResetPcieInterfaceDMA8192EE()\n");
1174 /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
1175 * released by SD1 Alan.
1178 /* 1. disable register write lock
1179 * write 0x1C bit[1:0] = 2'h0
1180 * write 0xCC bit[2] = 1'b1
1182 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1183 tmp &= ~(BIT(1) | BIT(0));
1184 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1185 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1187 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1189 /* 2. Check and pause TRX DMA
1190 * write 0x284 bit[18] = 1'b1
1191 * write 0x301 = 0xFF
1193 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1195 /* Already pause before the function for another reason. */
1196 release_mac_rx_pause = false;
1198 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1199 release_mac_rx_pause = true;
1202 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1203 if (backup_pcie_dma_pause != 0xFF)
1204 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1207 /* 3. reset TRX function
1208 * write 0x100 = 0x00
1210 rtl_write_byte(rtlpriv, REG_CR, 0);
1213 /* 4. Reset PCIe DMA
1214 * write 0x003 bit[0] = 0
1216 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1218 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1220 /* 5. Enable PCIe DMA
1221 * write 0x003 bit[0] = 1
1223 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1225 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1228 /* 6. enable TRX function
1229 * write 0x100 = 0xFF
1231 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1233 /* We should init LLT & RQPN and
1234 * prepare Tx/Rx descrptor address later
1235 * because MAC function is reset.
1239 /* 7. Restore PCIe autoload down bit
1240 * write 0xF8 bit[17] = 1'b1
1242 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1244 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1246 /* In MAC power on state, BB and RF maybe in ON state,
1247 * if we release TRx DMA here
1248 * it will cause packets to be started to Tx/Rx,
1249 * so we release Tx/Rx DMA later.
1251 if (!mac_power_on) {
1252 /* 8. release TRX DMA
1253 * write 0x284 bit[18] = 1'b0
1254 * write 0x301 = 0x00
1256 if (release_mac_rx_pause) {
1257 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1258 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1261 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1262 backup_pcie_dma_pause);
1265 /* 9. lock system register
1266 * write 0xCC bit[2] = 1'b0
1268 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1270 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1273 int rtl92ee_hw_init(struct ieee80211_hw *hw)
1275 struct rtl_priv *rtlpriv = rtl_priv(hw);
1276 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1277 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1278 struct rtl_phy *rtlphy = &rtlpriv->phy;
1279 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1280 bool rtstatus = true;
1285 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, " Rtl8192EE hw init\n");
1286 rtlpriv->rtlhal.being_init_adapter = true;
1287 rtlpriv->intf_ops->disable_aspm(hw);
1289 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1290 u1byte = rtl_read_byte(rtlpriv, REG_CR);
1291 if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1292 rtlhal->mac_func_enable = true;
1294 rtlhal->mac_func_enable = false;
1295 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E;
1298 if (_rtl8192ee_check_pcie_dma_hang(rtlpriv)) {
1299 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "92ee dma hang!\n");
1300 _rtl8192ee_reset_pcie_interface_dma(rtlpriv,
1301 rtlhal->mac_func_enable);
1302 rtlhal->mac_func_enable = false;
1305 rtstatus = _rtl92ee_init_mac(hw);
1307 rtl_write_byte(rtlpriv, 0x577, 0x03);
1309 /*for Crystal 40 Mhz setting */
1310 rtl_write_byte(rtlpriv, REG_AFE_CTRL4, 0x2A);
1311 rtl_write_byte(rtlpriv, REG_AFE_CTRL4 + 1, 0x00);
1312 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, 0x83);
1314 /*Forced the antenna b to wifi */
1315 if (rtlpriv->btcoexist.btc_info.btcoexist == 1) {
1316 rtl_write_byte(rtlpriv, 0x64, 0);
1317 rtl_write_byte(rtlpriv, 0x65, 1);
1320 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1325 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, 0x8000);
1326 err = rtl92ee_download_fw(hw, false);
1328 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1329 "Failed to download FW. Init HW without FW now..\n");
1331 rtlhal->fw_ready = false;
1334 rtlhal->fw_ready = true;
1335 /*fw related variable initialize */
1336 ppsc->fw_current_inpsmode = false;
1337 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E;
1338 rtlhal->fw_clk_change_in_progress = false;
1339 rtlhal->allow_sw_to_change_hwclc = false;
1340 rtlhal->last_hmeboxnum = 0;
1342 rtl92ee_phy_mac_config(hw);
1344 rtl92ee_phy_bb_config(hw);
1346 rtl92ee_phy_rf_config(hw);
1348 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, RF90_PATH_A,
1349 RF_CHNLBW, RFREG_OFFSET_MASK);
1350 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, RF90_PATH_B,
1351 RF_CHNLBW, RFREG_OFFSET_MASK);
1352 rtlphy->backup_rf_0x1a = (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,
1354 rtlphy->rfreg_chnlval[0] = (rtlphy->rfreg_chnlval[0] & 0xfffff3ff) |
1357 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
1358 rtlphy->rfreg_chnlval[0]);
1359 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
1360 rtlphy->rfreg_chnlval[0]);
1362 /*---- Set CCK and OFDM Block "ON"----*/
1363 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1364 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1367 * otherwise the rx sensitivity will be very pool. Maddest
1369 rtl_set_rfreg(hw, RF90_PATH_A, 0xB1, RFREG_OFFSET_MASK, 0x54418);
1371 /*Set Hardware(MAC default setting.)*/
1372 _rtl92ee_hw_configure(hw);
1374 rtlhal->mac_func_enable = true;
1376 rtl_cam_reset_all_entry(hw);
1377 rtl92ee_enable_hw_security_config(hw);
1379 ppsc->rfpwr_state = ERFON;
1381 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1382 _rtl92ee_enable_aspm_back_door(hw);
1383 rtlpriv->intf_ops->enable_aspm(hw);
1385 rtl92ee_bt_hw_init(hw);
1387 rtlpriv->rtlhal.being_init_adapter = false;
1389 if (ppsc->rfpwr_state == ERFON) {
1390 if (rtlphy->iqk_initialized) {
1391 rtl92ee_phy_iq_calibrate(hw, true);
1393 rtl92ee_phy_iq_calibrate(hw, false);
1394 rtlphy->iqk_initialized = true;
1398 rtlphy->rfpath_rx_enable[0] = true;
1399 if (rtlphy->rf_type == RF_2T2R)
1400 rtlphy->rfpath_rx_enable[1] = true;
1402 efuse_one_byte_read(hw, 0x1FA, &tmp_u1b);
1403 if (!(tmp_u1b & BIT(0))) {
1404 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1405 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1408 if ((!(tmp_u1b & BIT(1))) && (rtlphy->rf_type == RF_2T2R)) {
1409 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1410 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path B\n");
1413 rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
1415 /*Fixed LDPC rx hang issue. */
1416 tmp_u4b = rtl_read_dword(rtlpriv, REG_SYS_SWR_CTRL1);
1417 rtl_write_byte(rtlpriv, REG_SYS_SWR_CTRL2, 0x75);
1418 tmp_u4b = (tmp_u4b & 0xfff00fff) | (0x7E << 12);
1419 rtl_write_dword(rtlpriv, REG_SYS_SWR_CTRL1, tmp_u4b);
1421 rtl92ee_dm_init(hw);
1423 rtl_write_dword(rtlpriv, 0x4fc, 0);
1425 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1426 "end of Rtl8192EE hw init %x\n", err);
1430 static enum version_8192e _rtl92ee_read_chip_version(struct ieee80211_hw *hw)
1432 struct rtl_priv *rtlpriv = rtl_priv(hw);
1433 struct rtl_phy *rtlphy = &rtlpriv->phy;
1434 enum version_8192e version = VERSION_UNKNOWN;
1437 rtlphy->rf_type = RF_2T2R;
1439 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1440 if (value32 & TRP_VAUX_EN)
1441 version = (enum version_8192e)VERSION_TEST_CHIP_2T2R_8192E;
1443 version = (enum version_8192e)VERSION_NORMAL_CHIP_2T2R_8192E;
1445 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1446 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1447 "RF_2T2R" : "RF_1T1R");
1452 static int _rtl92ee_set_media_status(struct ieee80211_hw *hw,
1453 enum nl80211_iftype type)
1455 struct rtl_priv *rtlpriv = rtl_priv(hw);
1456 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1457 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1458 u8 mode = MSR_NOLINK;
1461 case NL80211_IFTYPE_UNSPECIFIED:
1463 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1464 "Set Network type to NO LINK!\n");
1466 case NL80211_IFTYPE_ADHOC:
1467 case NL80211_IFTYPE_MESH_POINT:
1469 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1470 "Set Network type to Ad Hoc!\n");
1472 case NL80211_IFTYPE_STATION:
1474 ledaction = LED_CTL_LINK;
1475 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1476 "Set Network type to STA!\n");
1478 case NL80211_IFTYPE_AP:
1480 ledaction = LED_CTL_LINK;
1481 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1482 "Set Network type to AP!\n");
1485 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1486 "Network type %d not support!\n", type);
1490 /* MSR_INFRA == Link in infrastructure network;
1491 * MSR_ADHOC == Link in ad hoc network;
1492 * Therefore, check link state is necessary.
1494 * MSR_AP == AP mode; link state is not cared here.
1496 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1498 ledaction = LED_CTL_NO_LINK;
1501 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1502 _rtl92ee_stop_tx_beacon(hw);
1503 _rtl92ee_enable_bcn_sub_func(hw);
1504 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1505 _rtl92ee_resume_tx_beacon(hw);
1506 _rtl92ee_disable_bcn_sub_func(hw);
1508 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1509 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1513 rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1514 rtlpriv->cfg->ops->led_control(hw, ledaction);
1516 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1518 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1522 void rtl92ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1524 struct rtl_priv *rtlpriv = rtl_priv(hw);
1525 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1526 u32 reg_rcr = rtlpci->receive_config;
1528 if (rtlpriv->psc.rfpwr_state != ERFON)
1532 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1533 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1535 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1537 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1538 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1539 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1544 int rtl92ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1546 struct rtl_priv *rtlpriv = rtl_priv(hw);
1548 if (_rtl92ee_set_media_status(hw, type))
1551 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1552 if (type != NL80211_IFTYPE_AP &&
1553 type != NL80211_IFTYPE_MESH_POINT)
1554 rtl92ee_set_check_bssid(hw, true);
1556 rtl92ee_set_check_bssid(hw, false);
1562 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1563 void rtl92ee_set_qos(struct ieee80211_hw *hw, int aci)
1565 struct rtl_priv *rtlpriv = rtl_priv(hw);
1567 rtl92ee_dm_init_edca_turbo(hw);
1570 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1573 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1576 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1579 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1582 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1587 static void rtl92ee_clear_interrupt(struct ieee80211_hw *hw)
1589 struct rtl_priv *rtlpriv = rtl_priv(hw);
1592 tmp = rtl_read_dword(rtlpriv, REG_HISR);
1593 rtl_write_dword(rtlpriv, REG_HISR, tmp);
1595 tmp = rtl_read_dword(rtlpriv, REG_HISRE);
1596 rtl_write_dword(rtlpriv, REG_HISRE, tmp);
1598 tmp = rtl_read_dword(rtlpriv, REG_HSISR);
1599 rtl_write_dword(rtlpriv, REG_HSISR, tmp);
1602 void rtl92ee_enable_interrupt(struct ieee80211_hw *hw)
1604 struct rtl_priv *rtlpriv = rtl_priv(hw);
1605 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1607 rtl92ee_clear_interrupt(hw);/*clear it here first*/
1609 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1610 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1611 rtlpci->irq_enabled = true;
1614 void rtl92ee_disable_interrupt(struct ieee80211_hw *hw)
1616 struct rtl_priv *rtlpriv = rtl_priv(hw);
1617 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1619 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1620 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1621 rtlpci->irq_enabled = false;
1622 /*synchronize_irq(rtlpci->pdev->irq);*/
1625 static void _rtl92ee_poweroff_adapter(struct ieee80211_hw *hw)
1627 struct rtl_priv *rtlpriv = rtl_priv(hw);
1628 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1631 rtlhal->mac_func_enable = false;
1633 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1635 /* Run LPS WL RFOFF flow */
1636 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1637 PWR_INTF_PCI_MSK, RTL8192E_NIC_LPS_ENTER_FLOW);
1639 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1641 /* ==== Reset digital sequence ====== */
1642 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1643 rtl92ee_firmware_selfreset(hw);
1646 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1647 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1649 /* reset MCU ready status */
1650 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1652 /* HW card disable configuration. */
1653 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1654 PWR_INTF_PCI_MSK, RTL8192E_NIC_DISABLE_FLOW);
1656 /* Reset MCU IO Wrapper */
1657 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1658 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1659 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1660 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0)));
1662 /* lock ISO/CLK/Power control register */
1663 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1666 void rtl92ee_card_disable(struct ieee80211_hw *hw)
1668 struct rtl_priv *rtlpriv = rtl_priv(hw);
1669 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1670 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1671 enum nl80211_iftype opmode;
1673 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8192ee card disable\n");
1675 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1677 mac->link_state = MAC80211_NOLINK;
1678 opmode = NL80211_IFTYPE_UNSPECIFIED;
1680 _rtl92ee_set_media_status(hw, opmode);
1682 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1683 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1684 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1686 _rtl92ee_poweroff_adapter(hw);
1688 /* after power off we should do iqk again */
1689 rtlpriv->phy.iqk_initialized = false;
1692 void rtl92ee_interrupt_recognized(struct ieee80211_hw *hw,
1693 u32 *p_inta, u32 *p_intb)
1695 struct rtl_priv *rtlpriv = rtl_priv(hw);
1696 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1698 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1699 rtl_write_dword(rtlpriv, ISR, *p_inta);
1701 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1702 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1705 void rtl92ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1707 struct rtl_priv *rtlpriv = rtl_priv(hw);
1708 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1709 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1710 u16 bcn_interval, atim_window;
1712 bcn_interval = mac->beacon_interval;
1713 atim_window = 2; /*FIX MERGE */
1714 rtl92ee_disable_interrupt(hw);
1715 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1716 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1717 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1718 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1719 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1720 rtl_write_byte(rtlpriv, 0x606, 0x30);
1721 rtlpci->reg_bcn_ctrl_val |= BIT(3);
1722 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
1725 void rtl92ee_set_beacon_interval(struct ieee80211_hw *hw)
1727 struct rtl_priv *rtlpriv = rtl_priv(hw);
1728 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1729 u16 bcn_interval = mac->beacon_interval;
1731 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1732 "beacon_interval:%d\n", bcn_interval);
1733 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1736 void rtl92ee_update_interrupt_mask(struct ieee80211_hw *hw,
1737 u32 add_msr, u32 rm_msr)
1739 struct rtl_priv *rtlpriv = rtl_priv(hw);
1740 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1742 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1743 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1746 rtlpci->irq_mask[0] |= add_msr;
1748 rtlpci->irq_mask[0] &= (~rm_msr);
1749 rtl92ee_disable_interrupt(hw);
1750 rtl92ee_enable_interrupt(hw);
1753 static u8 _rtl92ee_get_chnl_group(u8 chnl)
1758 if (1 <= chnl && chnl <= 2)
1760 else if (3 <= chnl && chnl <= 5)
1762 else if (6 <= chnl && chnl <= 8)
1764 else if (9 <= chnl && chnl <= 11)
1766 else if (12 <= chnl && chnl <= 14)
1769 if (36 <= chnl && chnl <= 42)
1771 else if (44 <= chnl && chnl <= 48)
1773 else if (50 <= chnl && chnl <= 58)
1775 else if (60 <= chnl && chnl <= 64)
1777 else if (100 <= chnl && chnl <= 106)
1779 else if (108 <= chnl && chnl <= 114)
1781 else if (116 <= chnl && chnl <= 122)
1783 else if (124 <= chnl && chnl <= 130)
1785 else if (132 <= chnl && chnl <= 138)
1787 else if (140 <= chnl && chnl <= 144)
1789 else if (149 <= chnl && chnl <= 155)
1791 else if (157 <= chnl && chnl <= 161)
1793 else if (165 <= chnl && chnl <= 171)
1795 else if (173 <= chnl && chnl <= 177)
1801 static void _rtl8192ee_read_power_value_fromprom(struct ieee80211_hw *hw,
1802 struct txpower_info_2g *pwr2g,
1803 struct txpower_info_5g *pwr5g,
1804 bool autoload_fail, u8 *hwinfo)
1806 struct rtl_priv *rtlpriv = rtl_priv(hw);
1807 u32 rf, addr = EEPROM_TX_PWR_INX, group, i = 0;
1809 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1810 "hal_ReadPowerValueFromPROM92E(): PROMContent[0x%x]=0x%x\n",
1811 (addr + 1), hwinfo[addr + 1]);
1812 if (0xFF == hwinfo[addr+1]) /*YJ,add,120316*/
1813 autoload_fail = true;
1815 if (autoload_fail) {
1816 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1817 "auto load fail : Use Default value!\n");
1818 for (rf = 0 ; rf < MAX_RF_PATH ; rf++) {
1819 /* 2.4G default value */
1820 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1821 pwr2g->index_cck_base[rf][group] = 0x2D;
1822 pwr2g->index_bw40_base[rf][group] = 0x2D;
1824 for (i = 0; i < MAX_TX_COUNT; i++) {
1826 pwr2g->bw20_diff[rf][0] = 0x02;
1827 pwr2g->ofdm_diff[rf][0] = 0x04;
1829 pwr2g->bw20_diff[rf][i] = 0xFE;
1830 pwr2g->bw40_diff[rf][i] = 0xFE;
1831 pwr2g->cck_diff[rf][i] = 0xFE;
1832 pwr2g->ofdm_diff[rf][i] = 0xFE;
1836 /*5G default value*/
1837 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
1838 pwr5g->index_bw40_base[rf][group] = 0x2A;
1840 for (i = 0; i < MAX_TX_COUNT; i++) {
1842 pwr5g->ofdm_diff[rf][0] = 0x04;
1843 pwr5g->bw20_diff[rf][0] = 0x00;
1844 pwr5g->bw80_diff[rf][0] = 0xFE;
1845 pwr5g->bw160_diff[rf][0] = 0xFE;
1847 pwr5g->ofdm_diff[rf][0] = 0xFE;
1848 pwr5g->bw20_diff[rf][0] = 0xFE;
1849 pwr5g->bw40_diff[rf][0] = 0xFE;
1850 pwr5g->bw80_diff[rf][0] = 0xFE;
1851 pwr5g->bw160_diff[rf][0] = 0xFE;
1858 rtl_priv(hw)->efuse.txpwr_fromeprom = true;
1860 for (rf = 0 ; rf < MAX_RF_PATH ; rf++) {
1861 /*2.4G default value*/
1862 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1863 pwr2g->index_cck_base[rf][group] = hwinfo[addr++];
1864 if (pwr2g->index_cck_base[rf][group] == 0xFF)
1865 pwr2g->index_cck_base[rf][group] = 0x2D;
1867 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
1868 pwr2g->index_bw40_base[rf][group] = hwinfo[addr++];
1869 if (pwr2g->index_bw40_base[rf][group] == 0xFF)
1870 pwr2g->index_bw40_base[rf][group] = 0x2D;
1872 for (i = 0; i < MAX_TX_COUNT; i++) {
1874 pwr2g->bw40_diff[rf][i] = 0;
1875 if (hwinfo[addr] == 0xFF) {
1876 pwr2g->bw20_diff[rf][i] = 0x02;
1878 pwr2g->bw20_diff[rf][i] = (hwinfo[addr]
1880 if (pwr2g->bw20_diff[rf][i] & BIT(3))
1881 pwr2g->bw20_diff[rf][i] |= 0xF0;
1884 if (hwinfo[addr] == 0xFF) {
1885 pwr2g->ofdm_diff[rf][i] = 0x04;
1887 pwr2g->ofdm_diff[rf][i] = (hwinfo[addr]
1889 if (pwr2g->ofdm_diff[rf][i] & BIT(3))
1890 pwr2g->ofdm_diff[rf][i] |= 0xF0;
1892 pwr2g->cck_diff[rf][i] = 0;
1895 if (hwinfo[addr] == 0xFF) {
1896 pwr2g->bw40_diff[rf][i] = 0xFE;
1898 pwr2g->bw40_diff[rf][i] = (hwinfo[addr]
1900 if (pwr2g->bw40_diff[rf][i] & BIT(3))
1901 pwr2g->bw40_diff[rf][i] |= 0xF0;
1904 if (hwinfo[addr] == 0xFF) {
1905 pwr2g->bw20_diff[rf][i] = 0xFE;
1907 pwr2g->bw20_diff[rf][i] = (hwinfo[addr]
1909 if (pwr2g->bw20_diff[rf][i] & BIT(3))
1910 pwr2g->bw20_diff[rf][i] |= 0xF0;
1914 if (hwinfo[addr] == 0xFF) {
1915 pwr2g->ofdm_diff[rf][i] = 0xFE;
1917 pwr2g->ofdm_diff[rf][i] = (hwinfo[addr]
1919 if (pwr2g->ofdm_diff[rf][i] & BIT(3))
1920 pwr2g->ofdm_diff[rf][i] |= 0xF0;
1923 if (hwinfo[addr] == 0xFF) {
1924 pwr2g->cck_diff[rf][i] = 0xFE;
1926 pwr2g->cck_diff[rf][i] = (hwinfo[addr]
1928 if (pwr2g->cck_diff[rf][i] & BIT(3))
1929 pwr2g->cck_diff[rf][i] |= 0xF0;
1935 /*5G default value*/
1936 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
1937 pwr5g->index_bw40_base[rf][group] = hwinfo[addr++];
1938 if (pwr5g->index_bw40_base[rf][group] == 0xFF)
1939 pwr5g->index_bw40_base[rf][group] = 0xFE;
1942 for (i = 0; i < MAX_TX_COUNT; i++) {
1944 pwr5g->bw40_diff[rf][i] = 0;
1946 if (hwinfo[addr] == 0xFF) {
1947 pwr5g->bw20_diff[rf][i] = 0;
1949 pwr5g->bw20_diff[rf][0] = (hwinfo[addr]
1951 if (pwr5g->bw20_diff[rf][i] & BIT(3))
1952 pwr5g->bw20_diff[rf][i] |= 0xF0;
1955 if (hwinfo[addr] == 0xFF) {
1956 pwr5g->ofdm_diff[rf][i] = 0x04;
1958 pwr5g->ofdm_diff[rf][0] = (hwinfo[addr]
1960 if (pwr5g->ofdm_diff[rf][i] & BIT(3))
1961 pwr5g->ofdm_diff[rf][i] |= 0xF0;
1965 if (hwinfo[addr] == 0xFF) {
1966 pwr5g->bw40_diff[rf][i] = 0xFE;
1968 pwr5g->bw40_diff[rf][i] = (hwinfo[addr]
1970 if (pwr5g->bw40_diff[rf][i] & BIT(3))
1971 pwr5g->bw40_diff[rf][i] |= 0xF0;
1974 if (hwinfo[addr] == 0xFF) {
1975 pwr5g->bw20_diff[rf][i] = 0xFE;
1977 pwr5g->bw20_diff[rf][i] = (hwinfo[addr]
1979 if (pwr5g->bw20_diff[rf][i] & BIT(3))
1980 pwr5g->bw20_diff[rf][i] |= 0xF0;
1986 if (hwinfo[addr] == 0xFF) {
1987 pwr5g->ofdm_diff[rf][1] = 0xFE;
1988 pwr5g->ofdm_diff[rf][2] = 0xFE;
1990 pwr5g->ofdm_diff[rf][1] = (hwinfo[addr] & 0xf0) >> 4;
1991 pwr5g->ofdm_diff[rf][2] = (hwinfo[addr] & 0x0f);
1995 if (hwinfo[addr] == 0xFF)
1996 pwr5g->ofdm_diff[rf][3] = 0xFE;
1998 pwr5g->ofdm_diff[rf][3] = (hwinfo[addr] & 0x0f);
2001 for (i = 1; i < MAX_TX_COUNT; i++) {
2002 if (pwr5g->ofdm_diff[rf][i] == 0xFF)
2003 pwr5g->ofdm_diff[rf][i] = 0xFE;
2004 else if (pwr5g->ofdm_diff[rf][i] & BIT(3))
2005 pwr5g->ofdm_diff[rf][i] |= 0xF0;
2008 for (i = 0; i < MAX_TX_COUNT; i++) {
2009 if (hwinfo[addr] == 0xFF) {
2010 pwr5g->bw80_diff[rf][i] = 0xFE;
2012 pwr5g->bw80_diff[rf][i] = (hwinfo[addr] & 0xf0)
2014 if (pwr5g->bw80_diff[rf][i] & BIT(3))
2015 pwr5g->bw80_diff[rf][i] |= 0xF0;
2018 if (hwinfo[addr] == 0xFF) {
2019 pwr5g->bw160_diff[rf][i] = 0xFE;
2021 pwr5g->bw160_diff[rf][i] =
2022 (hwinfo[addr] & 0x0f);
2023 if (pwr5g->bw160_diff[rf][i] & BIT(3))
2024 pwr5g->bw160_diff[rf][i] |= 0xF0;
2031 static void _rtl92ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2032 bool autoload_fail, u8 *hwinfo)
2034 struct rtl_priv *rtlpriv = rtl_priv(hw);
2035 struct rtl_efuse *efu = rtl_efuse(rtl_priv(hw));
2036 struct txpower_info_2g pwr2g;
2037 struct txpower_info_5g pwr5g;
2038 u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
2039 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
2040 56, 58, 60, 62, 64, 100, 102, 104, 106,
2041 108, 110, 112, 114, 116, 118, 120, 122,
2042 124, 126, 128, 130, 132, 134, 136, 138,
2043 140, 142, 144, 149, 151, 153, 155, 157,
2044 159, 161, 163, 165, 167, 168, 169, 171,
2047 u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {
2048 42, 58, 106, 122, 138, 155, 171
2053 _rtl8192ee_read_power_value_fromprom(hw, &pwr2g, &pwr5g,
2054 autoload_fail, hwinfo);
2056 for (rf = 0; rf < MAX_RF_PATH; rf++) {
2057 for (i = 0; i < 14; i++) {
2058 idx = _rtl92ee_get_chnl_group(i + 1);
2060 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2061 efu->txpwrlevel_cck[rf][i] =
2062 pwr2g.index_cck_base[rf][5];
2063 efu->txpwrlevel_ht40_1s[rf][i] =
2064 pwr2g.index_bw40_base[rf][idx];
2066 efu->txpwrlevel_cck[rf][i] =
2067 pwr2g.index_cck_base[rf][idx];
2068 efu->txpwrlevel_ht40_1s[rf][i] =
2069 pwr2g.index_bw40_base[rf][idx];
2072 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2073 idx = _rtl92ee_get_chnl_group(channel5g[i]);
2074 efu->txpwr_5g_bw40base[rf][i] =
2075 pwr5g.index_bw40_base[rf][idx];
2077 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2080 idx = _rtl92ee_get_chnl_group(channel5g_80m[i]);
2081 upper = pwr5g.index_bw40_base[rf][idx];
2082 lower = pwr5g.index_bw40_base[rf][idx + 1];
2084 efu->txpwr_5g_bw80base[rf][i] = (upper + lower) / 2;
2086 for (i = 0; i < MAX_TX_COUNT; i++) {
2087 efu->txpwr_cckdiff[rf][i] = pwr2g.cck_diff[rf][i];
2088 efu->txpwr_legacyhtdiff[rf][i] = pwr2g.ofdm_diff[rf][i];
2089 efu->txpwr_ht20diff[rf][i] = pwr2g.bw20_diff[rf][i];
2090 efu->txpwr_ht40diff[rf][i] = pwr2g.bw40_diff[rf][i];
2092 efu->txpwr_5g_ofdmdiff[rf][i] = pwr5g.ofdm_diff[rf][i];
2093 efu->txpwr_5g_bw20diff[rf][i] = pwr5g.bw20_diff[rf][i];
2094 efu->txpwr_5g_bw40diff[rf][i] = pwr5g.bw40_diff[rf][i];
2095 efu->txpwr_5g_bw80diff[rf][i] = pwr5g.bw80_diff[rf][i];
2100 efu->eeprom_thermalmeter = hwinfo[EEPROM_THERMAL_METER_92E];
2102 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
2104 if (efu->eeprom_thermalmeter == 0xff || autoload_fail) {
2105 efu->apk_thermalmeterignore = true;
2106 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
2109 efu->thermalmeter[0] = efu->eeprom_thermalmeter;
2110 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2111 "thermalmeter = 0x%x\n", efu->eeprom_thermalmeter);
2113 if (!autoload_fail) {
2114 efu->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION_92E]
2116 if (hwinfo[EEPROM_RF_BOARD_OPTION_92E] == 0xFF)
2117 efu->eeprom_regulatory = 0;
2119 efu->eeprom_regulatory = 0;
2121 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2122 "eeprom_regulatory = 0x%x\n", efu->eeprom_regulatory);
2125 static void _rtl92ee_read_adapter_info(struct ieee80211_hw *hw)
2127 struct rtl_priv *rtlpriv = rtl_priv(hw);
2128 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2129 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2131 u8 hwinfo[HWSET_MAX_SIZE];
2134 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
2135 rtl_efuse_shadow_map_update(hw);
2137 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
2139 } else if (rtlefuse->epromtype == EEPROM_93C46) {
2140 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2141 "RTL819X Not boot from eeprom, check it !!");
2144 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2145 "boot from neither eeprom nor efuse, check it !!");
2149 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n",
2150 hwinfo, HWSET_MAX_SIZE);
2152 eeprom_id = *((u16 *)&hwinfo[0]);
2153 if (eeprom_id != RTL8192E_EEPROM_ID) {
2154 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2155 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
2156 rtlefuse->autoload_failflag = true;
2158 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2159 rtlefuse->autoload_failflag = false;
2162 if (rtlefuse->autoload_failflag)
2164 /*VID DID SVID SDID*/
2165 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
2166 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
2167 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
2168 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
2169 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROMId = 0x%4x\n", eeprom_id);
2170 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2171 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
2172 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2173 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
2174 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2175 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
2176 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2177 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
2179 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
2180 if (rtlefuse->eeprom_oemid == 0xFF)
2181 rtlefuse->eeprom_oemid = 0;
2183 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2184 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
2186 rtlefuse->eeprom_version = *(u8 *)&hwinfo[EEPROM_VERSION];
2188 for (i = 0; i < 6; i += 2) {
2189 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
2190 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
2193 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2194 "dev_addr: %pM\n", rtlefuse->dev_addr);
2196 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
2197 /* set channel paln to world wide 13 */
2198 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
2200 _rtl92ee_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2203 rtl92ee_read_bt_coexist_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2207 rtlefuse->board_type = (((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E])
2209 if ((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E]) == 0xFF)
2210 rtlefuse->board_type = 0;
2212 rtlhal->board_type = rtlefuse->board_type;
2214 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_92E];
2215 if (hwinfo[EEPROM_XTAL_92E] == 0xFF)
2216 rtlefuse->crystalcap = 0x20;
2218 /*antenna diversity*/
2219 rtlefuse->antenna_div_type = NO_ANTDIV;
2220 rtlefuse->antenna_div_cfg = 0;
2222 if (rtlhal->oem_id == RT_CID_DEFAULT) {
2223 switch (rtlefuse->eeprom_oemid) {
2224 case EEPROM_CID_DEFAULT:
2225 if (rtlefuse->eeprom_did == 0x818B) {
2226 if ((rtlefuse->eeprom_svid == 0x10EC) &&
2227 (rtlefuse->eeprom_smid == 0x001B))
2228 rtlhal->oem_id = RT_CID_819X_LENOVO;
2230 rtlhal->oem_id = RT_CID_DEFAULT;
2234 rtlhal->oem_id = RT_CID_DEFAULT;
2240 static void _rtl92ee_hal_customized_behavior(struct ieee80211_hw *hw)
2242 struct rtl_priv *rtlpriv = rtl_priv(hw);
2243 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2244 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2246 pcipriv->ledctl.led_opendrain = true;
2248 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2249 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2252 void rtl92ee_read_eeprom_info(struct ieee80211_hw *hw)
2254 struct rtl_priv *rtlpriv = rtl_priv(hw);
2255 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2256 struct rtl_phy *rtlphy = &rtlpriv->phy;
2257 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2260 rtlhal->version = _rtl92ee_read_chip_version(hw);
2261 if (get_rf_type(rtlphy) == RF_1T1R) {
2262 rtlpriv->dm.rfpath_rxenable[0] = true;
2264 rtlpriv->dm.rfpath_rxenable[0] = true;
2265 rtlpriv->dm.rfpath_rxenable[1] = true;
2267 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2269 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2270 if (tmp_u1b & BIT(4)) {
2271 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2272 rtlefuse->epromtype = EEPROM_93C46;
2274 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2275 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2277 if (tmp_u1b & BIT(5)) {
2278 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2279 rtlefuse->autoload_failflag = false;
2280 _rtl92ee_read_adapter_info(hw);
2282 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2284 _rtl92ee_hal_customized_behavior(hw);
2286 rtlphy->rfpath_rx_enable[0] = true;
2287 if (rtlphy->rf_type == RF_2T2R)
2288 rtlphy->rfpath_rx_enable[1] = true;
2291 static u8 _rtl92ee_mrate_idx_to_arfr_id(struct ieee80211_hw *hw, u8 rate_index)
2295 switch (rate_index) {
2296 case RATR_INX_WIRELESS_NGB:
2299 case RATR_INX_WIRELESS_N:
2300 case RATR_INX_WIRELESS_NG:
2303 case RATR_INX_WIRELESS_NB:
2306 case RATR_INX_WIRELESS_GB:
2309 case RATR_INX_WIRELESS_G:
2312 case RATR_INX_WIRELESS_B:
2322 static void rtl92ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2323 struct ieee80211_sta *sta,
2326 struct rtl_priv *rtlpriv = rtl_priv(hw);
2327 struct rtl_phy *rtlphy = &rtlpriv->phy;
2328 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2329 struct rtl_sta_info *sta_entry = NULL;
2332 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2334 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2336 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2338 enum wireless_mode wirelessmode = 0;
2339 bool b_shortgi = false;
2340 u8 rate_mask[7] = {0};
2342 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2343 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2344 wirelessmode = sta_entry->wireless_mode;
2345 if (mac->opmode == NL80211_IFTYPE_STATION ||
2346 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2347 curtxbw_40mhz = mac->bw_40;
2348 else if (mac->opmode == NL80211_IFTYPE_AP ||
2349 mac->opmode == NL80211_IFTYPE_ADHOC)
2350 macid = sta->aid + 1;
2352 ratr_bitmap = sta->supp_rates[0];
2353 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2354 ratr_bitmap = 0xfff;
2356 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2357 sta->ht_cap.mcs.rx_mask[0] << 12);
2359 switch (wirelessmode) {
2360 case WIRELESS_MODE_B:
2361 ratr_index = RATR_INX_WIRELESS_B;
2362 if (ratr_bitmap & 0x0000000c)
2363 ratr_bitmap &= 0x0000000d;
2365 ratr_bitmap &= 0x0000000f;
2367 case WIRELESS_MODE_G:
2368 ratr_index = RATR_INX_WIRELESS_GB;
2370 if (rssi_level == 1)
2371 ratr_bitmap &= 0x00000f00;
2372 else if (rssi_level == 2)
2373 ratr_bitmap &= 0x00000ff0;
2375 ratr_bitmap &= 0x00000ff5;
2377 case WIRELESS_MODE_N_24G:
2379 ratr_index = RATR_INX_WIRELESS_NGB;
2381 ratr_index = RATR_INX_WIRELESS_NB;
2383 if (rtlphy->rf_type == RF_1T1R) {
2384 if (curtxbw_40mhz) {
2385 if (rssi_level == 1)
2386 ratr_bitmap &= 0x000f0000;
2387 else if (rssi_level == 2)
2388 ratr_bitmap &= 0x000ff000;
2390 ratr_bitmap &= 0x000ff015;
2392 if (rssi_level == 1)
2393 ratr_bitmap &= 0x000f0000;
2394 else if (rssi_level == 2)
2395 ratr_bitmap &= 0x000ff000;
2397 ratr_bitmap &= 0x000ff005;
2400 if (curtxbw_40mhz) {
2401 if (rssi_level == 1)
2402 ratr_bitmap &= 0x0f8f0000;
2403 else if (rssi_level == 2)
2404 ratr_bitmap &= 0x0ffff000;
2406 ratr_bitmap &= 0x0ffff015;
2408 if (rssi_level == 1)
2409 ratr_bitmap &= 0x0f8f0000;
2410 else if (rssi_level == 2)
2411 ratr_bitmap &= 0x0ffff000;
2413 ratr_bitmap &= 0x0ffff005;
2417 if ((curtxbw_40mhz && b_curshortgi_40mhz) ||
2418 (!curtxbw_40mhz && b_curshortgi_20mhz)) {
2421 else if (macid == 1)
2426 ratr_index = RATR_INX_WIRELESS_NGB;
2428 if (rtlphy->rf_type == RF_1T1R)
2429 ratr_bitmap &= 0x000ff0ff;
2431 ratr_bitmap &= 0x0f8ff0ff;
2434 ratr_index = _rtl92ee_mrate_idx_to_arfr_id(hw, ratr_index);
2435 sta_entry->ratr_index = ratr_index;
2437 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2438 "ratr_bitmap :%x\n", ratr_bitmap);
2439 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2441 rate_mask[0] = macid;
2442 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
2443 rate_mask[2] = curtxbw_40mhz;
2444 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2445 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2446 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2447 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2448 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2449 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2450 ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1],
2451 rate_mask[2], rate_mask[3], rate_mask[4],
2452 rate_mask[5], rate_mask[6]);
2453 rtl92ee_fill_h2c_cmd(hw, H2C_92E_RA_MASK, 7, rate_mask);
2454 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2457 void rtl92ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2458 struct ieee80211_sta *sta, u8 rssi_level)
2460 struct rtl_priv *rtlpriv = rtl_priv(hw);
2462 if (rtlpriv->dm.useramask)
2463 rtl92ee_update_hal_rate_mask(hw, sta, rssi_level);
2466 void rtl92ee_update_channel_access_setting(struct ieee80211_hw *hw)
2468 struct rtl_priv *rtlpriv = rtl_priv(hw);
2469 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2472 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2473 (u8 *)&mac->slot_time);
2474 if (!mac->ht_enable)
2475 sifs_timer = 0x0a0a;
2477 sifs_timer = 0x0e0e;
2478 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2481 bool rtl92ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2487 void rtl92ee_set_key(struct ieee80211_hw *hw, u32 key_index,
2488 u8 *p_macaddr, bool is_group, u8 enc_algo,
2489 bool is_wepkey, bool clear_all)
2491 struct rtl_priv *rtlpriv = rtl_priv(hw);
2492 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2493 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2494 u8 *macaddr = p_macaddr;
2496 bool is_pairwise = false;
2498 static u8 cam_const_addr[4][6] = {
2499 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2500 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2501 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2502 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2504 static u8 cam_const_broad[] = {
2505 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2511 u8 clear_number = 5;
2513 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2515 for (idx = 0; idx < clear_number; idx++) {
2516 rtl_cam_mark_invalid(hw, cam_offset + idx);
2517 rtl_cam_empty_entry(hw, cam_offset + idx);
2520 memset(rtlpriv->sec.key_buf[idx], 0,
2522 rtlpriv->sec.key_len[idx] = 0;
2528 case WEP40_ENCRYPTION:
2529 enc_algo = CAM_WEP40;
2531 case WEP104_ENCRYPTION:
2532 enc_algo = CAM_WEP104;
2534 case TKIP_ENCRYPTION:
2535 enc_algo = CAM_TKIP;
2537 case AESCCMP_ENCRYPTION:
2541 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
2542 "switch case not process\n");
2543 enc_algo = CAM_TKIP;
2547 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2548 macaddr = cam_const_addr[key_index];
2549 entry_id = key_index;
2552 macaddr = cam_const_broad;
2553 entry_id = key_index;
2555 if (mac->opmode == NL80211_IFTYPE_AP ||
2556 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2557 entry_id = rtl_cam_get_free_entry(hw,
2559 if (entry_id >= TOTAL_CAM_ENTRY) {
2560 RT_TRACE(rtlpriv, COMP_SEC,
2562 "Can not find free hw security cam entry\n");
2566 entry_id = CAM_PAIRWISE_KEY_POSITION;
2569 key_index = PAIRWISE_KEYIDX;
2574 if (rtlpriv->sec.key_len[key_index] == 0) {
2575 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2576 "delete one entry, entry_id is %d\n",
2578 if (mac->opmode == NL80211_IFTYPE_AP ||
2579 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2580 rtl_cam_del_entry(hw, p_macaddr);
2581 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2583 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2586 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2587 "set Pairwiase key\n");
2589 rtl_cam_add_one_entry(hw, macaddr, key_index,
2591 CAM_CONFIG_NO_USEDK,
2592 rtlpriv->sec.key_buf[key_index]);
2594 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2597 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2598 rtl_cam_add_one_entry(hw,
2601 CAM_PAIRWISE_KEY_POSITION,
2602 enc_algo, CAM_CONFIG_NO_USEDK,
2603 rtlpriv->sec.key_buf[entry_id]);
2606 rtl_cam_add_one_entry(hw, macaddr, key_index,
2608 CAM_CONFIG_NO_USEDK,
2609 rtlpriv->sec.key_buf[entry_id]);
2615 void rtl92ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2616 bool auto_load_fail, u8 *hwinfo)
2618 struct rtl_priv *rtlpriv = rtl_priv(hw);
2621 if (!auto_load_fail) {
2622 value = hwinfo[EEPROM_RF_BOARD_OPTION_92E];
2623 if (((value & 0xe0) >> 5) == 0x1)
2624 rtlpriv->btcoexist.btc_info.btcoexist = 1;
2626 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2628 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E;
2629 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X2;
2631 rtlpriv->btcoexist.btc_info.btcoexist = 1;
2632 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E;
2633 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X1;
2637 void rtl92ee_bt_reg_init(struct ieee80211_hw *hw)
2639 struct rtl_priv *rtlpriv = rtl_priv(hw);
2641 /* 0:Low, 1:High, 2:From Efuse. */
2642 rtlpriv->btcoexist.reg_bt_iso = 2;
2643 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2644 rtlpriv->btcoexist.reg_bt_sco = 3;
2645 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2646 rtlpriv->btcoexist.reg_bt_sco = 0;
2649 void rtl92ee_bt_hw_init(struct ieee80211_hw *hw)
2651 struct rtl_priv *rtlpriv = rtl_priv(hw);
2653 if (rtlpriv->cfg->ops->get_btc_status())
2654 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2657 void rtl92ee_suspend(struct ieee80211_hw *hw)
2661 void rtl92ee_resume(struct ieee80211_hw *hw)
2665 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
2666 void rtl92ee_allow_all_destaddr(struct ieee80211_hw *hw,
2667 bool allow_all_da, bool write_into_reg)
2669 struct rtl_priv *rtlpriv = rtl_priv(hw);
2670 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2672 if (allow_all_da) /* Set BIT0 */
2673 rtlpci->receive_config |= RCR_AAP;
2674 else /* Clear BIT0 */
2675 rtlpci->receive_config &= ~RCR_AAP;
2678 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
2680 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2681 "receive_config=0x%08X, write_into_reg=%d\n",
2682 rtlpci->receive_config, write_into_reg);