2 * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
4 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
6 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/stmmac.h>
20 #include <linux/bitops.h>
21 #include <linux/clk.h>
22 #include <linux/phy.h>
23 #include <linux/of_net.h>
24 #include <linux/gpio.h>
25 #include <linux/of_gpio.h>
26 #include <linux/of_device.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/delay.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/regmap.h>
33 struct platform_device *pdev;
35 struct regulator *regulator;
41 struct clk *clk_mac_pll;
42 struct clk *gmac_clkin;
43 struct clk *mac_clk_rx;
44 struct clk *mac_clk_tx;
45 struct clk *clk_mac_ref;
46 struct clk *clk_mac_refout;
56 #define HIWORD_UPDATE(val, mask, shift) \
57 ((val) << (shift) | (mask) << ((shift) + 16))
59 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
60 #define GRF_CLR_BIT(nr) (BIT(nr+16))
62 #define RK3288_GRF_SOC_CON1 0x0248
63 #define RK3288_GRF_SOC_CON3 0x0250
64 #define RK3288_GRF_GPIO3D_E 0x01ec
65 #define RK3288_GRF_GPIO4A_E 0x01f0
66 #define RK3288_GRF_GPIO4B_E 0x01f4
68 /*RK3288_GRF_SOC_CON1*/
69 #define GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
70 #define GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
71 #define GMAC_FLOW_CTRL GRF_BIT(9)
72 #define GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
73 #define GMAC_SPEED_10M GRF_CLR_BIT(10)
74 #define GMAC_SPEED_100M GRF_BIT(10)
75 #define GMAC_RMII_CLK_25M GRF_BIT(11)
76 #define GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
77 #define GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
78 #define GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
79 #define GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
80 #define GMAC_RMII_MODE GRF_BIT(14)
81 #define GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
83 /*RK3288_GRF_SOC_CON3*/
84 #define GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
85 #define GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
86 #define GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
87 #define GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
88 #define GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
89 #define GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
91 static void set_to_rgmii(struct rk_priv_data *bsp_priv,
92 int tx_delay, int rx_delay)
94 struct device *dev = &bsp_priv->pdev->dev;
96 if (IS_ERR(bsp_priv->grf)) {
97 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
101 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
102 GMAC_PHY_INTF_SEL_RGMII | GMAC_RMII_MODE_CLR);
103 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
104 GMAC_RXCLK_DLY_ENABLE | GMAC_TXCLK_DLY_ENABLE |
105 GMAC_CLK_RX_DL_CFG(rx_delay) |
106 GMAC_CLK_TX_DL_CFG(tx_delay));
109 static void set_to_rmii(struct rk_priv_data *bsp_priv)
111 struct device *dev = &bsp_priv->pdev->dev;
113 if (IS_ERR(bsp_priv->grf)) {
114 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
118 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
119 GMAC_PHY_INTF_SEL_RMII | GMAC_RMII_MODE);
122 static void set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
124 struct device *dev = &bsp_priv->pdev->dev;
126 if (IS_ERR(bsp_priv->grf)) {
127 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
132 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, GMAC_CLK_2_5M);
133 else if (speed == 100)
134 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, GMAC_CLK_25M);
135 else if (speed == 1000)
136 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, GMAC_CLK_125M);
138 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
141 static void set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
143 struct device *dev = &bsp_priv->pdev->dev;
145 if (IS_ERR(bsp_priv->grf)) {
146 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
151 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
152 GMAC_RMII_CLK_2_5M | GMAC_SPEED_10M);
153 } else if (speed == 100) {
154 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
155 GMAC_RMII_CLK_25M | GMAC_SPEED_100M);
157 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
161 static int gmac_clk_init(struct rk_priv_data *bsp_priv)
163 struct device *dev = &bsp_priv->pdev->dev;
165 bsp_priv->clk_enabled = false;
167 bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
168 if (IS_ERR(bsp_priv->mac_clk_rx))
169 dev_err(dev, "%s: cannot get clock %s\n",
170 __func__, "mac_clk_rx");
172 bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
173 if (IS_ERR(bsp_priv->mac_clk_tx))
174 dev_err(dev, "%s: cannot get clock %s\n",
175 __func__, "mac_clk_tx");
177 bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
178 if (IS_ERR(bsp_priv->aclk_mac))
179 dev_err(dev, "%s: cannot get clock %s\n",
180 __func__, "aclk_mac");
182 bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
183 if (IS_ERR(bsp_priv->pclk_mac))
184 dev_err(dev, "%s: cannot get clock %s\n",
185 __func__, "pclk_mac");
187 bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
188 if (IS_ERR(bsp_priv->clk_mac))
189 dev_err(dev, "%s: cannot get clock %s\n",
190 __func__, "stmmaceth");
192 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
193 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
194 if (IS_ERR(bsp_priv->clk_mac_ref))
195 dev_err(dev, "%s: cannot get clock %s\n",
196 __func__, "clk_mac_ref");
198 if (!bsp_priv->clock_input) {
199 bsp_priv->clk_mac_refout =
200 devm_clk_get(dev, "clk_mac_refout");
201 if (IS_ERR(bsp_priv->clk_mac_refout))
202 dev_err(dev, "%s: cannot get clock %s\n",
203 __func__, "clk_mac_refout");
207 if (bsp_priv->clock_input) {
208 dev_info(dev, "%s: clock input from PHY\n", __func__);
210 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
211 clk_set_rate(bsp_priv->clk_mac_pll, 50000000);
217 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
219 int phy_iface = phy_iface = bsp_priv->phy_iface;
222 if (!bsp_priv->clk_enabled) {
223 if (phy_iface == PHY_INTERFACE_MODE_RMII) {
224 if (!IS_ERR(bsp_priv->mac_clk_rx))
226 bsp_priv->mac_clk_rx);
228 if (!IS_ERR(bsp_priv->clk_mac_ref))
230 bsp_priv->clk_mac_ref);
232 if (!IS_ERR(bsp_priv->clk_mac_refout))
234 bsp_priv->clk_mac_refout);
237 if (!IS_ERR(bsp_priv->aclk_mac))
238 clk_prepare_enable(bsp_priv->aclk_mac);
240 if (!IS_ERR(bsp_priv->pclk_mac))
241 clk_prepare_enable(bsp_priv->pclk_mac);
243 if (!IS_ERR(bsp_priv->mac_clk_tx))
244 clk_prepare_enable(bsp_priv->mac_clk_tx);
247 * if (!IS_ERR(bsp_priv->clk_mac))
248 * clk_prepare_enable(bsp_priv->clk_mac);
251 bsp_priv->clk_enabled = true;
254 if (bsp_priv->clk_enabled) {
255 if (phy_iface == PHY_INTERFACE_MODE_RMII) {
256 if (!IS_ERR(bsp_priv->mac_clk_rx))
257 clk_disable_unprepare(
258 bsp_priv->mac_clk_rx);
260 if (!IS_ERR(bsp_priv->clk_mac_ref))
261 clk_disable_unprepare(
262 bsp_priv->clk_mac_ref);
264 if (!IS_ERR(bsp_priv->clk_mac_refout))
265 clk_disable_unprepare(
266 bsp_priv->clk_mac_refout);
269 if (!IS_ERR(bsp_priv->aclk_mac))
270 clk_disable_unprepare(bsp_priv->aclk_mac);
272 if (!IS_ERR(bsp_priv->pclk_mac))
273 clk_disable_unprepare(bsp_priv->pclk_mac);
275 if (!IS_ERR(bsp_priv->mac_clk_tx))
276 clk_disable_unprepare(bsp_priv->mac_clk_tx);
278 * if (!IS_ERR(bsp_priv->clk_mac))
279 * clk_disable_unprepare(bsp_priv->clk_mac);
281 bsp_priv->clk_enabled = false;
288 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
290 struct regulator *ldo = bsp_priv->regulator;
292 struct device *dev = &bsp_priv->pdev->dev;
295 dev_err(dev, "%s: no regulator found\n", __func__);
300 ret = regulator_enable(ldo);
302 dev_err(dev, "%s: fail to enable phy-supply\n",
305 ret = regulator_disable(ldo);
307 dev_err(dev, "%s: fail to disable phy-supply\n",
314 static void *rk_gmac_setup(struct platform_device *pdev)
316 struct rk_priv_data *bsp_priv;
317 struct device *dev = &pdev->dev;
319 const char *strings = NULL;
322 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
324 return ERR_PTR(-ENOMEM);
326 bsp_priv->phy_iface = of_get_phy_mode(dev->of_node);
328 bsp_priv->regulator = devm_regulator_get_optional(dev, "phy");
329 if (IS_ERR(bsp_priv->regulator)) {
330 if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) {
331 dev_err(dev, "phy regulator is not available yet, deferred probing\n");
332 return ERR_PTR(-EPROBE_DEFER);
334 dev_err(dev, "no regulator found\n");
335 bsp_priv->regulator = NULL;
338 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
340 dev_err(dev, "%s: Can not read property: clock_in_out.\n",
342 bsp_priv->clock_input = true;
344 dev_info(dev, "%s: clock input or output? (%s).\n",
346 if (!strcmp(strings, "input"))
347 bsp_priv->clock_input = true;
349 bsp_priv->clock_input = false;
352 ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
354 bsp_priv->tx_delay = 0x30;
355 dev_err(dev, "%s: Can not read property: tx_delay.", __func__);
356 dev_err(dev, "%s: set tx_delay to 0x%x\n",
357 __func__, bsp_priv->tx_delay);
359 dev_info(dev, "%s: TX delay(0x%x).\n", __func__, value);
360 bsp_priv->tx_delay = value;
363 ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
365 bsp_priv->rx_delay = 0x10;
366 dev_err(dev, "%s: Can not read property: rx_delay.", __func__);
367 dev_err(dev, "%s: set rx_delay to 0x%x\n",
368 __func__, bsp_priv->rx_delay);
370 dev_info(dev, "%s: RX delay(0x%x).\n", __func__, value);
371 bsp_priv->rx_delay = value;
374 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
376 bsp_priv->pdev = pdev;
379 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) {
380 dev_info(dev, "%s: init for RGMII\n", __func__);
381 set_to_rgmii(bsp_priv, bsp_priv->tx_delay, bsp_priv->rx_delay);
382 } else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
383 dev_info(dev, "%s: init for RMII\n", __func__);
384 set_to_rmii(bsp_priv);
386 dev_err(dev, "%s: NO interface defined!\n", __func__);
389 gmac_clk_init(bsp_priv);
394 static int rk_gmac_init(struct platform_device *pdev, void *priv)
396 struct rk_priv_data *bsp_priv = priv;
399 ret = phy_power_on(bsp_priv, true);
403 ret = gmac_clk_enable(bsp_priv, true);
410 static void rk_gmac_exit(struct platform_device *pdev, void *priv)
412 struct rk_priv_data *gmac = priv;
414 phy_power_on(gmac, false);
415 gmac_clk_enable(gmac, false);
418 static void rk_fix_speed(void *priv, unsigned int speed)
420 struct rk_priv_data *bsp_priv = priv;
421 struct device *dev = &bsp_priv->pdev->dev;
423 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII)
424 set_rgmii_speed(bsp_priv, speed);
425 else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
426 set_rmii_speed(bsp_priv, speed);
428 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
431 const struct stmmac_of_data rk3288_gmac_data = {
433 .fix_mac_speed = rk_fix_speed,
434 .setup = rk_gmac_setup,
435 .init = rk_gmac_init,
436 .exit = rk_gmac_exit,