1 /* Renesas Ethernet AVB device driver
3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015 Cogent Embedded, Inc. <source@cogentembedded.com>
7 * Based on the SuperH Ethernet driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
14 #include <linux/cache.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/net_tstamp.h>
27 #include <linux/of_device.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_mdio.h>
30 #include <linux/of_net.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
37 #define RAVB_DEF_MSG_ENABLE \
43 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
47 for (i = 0; i < 10000; i++) {
48 if ((ravb_read(ndev, reg) & mask) == value)
55 static int ravb_config(struct net_device *ndev)
60 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG,
62 /* Check if the operating mode is changed to the config mode */
63 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
65 netdev_err(ndev, "failed to switch device to config mode\n");
70 static void ravb_set_duplex(struct net_device *ndev)
72 struct ravb_private *priv = netdev_priv(ndev);
73 u32 ecmr = ravb_read(ndev, ECMR);
75 if (priv->duplex) /* Full */
79 ravb_write(ndev, ecmr, ECMR);
82 static void ravb_set_rate(struct net_device *ndev)
84 struct ravb_private *priv = netdev_priv(ndev);
86 switch (priv->speed) {
87 case 100: /* 100BASE */
88 ravb_write(ndev, GECMR_SPEED_100, GECMR);
90 case 1000: /* 1000BASE */
91 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
98 static void ravb_set_buffer_align(struct sk_buff *skb)
100 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
103 skb_reserve(skb, RAVB_ALIGN - reserve);
106 /* Get MAC address from the MAC address registers
108 * Ethernet AVB device doesn't have ROM for MAC address.
109 * This function gets the MAC address that was used by a bootloader.
111 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
114 ether_addr_copy(ndev->dev_addr, mac);
116 ndev->dev_addr[0] = (ravb_read(ndev, MAHR) >> 24);
117 ndev->dev_addr[1] = (ravb_read(ndev, MAHR) >> 16) & 0xFF;
118 ndev->dev_addr[2] = (ravb_read(ndev, MAHR) >> 8) & 0xFF;
119 ndev->dev_addr[3] = (ravb_read(ndev, MAHR) >> 0) & 0xFF;
120 ndev->dev_addr[4] = (ravb_read(ndev, MALR) >> 8) & 0xFF;
121 ndev->dev_addr[5] = (ravb_read(ndev, MALR) >> 0) & 0xFF;
125 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
127 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
129 u32 pir = ravb_read(priv->ndev, PIR);
135 ravb_write(priv->ndev, pir, PIR);
138 /* MDC pin control */
139 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
141 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
144 /* Data I/O pin control */
145 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
147 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
151 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
153 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
157 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
159 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
162 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
165 /* MDIO bus control struct */
166 static struct mdiobb_ops bb_ops = {
167 .owner = THIS_MODULE,
168 .set_mdc = ravb_set_mdc,
169 .set_mdio_dir = ravb_set_mdio_dir,
170 .set_mdio_data = ravb_set_mdio_data,
171 .get_mdio_data = ravb_get_mdio_data,
174 /* Free skb's and DMA buffers for Ethernet AVB */
175 static void ravb_ring_free(struct net_device *ndev, int q)
177 struct ravb_private *priv = netdev_priv(ndev);
181 /* Free RX skb ringbuffer */
182 if (priv->rx_skb[q]) {
183 for (i = 0; i < priv->num_rx_ring[q]; i++)
184 dev_kfree_skb(priv->rx_skb[q][i]);
186 kfree(priv->rx_skb[q]);
187 priv->rx_skb[q] = NULL;
189 /* Free TX skb ringbuffer */
190 if (priv->tx_skb[q]) {
191 for (i = 0; i < priv->num_tx_ring[q]; i++)
192 dev_kfree_skb(priv->tx_skb[q][i]);
194 kfree(priv->tx_skb[q]);
195 priv->tx_skb[q] = NULL;
197 /* Free aligned TX buffers */
198 kfree(priv->tx_align[q]);
199 priv->tx_align[q] = NULL;
201 if (priv->rx_ring[q]) {
202 ring_size = sizeof(struct ravb_ex_rx_desc) *
203 (priv->num_rx_ring[q] + 1);
204 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
205 priv->rx_desc_dma[q]);
206 priv->rx_ring[q] = NULL;
209 if (priv->tx_ring[q]) {
210 ring_size = sizeof(struct ravb_tx_desc) *
211 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
212 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
213 priv->tx_desc_dma[q]);
214 priv->tx_ring[q] = NULL;
218 /* Format skb and descriptor buffer for Ethernet AVB */
219 static void ravb_ring_format(struct net_device *ndev, int q)
221 struct ravb_private *priv = netdev_priv(ndev);
222 struct ravb_ex_rx_desc *rx_desc;
223 struct ravb_tx_desc *tx_desc;
224 struct ravb_desc *desc;
225 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
226 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
233 priv->dirty_rx[q] = 0;
234 priv->dirty_tx[q] = 0;
236 memset(priv->rx_ring[q], 0, rx_ring_size);
237 /* Build RX ring buffer */
238 for (i = 0; i < priv->num_rx_ring[q]; i++) {
240 rx_desc = &priv->rx_ring[q][i];
241 /* The size of the buffer should be on 16-byte boundary. */
242 rx_desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
243 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
244 ALIGN(PKT_BUF_SZ, 16),
246 /* We just set the data size to 0 for a failed mapping which
247 * should prevent DMA from happening...
249 if (dma_mapping_error(ndev->dev.parent, dma_addr))
250 rx_desc->ds_cc = cpu_to_le16(0);
251 rx_desc->dptr = cpu_to_le32(dma_addr);
252 rx_desc->die_dt = DT_FEMPTY;
254 rx_desc = &priv->rx_ring[q][i];
255 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
256 rx_desc->die_dt = DT_LINKFIX; /* type */
258 memset(priv->tx_ring[q], 0, tx_ring_size);
259 /* Build TX ring buffer */
260 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
262 tx_desc->die_dt = DT_EEMPTY;
264 tx_desc->die_dt = DT_EEMPTY;
266 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
267 tx_desc->die_dt = DT_LINKFIX; /* type */
269 /* RX descriptor base address for best effort */
270 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
271 desc->die_dt = DT_LINKFIX; /* type */
272 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
274 /* TX descriptor base address for best effort */
275 desc = &priv->desc_bat[q];
276 desc->die_dt = DT_LINKFIX; /* type */
277 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
280 /* Init skb and descriptor buffer for Ethernet AVB */
281 static int ravb_ring_init(struct net_device *ndev, int q)
283 struct ravb_private *priv = netdev_priv(ndev);
288 /* Allocate RX and TX skb rings */
289 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
290 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
291 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
292 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
293 if (!priv->rx_skb[q] || !priv->tx_skb[q])
296 for (i = 0; i < priv->num_rx_ring[q]; i++) {
297 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
300 ravb_set_buffer_align(skb);
301 priv->rx_skb[q][i] = skb;
304 /* Allocate rings for the aligned buffers */
305 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
306 DPTR_ALIGN - 1, GFP_KERNEL);
307 if (!priv->tx_align[q])
310 /* Allocate all RX descriptors. */
311 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
312 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
313 &priv->rx_desc_dma[q],
315 if (!priv->rx_ring[q])
318 priv->dirty_rx[q] = 0;
320 /* Allocate all TX descriptors. */
321 ring_size = sizeof(struct ravb_tx_desc) *
322 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
323 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
324 &priv->tx_desc_dma[q],
326 if (!priv->tx_ring[q])
332 ravb_ring_free(ndev, q);
337 /* E-MAC init function */
338 static void ravb_emac_init(struct net_device *ndev)
340 struct ravb_private *priv = netdev_priv(ndev);
343 /* Receive frame limit set register */
344 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
346 /* PAUSE prohibition */
347 ecmr = ravb_read(ndev, ECMR);
349 ecmr |= ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
350 ravb_write(ndev, ecmr, ECMR);
354 /* Set MAC address */
356 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
357 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
359 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
361 ravb_write(ndev, 1, MPR);
363 /* E-MAC status register clear */
364 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
366 /* E-MAC interrupt enable register */
367 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
370 /* Device init function for Ethernet AVB */
371 static int ravb_dmac_init(struct net_device *ndev)
375 /* Set CONFIG mode */
376 error = ravb_config(ndev);
380 error = ravb_ring_init(ndev, RAVB_BE);
383 error = ravb_ring_init(ndev, RAVB_NC);
385 ravb_ring_free(ndev, RAVB_BE);
389 /* Descriptor format */
390 ravb_ring_format(ndev, RAVB_BE);
391 ravb_ring_format(ndev, RAVB_NC);
393 #if defined(__LITTLE_ENDIAN)
394 ravb_write(ndev, ravb_read(ndev, CCC) & ~CCC_BOC, CCC);
396 ravb_write(ndev, ravb_read(ndev, CCC) | CCC_BOC, CCC);
400 ravb_write(ndev, RCR_EFFS | RCR_ENCF | RCR_ETS0 | 0x18000000, RCR);
403 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
405 /* Timestamp enable */
406 ravb_write(ndev, TCCR_TFEN, TCCR);
408 /* Interrupt enable: */
410 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
411 /* Receive FIFO full error, descriptor empty */
412 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
413 /* Frame transmitted, timestamp FIFO updated */
414 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
416 /* Setting the control will start the AVB-DMAC process. */
417 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_OPERATION,
423 /* Free TX skb function for AVB-IP */
424 static int ravb_tx_free(struct net_device *ndev, int q)
426 struct ravb_private *priv = netdev_priv(ndev);
427 struct net_device_stats *stats = &priv->stats[q];
428 struct ravb_tx_desc *desc;
433 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
434 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
436 desc = &priv->tx_ring[q][entry];
437 if (desc->die_dt != DT_FEMPTY)
439 /* Descriptor type must be checked before all other reads */
441 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
442 /* Free the original skb. */
443 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
444 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
445 size, DMA_TO_DEVICE);
446 /* Last packet descriptor? */
447 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
448 entry /= NUM_TX_DESC;
449 dev_kfree_skb_any(priv->tx_skb[q][entry]);
450 priv->tx_skb[q][entry] = NULL;
455 stats->tx_bytes += size;
456 desc->die_dt = DT_EEMPTY;
461 static void ravb_get_tx_tstamp(struct net_device *ndev)
463 struct ravb_private *priv = netdev_priv(ndev);
464 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
465 struct skb_shared_hwtstamps shhwtstamps;
467 struct timespec64 ts;
472 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
474 tfa2 = ravb_read(ndev, TFA2);
475 tfa_tag = (tfa2 & TFA2_TST) >> 16;
476 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
477 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
478 ravb_read(ndev, TFA1);
479 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
480 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
481 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
485 list_del(&ts_skb->list);
487 if (tag == tfa_tag) {
488 skb_tstamp_tx(skb, &shhwtstamps);
492 ravb_write(ndev, ravb_read(ndev, TCCR) | TCCR_TFR, TCCR);
496 /* Packet receive function for Ethernet AVB */
497 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
499 struct ravb_private *priv = netdev_priv(ndev);
500 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
501 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
503 struct net_device_stats *stats = &priv->stats[q];
504 struct ravb_ex_rx_desc *desc;
507 struct timespec64 ts;
512 boguscnt = min(boguscnt, *quota);
514 desc = &priv->rx_ring[q][entry];
515 while (desc->die_dt != DT_FEMPTY) {
516 /* Descriptor type must be checked before all other reads */
518 desc_status = desc->msc;
519 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
524 /* We use 0-byte descriptors to mark the DMA mapping errors */
528 if (desc_status & MSC_MC)
531 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
534 if (desc_status & MSC_CRC)
535 stats->rx_crc_errors++;
536 if (desc_status & MSC_RFE)
537 stats->rx_frame_errors++;
538 if (desc_status & (MSC_RTLF | MSC_RTSF))
539 stats->rx_length_errors++;
540 if (desc_status & MSC_CEEF)
541 stats->rx_missed_errors++;
543 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
545 skb = priv->rx_skb[q][entry];
546 priv->rx_skb[q][entry] = NULL;
547 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
548 ALIGN(PKT_BUF_SZ, 16),
550 get_ts &= (q == RAVB_NC) ?
551 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
552 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
554 struct skb_shared_hwtstamps *shhwtstamps;
556 shhwtstamps = skb_hwtstamps(skb);
557 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
558 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
559 32) | le32_to_cpu(desc->ts_sl);
560 ts.tv_nsec = le32_to_cpu(desc->ts_n);
561 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
563 skb_put(skb, pkt_len);
564 skb->protocol = eth_type_trans(skb, ndev);
565 napi_gro_receive(&priv->napi[q], skb);
567 stats->rx_bytes += pkt_len;
570 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
571 desc = &priv->rx_ring[q][entry];
574 /* Refill the RX ring buffers. */
575 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
576 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
577 desc = &priv->rx_ring[q][entry];
578 /* The size of the buffer should be on 16-byte boundary. */
579 desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
581 if (!priv->rx_skb[q][entry]) {
582 skb = netdev_alloc_skb(ndev,
583 PKT_BUF_SZ + RAVB_ALIGN - 1);
585 break; /* Better luck next round. */
586 ravb_set_buffer_align(skb);
587 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
588 le16_to_cpu(desc->ds_cc),
590 skb_checksum_none_assert(skb);
591 /* We just set the data size to 0 for a failed mapping
592 * which should prevent DMA from happening...
594 if (dma_mapping_error(ndev->dev.parent, dma_addr))
595 desc->ds_cc = cpu_to_le16(0);
596 desc->dptr = cpu_to_le32(dma_addr);
597 priv->rx_skb[q][entry] = skb;
599 /* Descriptor type must be set after all the above writes */
601 desc->die_dt = DT_FEMPTY;
604 *quota -= limit - (++boguscnt);
606 return boguscnt <= 0;
609 static void ravb_rcv_snd_disable(struct net_device *ndev)
611 /* Disable TX and RX */
612 ravb_write(ndev, ravb_read(ndev, ECMR) & ~(ECMR_RE | ECMR_TE), ECMR);
615 static void ravb_rcv_snd_enable(struct net_device *ndev)
617 /* Enable TX and RX */
618 ravb_write(ndev, ravb_read(ndev, ECMR) | ECMR_RE | ECMR_TE, ECMR);
621 /* function for waiting dma process finished */
622 static int ravb_stop_dma(struct net_device *ndev)
626 /* Wait for stopping the hardware TX process */
627 error = ravb_wait(ndev, TCCR,
628 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
632 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
637 /* Stop the E-MAC's RX/TX processes. */
638 ravb_rcv_snd_disable(ndev);
640 /* Wait for stopping the RX DMA process */
641 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
645 /* Stop AVB-DMAC process */
646 return ravb_config(ndev);
649 /* E-MAC interrupt handler */
650 static void ravb_emac_interrupt(struct net_device *ndev)
652 struct ravb_private *priv = netdev_priv(ndev);
655 ecsr = ravb_read(ndev, ECSR);
656 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
658 ndev->stats.tx_carrier_errors++;
659 if (ecsr & ECSR_LCHNG) {
661 if (priv->no_avb_link)
663 psr = ravb_read(ndev, PSR);
664 if (priv->avb_link_active_low)
666 if (!(psr & PSR_LMON)) {
667 /* DIsable RX and TX */
668 ravb_rcv_snd_disable(ndev);
670 /* Enable RX and TX */
671 ravb_rcv_snd_enable(ndev);
676 /* Error interrupt handler */
677 static void ravb_error_interrupt(struct net_device *ndev)
679 struct ravb_private *priv = netdev_priv(ndev);
682 eis = ravb_read(ndev, EIS);
683 ravb_write(ndev, ~EIS_QFS, EIS);
685 ris2 = ravb_read(ndev, RIS2);
686 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
688 /* Receive Descriptor Empty int */
689 if (ris2 & RIS2_QFF0)
690 priv->stats[RAVB_BE].rx_over_errors++;
692 /* Receive Descriptor Empty int */
693 if (ris2 & RIS2_QFF1)
694 priv->stats[RAVB_NC].rx_over_errors++;
696 /* Receive FIFO Overflow int */
697 if (ris2 & RIS2_RFFF)
698 priv->rx_fifo_errors++;
702 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
704 struct net_device *ndev = dev_id;
705 struct ravb_private *priv = netdev_priv(ndev);
706 irqreturn_t result = IRQ_NONE;
709 spin_lock(&priv->lock);
710 /* Get interrupt status */
711 iss = ravb_read(ndev, ISS);
713 /* Received and transmitted interrupts */
714 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
715 u32 ris0 = ravb_read(ndev, RIS0);
716 u32 ric0 = ravb_read(ndev, RIC0);
717 u32 tis = ravb_read(ndev, TIS);
718 u32 tic = ravb_read(ndev, TIC);
721 /* Timestamp updated */
722 if (tis & TIS_TFUF) {
723 ravb_write(ndev, ~TIS_TFUF, TIS);
724 ravb_get_tx_tstamp(ndev);
725 result = IRQ_HANDLED;
728 /* Network control and best effort queue RX/TX */
729 for (q = RAVB_NC; q >= RAVB_BE; q--) {
730 if (((ris0 & ric0) & BIT(q)) ||
731 ((tis & tic) & BIT(q))) {
732 if (napi_schedule_prep(&priv->napi[q])) {
733 /* Mask RX and TX interrupts */
736 ravb_write(ndev, ric0, RIC0);
737 ravb_write(ndev, tic, TIC);
738 __napi_schedule(&priv->napi[q]);
741 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
744 " tx status 0x%08x, tx mask 0x%08x.\n",
747 result = IRQ_HANDLED;
752 /* E-MAC status summary */
754 ravb_emac_interrupt(ndev);
755 result = IRQ_HANDLED;
758 /* Error status summary */
760 ravb_error_interrupt(ndev);
761 result = IRQ_HANDLED;
765 result = ravb_ptp_interrupt(ndev);
768 spin_unlock(&priv->lock);
772 static int ravb_poll(struct napi_struct *napi, int budget)
774 struct net_device *ndev = napi->dev;
775 struct ravb_private *priv = netdev_priv(ndev);
777 int q = napi - priv->napi;
783 tis = ravb_read(ndev, TIS);
784 ris0 = ravb_read(ndev, RIS0);
785 if (!((ris0 & mask) || (tis & mask)))
788 /* Processing RX Descriptor Ring */
790 /* Clear RX interrupt */
791 ravb_write(ndev, ~mask, RIS0);
792 if (ravb_rx(ndev, "a, q))
795 /* Processing TX Descriptor Ring */
797 spin_lock_irqsave(&priv->lock, flags);
798 /* Clear TX interrupt */
799 ravb_write(ndev, ~mask, TIS);
800 ravb_tx_free(ndev, q);
801 netif_wake_subqueue(ndev, q);
803 spin_unlock_irqrestore(&priv->lock, flags);
809 /* Re-enable RX/TX interrupts */
810 spin_lock_irqsave(&priv->lock, flags);
811 ravb_write(ndev, ravb_read(ndev, RIC0) | mask, RIC0);
812 ravb_write(ndev, ravb_read(ndev, TIC) | mask, TIC);
814 spin_unlock_irqrestore(&priv->lock, flags);
816 /* Receive error message handling */
817 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
818 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
819 if (priv->rx_over_errors != ndev->stats.rx_over_errors) {
820 ndev->stats.rx_over_errors = priv->rx_over_errors;
821 netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n");
823 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) {
824 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
825 netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n");
828 return budget - quota;
831 /* PHY state control function */
832 static void ravb_adjust_link(struct net_device *ndev)
834 struct ravb_private *priv = netdev_priv(ndev);
835 struct phy_device *phydev = priv->phydev;
836 bool new_state = false;
839 if (phydev->duplex != priv->duplex) {
841 priv->duplex = phydev->duplex;
842 ravb_set_duplex(ndev);
845 if (phydev->speed != priv->speed) {
847 priv->speed = phydev->speed;
851 ravb_write(ndev, ravb_read(ndev, ECMR) & ~ECMR_TXF,
854 priv->link = phydev->link;
855 if (priv->no_avb_link)
856 ravb_rcv_snd_enable(ndev);
858 } else if (priv->link) {
863 if (priv->no_avb_link)
864 ravb_rcv_snd_disable(ndev);
867 if (new_state && netif_msg_link(priv))
868 phy_print_status(phydev);
871 /* PHY init function */
872 static int ravb_phy_init(struct net_device *ndev)
874 struct device_node *np = ndev->dev.parent->of_node;
875 struct ravb_private *priv = netdev_priv(ndev);
876 struct phy_device *phydev;
877 struct device_node *pn;
883 /* Try connecting to PHY */
884 pn = of_parse_phandle(np, "phy-handle", 0);
885 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
886 priv->phy_interface);
888 netdev_err(ndev, "failed to connect PHY\n");
892 /* This driver only support 10/100Mbit speeds on Gen3
895 if (priv->chip_id == RCAR_GEN3) {
898 err = phy_set_max_speed(phydev, SPEED_100);
900 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
901 phy_disconnect(phydev);
905 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
908 /* 10BASE is not supported */
909 phydev->supported &= ~PHY_10BT_FEATURES;
911 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
912 phydev->addr, phydev->irq, phydev->drv->name);
914 priv->phydev = phydev;
919 /* PHY control start function */
920 static int ravb_phy_start(struct net_device *ndev)
922 struct ravb_private *priv = netdev_priv(ndev);
925 error = ravb_phy_init(ndev);
929 phy_start(priv->phydev);
934 static int ravb_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
936 struct ravb_private *priv = netdev_priv(ndev);
941 spin_lock_irqsave(&priv->lock, flags);
942 error = phy_ethtool_gset(priv->phydev, ecmd);
943 spin_unlock_irqrestore(&priv->lock, flags);
949 static int ravb_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
951 struct ravb_private *priv = netdev_priv(ndev);
958 spin_lock_irqsave(&priv->lock, flags);
960 /* Disable TX and RX */
961 ravb_rcv_snd_disable(ndev);
963 error = phy_ethtool_sset(priv->phydev, ecmd);
967 if (ecmd->duplex == DUPLEX_FULL)
972 ravb_set_duplex(ndev);
977 /* Enable TX and RX */
978 ravb_rcv_snd_enable(ndev);
981 spin_unlock_irqrestore(&priv->lock, flags);
986 static int ravb_nway_reset(struct net_device *ndev)
988 struct ravb_private *priv = netdev_priv(ndev);
993 spin_lock_irqsave(&priv->lock, flags);
994 error = phy_start_aneg(priv->phydev);
995 spin_unlock_irqrestore(&priv->lock, flags);
1001 static u32 ravb_get_msglevel(struct net_device *ndev)
1003 struct ravb_private *priv = netdev_priv(ndev);
1005 return priv->msg_enable;
1008 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1010 struct ravb_private *priv = netdev_priv(ndev);
1012 priv->msg_enable = value;
1015 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1016 "rx_queue_0_current",
1017 "tx_queue_0_current",
1020 "rx_queue_0_packets",
1021 "tx_queue_0_packets",
1024 "rx_queue_0_mcast_packets",
1025 "rx_queue_0_errors",
1026 "rx_queue_0_crc_errors",
1027 "rx_queue_0_frame_errors",
1028 "rx_queue_0_length_errors",
1029 "rx_queue_0_missed_errors",
1030 "rx_queue_0_over_errors",
1032 "rx_queue_1_current",
1033 "tx_queue_1_current",
1036 "rx_queue_1_packets",
1037 "tx_queue_1_packets",
1040 "rx_queue_1_mcast_packets",
1041 "rx_queue_1_errors",
1042 "rx_queue_1_crc_errors",
1043 "rx_queue_1_frame_errors",
1044 "rx_queue_1_length_errors",
1045 "rx_queue_1_missed_errors",
1046 "rx_queue_1_over_errors",
1049 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1051 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1055 return RAVB_STATS_LEN;
1061 static void ravb_get_ethtool_stats(struct net_device *ndev,
1062 struct ethtool_stats *stats, u64 *data)
1064 struct ravb_private *priv = netdev_priv(ndev);
1068 /* Device-specific stats */
1069 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1070 struct net_device_stats *stats = &priv->stats[q];
1072 data[i++] = priv->cur_rx[q];
1073 data[i++] = priv->cur_tx[q];
1074 data[i++] = priv->dirty_rx[q];
1075 data[i++] = priv->dirty_tx[q];
1076 data[i++] = stats->rx_packets;
1077 data[i++] = stats->tx_packets;
1078 data[i++] = stats->rx_bytes;
1079 data[i++] = stats->tx_bytes;
1080 data[i++] = stats->multicast;
1081 data[i++] = stats->rx_errors;
1082 data[i++] = stats->rx_crc_errors;
1083 data[i++] = stats->rx_frame_errors;
1084 data[i++] = stats->rx_length_errors;
1085 data[i++] = stats->rx_missed_errors;
1086 data[i++] = stats->rx_over_errors;
1090 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1092 switch (stringset) {
1094 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1099 static void ravb_get_ringparam(struct net_device *ndev,
1100 struct ethtool_ringparam *ring)
1102 struct ravb_private *priv = netdev_priv(ndev);
1104 ring->rx_max_pending = BE_RX_RING_MAX;
1105 ring->tx_max_pending = BE_TX_RING_MAX;
1106 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1107 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1110 static int ravb_set_ringparam(struct net_device *ndev,
1111 struct ethtool_ringparam *ring)
1113 struct ravb_private *priv = netdev_priv(ndev);
1116 if (ring->tx_pending > BE_TX_RING_MAX ||
1117 ring->rx_pending > BE_RX_RING_MAX ||
1118 ring->tx_pending < BE_TX_RING_MIN ||
1119 ring->rx_pending < BE_RX_RING_MIN)
1121 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1124 if (netif_running(ndev)) {
1125 netif_device_detach(ndev);
1126 /* Stop PTP Clock driver */
1127 ravb_ptp_stop(ndev);
1128 /* Wait for DMA stopping */
1129 error = ravb_stop_dma(ndev);
1132 "cannot set ringparam! Any AVB processes are still running?\n");
1135 synchronize_irq(ndev->irq);
1137 /* Free all the skb's in the RX queue and the DMA buffers. */
1138 ravb_ring_free(ndev, RAVB_BE);
1139 ravb_ring_free(ndev, RAVB_NC);
1142 /* Set new parameters */
1143 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1144 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1146 if (netif_running(ndev)) {
1147 error = ravb_dmac_init(ndev);
1150 "%s: ravb_dmac_init() failed, error %d\n",
1155 ravb_emac_init(ndev);
1157 /* Initialise PTP Clock driver */
1158 ravb_ptp_init(ndev, priv->pdev);
1160 netif_device_attach(ndev);
1166 static int ravb_get_ts_info(struct net_device *ndev,
1167 struct ethtool_ts_info *info)
1169 struct ravb_private *priv = netdev_priv(ndev);
1171 info->so_timestamping =
1172 SOF_TIMESTAMPING_TX_SOFTWARE |
1173 SOF_TIMESTAMPING_RX_SOFTWARE |
1174 SOF_TIMESTAMPING_SOFTWARE |
1175 SOF_TIMESTAMPING_TX_HARDWARE |
1176 SOF_TIMESTAMPING_RX_HARDWARE |
1177 SOF_TIMESTAMPING_RAW_HARDWARE;
1178 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1180 (1 << HWTSTAMP_FILTER_NONE) |
1181 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1182 (1 << HWTSTAMP_FILTER_ALL);
1183 info->phc_index = ptp_clock_index(priv->ptp.clock);
1188 static const struct ethtool_ops ravb_ethtool_ops = {
1189 .get_settings = ravb_get_settings,
1190 .set_settings = ravb_set_settings,
1191 .nway_reset = ravb_nway_reset,
1192 .get_msglevel = ravb_get_msglevel,
1193 .set_msglevel = ravb_set_msglevel,
1194 .get_link = ethtool_op_get_link,
1195 .get_strings = ravb_get_strings,
1196 .get_ethtool_stats = ravb_get_ethtool_stats,
1197 .get_sset_count = ravb_get_sset_count,
1198 .get_ringparam = ravb_get_ringparam,
1199 .set_ringparam = ravb_set_ringparam,
1200 .get_ts_info = ravb_get_ts_info,
1203 /* Network device open function for Ethernet AVB */
1204 static int ravb_open(struct net_device *ndev)
1206 struct ravb_private *priv = netdev_priv(ndev);
1209 napi_enable(&priv->napi[RAVB_BE]);
1210 napi_enable(&priv->napi[RAVB_NC]);
1212 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, ndev->name,
1215 netdev_err(ndev, "cannot request IRQ\n");
1219 if (priv->chip_id == RCAR_GEN3) {
1220 error = request_irq(priv->emac_irq, ravb_interrupt,
1221 IRQF_SHARED, ndev->name, ndev);
1223 netdev_err(ndev, "cannot request IRQ\n");
1229 error = ravb_dmac_init(ndev);
1232 ravb_emac_init(ndev);
1234 /* Initialise PTP Clock driver */
1235 ravb_ptp_init(ndev, priv->pdev);
1237 netif_tx_start_all_queues(ndev);
1239 /* PHY control start */
1240 error = ravb_phy_start(ndev);
1247 /* Stop PTP Clock driver */
1248 ravb_ptp_stop(ndev);
1250 if (priv->chip_id == RCAR_GEN3)
1251 free_irq(priv->emac_irq, ndev);
1253 free_irq(ndev->irq, ndev);
1255 napi_disable(&priv->napi[RAVB_NC]);
1256 napi_disable(&priv->napi[RAVB_BE]);
1260 /* Timeout function for Ethernet AVB */
1261 static void ravb_tx_timeout(struct net_device *ndev)
1263 struct ravb_private *priv = netdev_priv(ndev);
1265 netif_err(priv, tx_err, ndev,
1266 "transmit timed out, status %08x, resetting...\n",
1267 ravb_read(ndev, ISS));
1269 /* tx_errors count up */
1270 ndev->stats.tx_errors++;
1272 schedule_work(&priv->work);
1275 static void ravb_tx_timeout_work(struct work_struct *work)
1277 struct ravb_private *priv = container_of(work, struct ravb_private,
1279 struct net_device *ndev = priv->ndev;
1281 netif_tx_stop_all_queues(ndev);
1283 /* Stop PTP Clock driver */
1284 ravb_ptp_stop(ndev);
1286 /* Wait for DMA stopping */
1287 ravb_stop_dma(ndev);
1289 ravb_ring_free(ndev, RAVB_BE);
1290 ravb_ring_free(ndev, RAVB_NC);
1293 ravb_dmac_init(ndev);
1294 ravb_emac_init(ndev);
1296 /* Initialise PTP Clock driver */
1297 ravb_ptp_init(ndev, priv->pdev);
1299 netif_tx_start_all_queues(ndev);
1302 /* Packet transmit function for Ethernet AVB */
1303 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1305 struct ravb_private *priv = netdev_priv(ndev);
1306 u16 q = skb_get_queue_mapping(skb);
1307 struct ravb_tstamp_skb *ts_skb;
1308 struct ravb_tx_desc *desc;
1309 unsigned long flags;
1315 spin_lock_irqsave(&priv->lock, flags);
1316 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1318 netif_err(priv, tx_queued, ndev,
1319 "still transmitting with the full ring!\n");
1320 netif_stop_subqueue(ndev, q);
1321 spin_unlock_irqrestore(&priv->lock, flags);
1322 return NETDEV_TX_BUSY;
1324 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1325 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
1327 if (skb_put_padto(skb, ETH_ZLEN))
1330 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1331 entry / NUM_TX_DESC * DPTR_ALIGN;
1332 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1333 /* Zero length DMA descriptors are problematic as they seem to
1334 * terminate DMA transfers. Avoid them by simply using a length of
1335 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN.
1337 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of
1338 * data by the call to skb_put_padto() above this is safe with
1339 * respect to both the length of the first DMA descriptor (len)
1340 * overflowing the available data and the length of the second DMA
1341 * descriptor (skb->len - len) being negative.
1346 memcpy(buffer, skb->data, len);
1347 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1348 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1351 desc = &priv->tx_ring[q][entry];
1352 desc->ds_tagl = cpu_to_le16(len);
1353 desc->dptr = cpu_to_le32(dma_addr);
1355 buffer = skb->data + len;
1356 len = skb->len - len;
1357 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1358 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1362 desc->ds_tagl = cpu_to_le16(len);
1363 desc->dptr = cpu_to_le32(dma_addr);
1365 /* TX timestamp required */
1367 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1370 dma_unmap_single(ndev->dev.parent, dma_addr, len,
1375 ts_skb->tag = priv->ts_skb_tag++;
1376 priv->ts_skb_tag &= 0x3ff;
1377 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1379 /* TAG and timestamp required flag */
1380 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1381 skb_tx_timestamp(skb);
1382 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1383 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1386 /* Descriptor type must be set after all the above writes */
1388 desc->die_dt = DT_FEND;
1390 desc->die_dt = DT_FSTART;
1392 ravb_write(ndev, ravb_read(ndev, TCCR) | (TCCR_TSRQ0 << q), TCCR);
1394 priv->cur_tx[q] += NUM_TX_DESC;
1395 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1396 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && !ravb_tx_free(ndev, q))
1397 netif_stop_subqueue(ndev, q);
1401 spin_unlock_irqrestore(&priv->lock, flags);
1402 return NETDEV_TX_OK;
1405 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1406 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1408 dev_kfree_skb_any(skb);
1409 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
1413 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1414 void *accel_priv, select_queue_fallback_t fallback)
1416 /* If skb needs TX timestamp, it is handled in network control queue */
1417 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1422 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1424 struct ravb_private *priv = netdev_priv(ndev);
1425 struct net_device_stats *nstats, *stats0, *stats1;
1427 nstats = &ndev->stats;
1428 stats0 = &priv->stats[RAVB_BE];
1429 stats1 = &priv->stats[RAVB_NC];
1431 nstats->tx_dropped += ravb_read(ndev, TROCR);
1432 ravb_write(ndev, 0, TROCR); /* (write clear) */
1433 nstats->collisions += ravb_read(ndev, CDCR);
1434 ravb_write(ndev, 0, CDCR); /* (write clear) */
1435 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1436 ravb_write(ndev, 0, LCCR); /* (write clear) */
1438 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1439 ravb_write(ndev, 0, CERCR); /* (write clear) */
1440 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1441 ravb_write(ndev, 0, CEECR); /* (write clear) */
1443 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1444 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1445 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1446 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1447 nstats->multicast = stats0->multicast + stats1->multicast;
1448 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1449 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1450 nstats->rx_frame_errors =
1451 stats0->rx_frame_errors + stats1->rx_frame_errors;
1452 nstats->rx_length_errors =
1453 stats0->rx_length_errors + stats1->rx_length_errors;
1454 nstats->rx_missed_errors =
1455 stats0->rx_missed_errors + stats1->rx_missed_errors;
1456 nstats->rx_over_errors =
1457 stats0->rx_over_errors + stats1->rx_over_errors;
1462 /* Update promiscuous bit */
1463 static void ravb_set_rx_mode(struct net_device *ndev)
1465 struct ravb_private *priv = netdev_priv(ndev);
1466 unsigned long flags;
1469 spin_lock_irqsave(&priv->lock, flags);
1470 ecmr = ravb_read(ndev, ECMR);
1471 if (ndev->flags & IFF_PROMISC)
1475 ravb_write(ndev, ecmr, ECMR);
1477 spin_unlock_irqrestore(&priv->lock, flags);
1480 /* Device close function for Ethernet AVB */
1481 static int ravb_close(struct net_device *ndev)
1483 struct ravb_private *priv = netdev_priv(ndev);
1484 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1486 netif_tx_stop_all_queues(ndev);
1488 /* Disable interrupts by clearing the interrupt masks. */
1489 ravb_write(ndev, 0, RIC0);
1490 ravb_write(ndev, 0, RIC1);
1491 ravb_write(ndev, 0, RIC2);
1492 ravb_write(ndev, 0, TIC);
1494 /* Stop PTP Clock driver */
1495 ravb_ptp_stop(ndev);
1497 /* Set the config mode to stop the AVB-DMAC's processes */
1498 if (ravb_stop_dma(ndev) < 0)
1500 "device will be stopped after h/w processes are done.\n");
1502 /* Clear the timestamp list */
1503 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1504 list_del(&ts_skb->list);
1508 /* PHY disconnect */
1510 phy_stop(priv->phydev);
1511 phy_disconnect(priv->phydev);
1512 priv->phydev = NULL;
1515 free_irq(ndev->irq, ndev);
1517 napi_disable(&priv->napi[RAVB_NC]);
1518 napi_disable(&priv->napi[RAVB_BE]);
1520 /* Free all the skb's in the RX queue and the DMA buffers. */
1521 ravb_ring_free(ndev, RAVB_BE);
1522 ravb_ring_free(ndev, RAVB_NC);
1527 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1529 struct ravb_private *priv = netdev_priv(ndev);
1530 struct hwtstamp_config config;
1533 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1535 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1536 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1537 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1538 config.rx_filter = HWTSTAMP_FILTER_ALL;
1540 config.rx_filter = HWTSTAMP_FILTER_NONE;
1542 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1546 /* Control hardware time stamping */
1547 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1549 struct ravb_private *priv = netdev_priv(ndev);
1550 struct hwtstamp_config config;
1551 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1554 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1557 /* Reserved for future extensions */
1561 switch (config.tx_type) {
1562 case HWTSTAMP_TX_OFF:
1565 case HWTSTAMP_TX_ON:
1566 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1572 switch (config.rx_filter) {
1573 case HWTSTAMP_FILTER_NONE:
1576 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1577 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1580 config.rx_filter = HWTSTAMP_FILTER_ALL;
1581 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1584 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1585 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1587 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1591 /* ioctl to device function */
1592 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1594 struct ravb_private *priv = netdev_priv(ndev);
1595 struct phy_device *phydev = priv->phydev;
1597 if (!netif_running(ndev))
1605 return ravb_hwtstamp_get(ndev, req);
1607 return ravb_hwtstamp_set(ndev, req);
1610 return phy_mii_ioctl(phydev, req, cmd);
1613 static const struct net_device_ops ravb_netdev_ops = {
1614 .ndo_open = ravb_open,
1615 .ndo_stop = ravb_close,
1616 .ndo_start_xmit = ravb_start_xmit,
1617 .ndo_select_queue = ravb_select_queue,
1618 .ndo_get_stats = ravb_get_stats,
1619 .ndo_set_rx_mode = ravb_set_rx_mode,
1620 .ndo_tx_timeout = ravb_tx_timeout,
1621 .ndo_do_ioctl = ravb_do_ioctl,
1622 .ndo_validate_addr = eth_validate_addr,
1623 .ndo_set_mac_address = eth_mac_addr,
1624 .ndo_change_mtu = eth_change_mtu,
1627 /* MDIO bus init function */
1628 static int ravb_mdio_init(struct ravb_private *priv)
1630 struct platform_device *pdev = priv->pdev;
1631 struct device *dev = &pdev->dev;
1635 priv->mdiobb.ops = &bb_ops;
1637 /* MII controller setting */
1638 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1642 /* Hook up MII support for ethtool */
1643 priv->mii_bus->name = "ravb_mii";
1644 priv->mii_bus->parent = dev;
1645 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1646 pdev->name, pdev->id);
1648 /* Register MDIO bus */
1649 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1656 free_mdio_bitbang(priv->mii_bus);
1660 /* MDIO bus release function */
1661 static int ravb_mdio_release(struct ravb_private *priv)
1663 /* Unregister mdio bus */
1664 mdiobus_unregister(priv->mii_bus);
1666 /* Free bitbang info */
1667 free_mdio_bitbang(priv->mii_bus);
1672 static const struct of_device_id ravb_match_table[] = {
1673 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1674 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1675 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1678 MODULE_DEVICE_TABLE(of, ravb_match_table);
1680 static int ravb_probe(struct platform_device *pdev)
1682 struct device_node *np = pdev->dev.of_node;
1683 const struct of_device_id *match;
1684 struct ravb_private *priv;
1685 enum ravb_chip_id chip_id;
1686 struct net_device *ndev;
1688 struct resource *res;
1692 "this driver is required to be instantiated from device tree\n");
1696 /* Get base address */
1697 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1699 dev_err(&pdev->dev, "invalid resource\n");
1703 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
1704 NUM_TX_QUEUE, NUM_RX_QUEUE);
1708 pm_runtime_enable(&pdev->dev);
1709 pm_runtime_get_sync(&pdev->dev);
1711 /* The Ether-specific entries in the device structure. */
1712 ndev->base_addr = res->start;
1715 match = of_match_device(of_match_ptr(ravb_match_table), &pdev->dev);
1716 chip_id = (enum ravb_chip_id)match->data;
1718 if (chip_id == RCAR_GEN3)
1719 irq = platform_get_irq_byname(pdev, "ch22");
1721 irq = platform_get_irq(pdev, 0);
1728 SET_NETDEV_DEV(ndev, &pdev->dev);
1730 priv = netdev_priv(ndev);
1733 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
1734 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
1735 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
1736 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
1737 priv->addr = devm_ioremap_resource(&pdev->dev, res);
1738 if (IS_ERR(priv->addr)) {
1739 error = PTR_ERR(priv->addr);
1743 spin_lock_init(&priv->lock);
1744 INIT_WORK(&priv->work, ravb_tx_timeout_work);
1746 priv->phy_interface = of_get_phy_mode(np);
1748 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
1749 priv->avb_link_active_low =
1750 of_property_read_bool(np, "renesas,ether-link-active-low");
1752 if (chip_id == RCAR_GEN3) {
1753 irq = platform_get_irq_byname(pdev, "ch24");
1758 priv->emac_irq = irq;
1761 priv->chip_id = chip_id;
1764 ndev->netdev_ops = &ravb_netdev_ops;
1765 ndev->ethtool_ops = &ravb_ethtool_ops;
1767 /* Set AVB config mode */
1768 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG,
1771 /* Set CSEL value */
1772 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) | CCC_CSEL_HPB,
1776 ravb_write(ndev, ((1000 << 20) / 130) & GTI_TIV, GTI);
1778 /* Request GTI loading */
1779 ravb_write(ndev, ravb_read(ndev, GCCR) | GCCR_LTI, GCCR);
1781 /* Allocate descriptor base address table */
1782 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
1783 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
1784 &priv->desc_bat_dma, GFP_KERNEL);
1785 if (!priv->desc_bat) {
1787 "Cannot allocate desc base address table (size %d bytes)\n",
1788 priv->desc_bat_size);
1792 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
1793 priv->desc_bat[q].die_dt = DT_EOS;
1794 ravb_write(ndev, priv->desc_bat_dma, DBAT);
1796 /* Initialise HW timestamp list */
1797 INIT_LIST_HEAD(&priv->ts_skb_list);
1799 /* Debug message level */
1800 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
1802 /* Read and set MAC address */
1803 ravb_read_mac_address(ndev, of_get_mac_address(np));
1804 if (!is_valid_ether_addr(ndev->dev_addr)) {
1805 dev_warn(&pdev->dev,
1806 "no valid MAC address supplied, using a random one\n");
1807 eth_hw_addr_random(ndev);
1811 error = ravb_mdio_init(priv);
1813 dev_err(&pdev->dev, "failed to initialize MDIO\n");
1817 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
1818 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
1820 /* Network device register */
1821 error = register_netdev(ndev);
1825 /* Print device information */
1826 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
1827 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
1829 platform_set_drvdata(pdev, ndev);
1834 netif_napi_del(&priv->napi[RAVB_NC]);
1835 netif_napi_del(&priv->napi[RAVB_BE]);
1836 ravb_mdio_release(priv);
1838 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
1839 priv->desc_bat_dma);
1844 pm_runtime_put(&pdev->dev);
1845 pm_runtime_disable(&pdev->dev);
1849 static int ravb_remove(struct platform_device *pdev)
1851 struct net_device *ndev = platform_get_drvdata(pdev);
1852 struct ravb_private *priv = netdev_priv(ndev);
1854 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
1855 priv->desc_bat_dma);
1856 /* Set reset mode */
1857 ravb_write(ndev, CCC_OPC_RESET, CCC);
1858 pm_runtime_put_sync(&pdev->dev);
1859 unregister_netdev(ndev);
1860 netif_napi_del(&priv->napi[RAVB_NC]);
1861 netif_napi_del(&priv->napi[RAVB_BE]);
1862 ravb_mdio_release(priv);
1863 pm_runtime_disable(&pdev->dev);
1865 platform_set_drvdata(pdev, NULL);
1871 static int ravb_runtime_nop(struct device *dev)
1873 /* Runtime PM callback shared between ->runtime_suspend()
1874 * and ->runtime_resume(). Simply returns success.
1876 * This driver re-initializes all registers after
1877 * pm_runtime_get_sync() anyway so there is no need
1878 * to save and restore registers here.
1883 static const struct dev_pm_ops ravb_dev_pm_ops = {
1884 .runtime_suspend = ravb_runtime_nop,
1885 .runtime_resume = ravb_runtime_nop,
1888 #define RAVB_PM_OPS (&ravb_dev_pm_ops)
1890 #define RAVB_PM_OPS NULL
1893 static struct platform_driver ravb_driver = {
1894 .probe = ravb_probe,
1895 .remove = ravb_remove,
1899 .of_match_table = ravb_match_table,
1903 module_platform_driver(ravb_driver);
1905 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
1906 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
1907 MODULE_LICENSE("GPL v2");