2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
46 #include <linux/interrupt.h>
47 #include <linux/spinlock.h>
49 #include <linux/mlx4/device.h>
50 #include <linux/mlx4/driver.h>
51 #include <linux/mlx4/doorbell.h>
52 #include <linux/mlx4/cmd.h>
55 #define DRV_NAME "mlx4_core"
56 #define PFX DRV_NAME ": "
57 #define DRV_VERSION "2.2-1"
58 #define DRV_RELDATE "Feb, 2014"
60 #define MLX4_FS_UDP_UC_EN (1 << 1)
61 #define MLX4_FS_TCP_UC_EN (1 << 2)
62 #define MLX4_FS_NUM_OF_L2_ADDR 8
63 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
64 #define MLX4_FS_NUM_MCG (1 << 17)
66 #define INIT_HCA_TPT_MW_ENABLE (1 << 7)
68 #define MLX4_QUERY_IF_STAT_RESET BIT(31)
71 MLX4_HCR_BASE = 0x80680,
72 MLX4_HCR_SIZE = 0x0001c,
73 MLX4_CLR_INT_SIZE = 0x00008,
74 MLX4_SLAVE_COMM_BASE = 0x0,
75 MLX4_COMM_PAGESIZE = 0x1000,
76 MLX4_CLOCK_SIZE = 0x00008,
77 MLX4_COMM_CHAN_CAPS = 0x8,
78 MLX4_COMM_CHAN_FLAGS = 0xc
82 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
83 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
84 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
85 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
86 MLX4_MTT_ENTRY_PER_SEG = 8,
90 MLX4_NUM_PDS = 1 << 15
94 MLX4_CMPT_TYPE_QP = 0,
95 MLX4_CMPT_TYPE_SRQ = 1,
96 MLX4_CMPT_TYPE_CQ = 2,
97 MLX4_CMPT_TYPE_EQ = 3,
102 MLX4_CMPT_SHIFT = 24,
103 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
106 enum mlx4_mpt_state {
107 MLX4_MPT_DISABLED = 0,
112 #define MLX4_COMM_TIME 10000
113 #define MLX4_COMM_OFFLINE_TIME_OUT 30000
114 #define MLX4_COMM_CMD_NA_OP 0x0
122 MLX4_COMM_CMD_VHCR_EN,
123 MLX4_COMM_CMD_VHCR_POST,
124 MLX4_COMM_CMD_FLR = 254
128 MLX4_VF_SMI_DISABLED,
132 /*The flag indicates that the slave should delay the RESET cmd*/
133 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
134 /*indicates how many retries will be done if we are in the middle of FLR*/
135 #define NUM_OF_RESET_RETRIES 10
136 #define SLEEP_TIME_IN_RESET (2 * 1000)
149 MLX4_NUM_OF_RESOURCE_TYPE
152 enum mlx4_alloc_mode {
154 RES_OP_RESERVE_AND_MAP,
158 enum mlx4_res_tracker_free_type {
160 RES_TR_FREE_SLAVES_ONLY,
161 RES_TR_FREE_STRUCTS_ONLY,
165 *Virtual HCR structures.
166 * mlx4_vhcr is the sw representation, in machine endianness
168 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
169 * to FW to go through communication channel.
170 * It is big endian, and has the same structure as the physical HCR
171 * used by command interface
184 struct mlx4_vhcr_cmd {
196 struct mlx4_cmd_info {
201 bool encode_slave_id;
202 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
203 struct mlx4_cmd_mailbox *inbox);
204 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
205 struct mlx4_cmd_mailbox *inbox,
206 struct mlx4_cmd_mailbox *outbox,
207 struct mlx4_cmd_info *cmd);
210 #ifdef CONFIG_MLX4_DEBUG
211 extern int mlx4_debug_level;
212 #else /* CONFIG_MLX4_DEBUG */
213 #define mlx4_debug_level (0)
214 #endif /* CONFIG_MLX4_DEBUG */
216 #define mlx4_dbg(mdev, format, ...) \
218 if (mlx4_debug_level) \
219 dev_printk(KERN_DEBUG, \
220 &(mdev)->persist->pdev->dev, format, \
224 #define mlx4_err(mdev, format, ...) \
225 dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
226 #define mlx4_info(mdev, format, ...) \
227 dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
228 #define mlx4_warn(mdev, format, ...) \
229 dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
231 extern int mlx4_log_num_mgm_entry_size;
232 extern int log_mtts_per_seg;
233 extern int mlx4_internal_err_reset;
235 #define MLX4_MAX_NUM_SLAVES (min(MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF, \
237 #define ALL_SLAVES 0xff
248 unsigned long *table;
252 unsigned long **bits;
253 unsigned int *num_free;
260 struct mlx4_icm_table {
268 struct mlx4_icm **icm;
271 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
272 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
273 #define MLX4_MPT_FLAG_MIO (1 << 17)
274 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
275 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
276 #define MLX4_MPT_FLAG_REGION (1 << 8)
278 #define MLX4_MPT_PD_MASK (0x1FFFFUL)
279 #define MLX4_MPT_PD_VF_MASK (0xFE0000UL)
280 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
281 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
282 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
284 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
286 #define MLX4_MPT_STATUS_SW 0xF0
287 #define MLX4_MPT_STATUS_HW 0x00
289 #define MLX4_CQE_SIZE_MASK_STRIDE 0x3
290 #define MLX4_EQE_SIZE_MASK_STRIDE 0x30
292 #define MLX4_EQ_ASYNC 0
293 #define MLX4_EQ_TO_CQ_VECTOR(vector) ((vector) - \
294 !!((int)(vector) >= MLX4_EQ_ASYNC))
295 #define MLX4_CQ_TO_EQ_VECTOR(vector) ((vector) + \
296 !!((int)(vector) >= MLX4_EQ_ASYNC))
299 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
301 struct mlx4_mpt_entry {
315 __be32 first_byte_offset;
319 * Must be packed because start is 64 bits but only aligned to 32 bits.
321 struct mlx4_eq_context {
335 __be32 mtt_base_addr_l;
337 __be32 consumer_index;
338 __be32 producer_index;
342 struct mlx4_cq_context {
346 __be32 logsize_usrpage;
354 __be32 mtt_base_addr_l;
355 __be32 last_notified_index;
356 __be32 solicit_producer_index;
357 __be32 consumer_index;
358 __be32 producer_index;
363 struct mlx4_srq_context {
364 __be32 state_logsize_srqn;
368 __be32 pg_offset_cqn;
373 __be32 mtt_base_addr_l;
375 __be16 limit_watermark;
383 struct mlx4_eq_tasklet {
384 struct list_head list;
385 struct list_head process_list;
386 struct tasklet_struct task;
387 /* lock on completion tasklet list */
392 struct mlx4_dev *dev;
393 void __iomem *doorbell;
399 struct mlx4_buf_list *page_list;
401 struct mlx4_eq_tasklet tasklet_ctx;
402 struct mlx4_active_ports actv_ports;
404 cpumask_var_t affinity_mask;
407 struct mlx4_slave_eqe {
413 struct mlx4_slave_event_eq_info {
418 struct mlx4_profile {
433 struct mlx4_icm *fw_icm;
434 struct mlx4_icm *aux_icm;
449 MLX4_MCAST_CONFIG = 0,
450 MLX4_MCAST_DISABLE = 1,
451 MLX4_MCAST_ENABLE = 2,
454 #define VLAN_FLTR_SIZE 128
456 struct mlx4_vlan_fltr {
457 __be32 entry[VLAN_FLTR_SIZE];
460 struct mlx4_mcast_entry {
461 struct list_head list;
465 struct mlx4_promisc_qp {
466 struct list_head list;
470 struct mlx4_steer_index {
471 struct list_head list;
473 struct list_head duplicates;
476 #define MLX4_EVENT_TYPES_NUM 64
478 struct mlx4_slave_state {
486 u16 mtu[MLX4_MAX_PORTS + 1];
487 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
488 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
489 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
490 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
491 /* event type to eq number lookup */
492 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
496 /*initialized via the kzalloc*/
497 u8 is_slave_going_down;
499 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
502 #define MLX4_VGT 4095
505 struct mlx4_vport_state {
516 struct mlx4_vf_admin_state {
517 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
518 u8 enable_smi[MLX4_MAX_PORTS + 1];
521 struct mlx4_vport_oper_state {
522 struct mlx4_vport_state state;
527 struct mlx4_vf_oper_state {
528 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
529 u8 smi_enabled[MLX4_MAX_PORTS + 1];
534 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
537 struct resource_allocator {
538 spinlock_t alloc_lock; /* protect quotas */
541 int res_port_rsvd[MLX4_MAX_PORTS];
545 int res_port_free[MLX4_MAX_PORTS];
552 struct mlx4_resource_tracker {
554 /* tree for each resources */
555 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
556 /* num_of_slave's lists, one per slave */
557 struct slave_list *slave_list;
558 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
561 #define SLAVE_EVENT_EQ_SIZE 128
562 struct mlx4_slave_event_eq {
566 spinlock_t event_lock;
567 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
570 struct mlx4_qos_manager {
572 DECLARE_BITMAP(priority_bm, MLX4_NUM_UP);
575 struct mlx4_master_qp0_state {
576 int proxy_qp0_active;
581 struct mlx4_mfunc_master_ctx {
582 struct mlx4_slave_state *slave_state;
583 struct mlx4_vf_admin_state *vf_admin;
584 struct mlx4_vf_oper_state *vf_oper;
585 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
586 int init_port_ref[MLX4_MAX_PORTS + 1];
587 u16 max_mtu[MLX4_MAX_PORTS + 1];
588 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
589 struct mlx4_resource_tracker res_tracker;
590 struct workqueue_struct *comm_wq;
591 struct work_struct comm_work;
592 struct work_struct slave_event_work;
593 struct work_struct slave_flr_event_work;
594 spinlock_t slave_state_lock;
595 __be32 comm_arm_bit_vector[4];
596 struct mlx4_eqe cmd_eqe;
597 struct mlx4_slave_event_eq slave_eq;
598 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
599 struct mlx4_qos_manager qos_ctl[MLX4_MAX_PORTS + 1];
603 struct mlx4_comm __iomem *comm;
604 struct mlx4_vhcr_cmd *vhcr;
607 struct mlx4_mfunc_master_ctx master;
610 #define MGM_QPN_MASK 0x00FFFFFF
611 #define MGM_BLCK_LB_BIT 30
614 __be32 next_gid_index;
615 __be32 members_count;
618 __be32 qp[MLX4_MAX_QP_PER_MGM];
622 struct pci_pool *pool;
624 struct mutex slave_cmd_mutex;
625 struct semaphore poll_sem;
626 struct semaphore event_sem;
628 spinlock_t context_lock;
630 struct mlx4_cmd_context *context;
639 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
640 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
641 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2,
643 struct mlx4_vf_immed_vlan_work {
644 struct work_struct work;
645 struct mlx4_priv *priv;
658 struct mlx4_uar_table {
659 struct mlx4_bitmap bitmap;
662 struct mlx4_mr_table {
663 struct mlx4_bitmap mpt_bitmap;
664 struct mlx4_buddy mtt_buddy;
667 struct mlx4_icm_table mtt_table;
668 struct mlx4_icm_table dmpt_table;
671 struct mlx4_cq_table {
672 struct mlx4_bitmap bitmap;
674 struct radix_tree_root tree;
675 struct mlx4_icm_table table;
676 struct mlx4_icm_table cmpt_table;
679 struct mlx4_eq_table {
680 struct mlx4_bitmap bitmap;
682 void __iomem *clr_int;
683 void __iomem **uar_map;
686 struct mlx4_icm_table table;
687 struct mlx4_icm_table cmpt_table;
692 struct mlx4_srq_table {
693 struct mlx4_bitmap bitmap;
695 struct radix_tree_root tree;
696 struct mlx4_icm_table table;
697 struct mlx4_icm_table cmpt_table;
700 enum mlx4_qp_table_zones {
701 MLX4_QP_TABLE_ZONE_GENERAL,
702 MLX4_QP_TABLE_ZONE_RSS,
703 MLX4_QP_TABLE_ZONE_RAW_ETH,
704 MLX4_QP_TABLE_ZONE_NUM
707 struct mlx4_qp_table {
708 struct mlx4_bitmap *bitmap_gen;
709 struct mlx4_zone_allocator *zones;
710 u32 zones_uids[MLX4_QP_TABLE_ZONE_NUM];
714 struct mlx4_icm_table qp_table;
715 struct mlx4_icm_table auxc_table;
716 struct mlx4_icm_table altc_table;
717 struct mlx4_icm_table rdmarc_table;
718 struct mlx4_icm_table cmpt_table;
721 struct mlx4_mcg_table {
723 struct mlx4_bitmap bitmap;
724 struct mlx4_icm_table table;
727 struct mlx4_catas_err {
729 struct timer_list timer;
730 struct list_head list;
733 #define MLX4_MAX_MAC_NUM 128
734 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
736 struct mlx4_mac_table {
737 __be64 entries[MLX4_MAX_MAC_NUM];
738 int refs[MLX4_MAX_MAC_NUM];
744 #define MLX4_ROCE_GID_ENTRY_SIZE 16
746 struct mlx4_roce_gid_entry {
747 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE];
750 struct mlx4_roce_gid_table {
751 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS];
755 #define MLX4_MAX_VLAN_NUM 128
756 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
758 struct mlx4_vlan_table {
759 __be32 entries[MLX4_MAX_VLAN_NUM];
760 int refs[MLX4_MAX_VLAN_NUM];
766 #define SET_PORT_GEN_ALL_VALID 0x7
767 #define SET_PORT_PROMISC_SHIFT 31
768 #define SET_PORT_MC_PROMISC_SHIFT 30
771 MCAST_DIRECT_ONLY = 0,
777 struct mlx4_set_port_general_context {
795 struct mlx4_set_port_rqp_calc_context {
813 struct mlx4_port_info {
814 struct mlx4_dev *dev;
817 struct device_attribute port_attr;
818 enum mlx4_port_type tmp_type;
819 char dev_mtu_name[16];
820 struct device_attribute port_mtu_attr;
821 struct mlx4_mac_table mac_table;
822 struct mlx4_vlan_table vlan_table;
823 struct mlx4_roce_gid_table gid_table;
825 struct cpu_rmap *rmap;
829 struct mlx4_dev *dev;
830 u8 do_sense_port[MLX4_MAX_PORTS + 1];
831 u8 sense_allowed[MLX4_MAX_PORTS + 1];
832 struct delayed_work sense_poll;
835 struct mlx4_msix_ctl {
836 DECLARE_BITMAP(pool_bm, MAX_MSIX);
837 struct mutex pool_lock;
841 struct list_head promisc_qps[MLX4_NUM_STEERS];
842 struct list_head steer_entries[MLX4_NUM_STEERS];
846 MLX4_PCI_DEV_IS_VF = 1 << 0,
847 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
858 struct list_head dev_list;
859 struct list_head ctx_list;
865 struct list_head pgdir_list;
866 struct mutex pgdir_mutex;
870 struct mlx4_mfunc mfunc;
872 struct mlx4_bitmap pd_bitmap;
873 struct mlx4_bitmap xrcd_bitmap;
874 struct mlx4_uar_table uar_table;
875 struct mlx4_mr_table mr_table;
876 struct mlx4_cq_table cq_table;
877 struct mlx4_eq_table eq_table;
878 struct mlx4_srq_table srq_table;
879 struct mlx4_qp_table qp_table;
880 struct mlx4_mcg_table mcg_table;
881 struct mlx4_bitmap counters_bitmap;
882 int def_counter[MLX4_MAX_PORTS];
884 struct mlx4_catas_err catas_err;
886 void __iomem *clr_base;
888 struct mlx4_uar driver_uar;
890 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
891 struct mlx4_sense sense;
892 struct mutex port_mutex;
893 struct mlx4_msix_ctl msix_ctl;
894 struct mlx4_steer *steer;
895 struct list_head bf_list;
896 struct mutex bf_mutex;
897 struct io_mapping *bf_mapping;
898 void __iomem *clock_mapping;
901 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
902 struct mlx4_port_map v2p; /* cached port mapping configuration */
903 struct mutex bond_mutex; /* for bond mode */
904 __be64 slave_node_guids[MLX4_MFUNC_MAX];
906 atomic_t opreq_count;
907 struct work_struct opreq_task;
910 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
912 return container_of(dev, struct mlx4_priv, dev);
915 #define MLX4_SENSE_RANGE (HZ * 3)
917 extern struct workqueue_struct *mlx4_wq;
919 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
920 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
921 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt,
922 int align, u32 skip_mask);
923 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
925 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
926 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
927 u32 reserved_bot, u32 resetrved_top);
928 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
930 int mlx4_reset(struct mlx4_dev *dev);
932 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
933 void mlx4_free_eq_table(struct mlx4_dev *dev);
935 int mlx4_init_pd_table(struct mlx4_dev *dev);
936 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
937 int mlx4_init_uar_table(struct mlx4_dev *dev);
938 int mlx4_init_mr_table(struct mlx4_dev *dev);
939 int mlx4_init_eq_table(struct mlx4_dev *dev);
940 int mlx4_init_cq_table(struct mlx4_dev *dev);
941 int mlx4_init_qp_table(struct mlx4_dev *dev);
942 int mlx4_init_srq_table(struct mlx4_dev *dev);
943 int mlx4_init_mcg_table(struct mlx4_dev *dev);
945 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
946 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
947 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
948 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
949 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
950 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
951 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
952 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
953 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
954 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp);
955 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
956 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
957 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
958 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
959 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
960 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
961 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
962 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp);
963 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
964 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
965 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
967 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
968 struct mlx4_vhcr *vhcr,
969 struct mlx4_cmd_mailbox *inbox,
970 struct mlx4_cmd_mailbox *outbox,
971 struct mlx4_cmd_info *cmd);
972 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
973 struct mlx4_vhcr *vhcr,
974 struct mlx4_cmd_mailbox *inbox,
975 struct mlx4_cmd_mailbox *outbox,
976 struct mlx4_cmd_info *cmd);
977 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
978 struct mlx4_vhcr *vhcr,
979 struct mlx4_cmd_mailbox *inbox,
980 struct mlx4_cmd_mailbox *outbox,
981 struct mlx4_cmd_info *cmd);
982 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
983 struct mlx4_vhcr *vhcr,
984 struct mlx4_cmd_mailbox *inbox,
985 struct mlx4_cmd_mailbox *outbox,
986 struct mlx4_cmd_info *cmd);
987 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
988 struct mlx4_vhcr *vhcr,
989 struct mlx4_cmd_mailbox *inbox,
990 struct mlx4_cmd_mailbox *outbox,
991 struct mlx4_cmd_info *cmd);
992 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
993 struct mlx4_vhcr *vhcr,
994 struct mlx4_cmd_mailbox *inbox,
995 struct mlx4_cmd_mailbox *outbox,
996 struct mlx4_cmd_info *cmd);
997 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
998 struct mlx4_vhcr *vhcr,
999 struct mlx4_cmd_mailbox *inbox,
1000 struct mlx4_cmd_mailbox *outbox,
1001 struct mlx4_cmd_info *cmd);
1002 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
1003 struct mlx4_vhcr *vhcr,
1004 struct mlx4_cmd_mailbox *inbox,
1005 struct mlx4_cmd_mailbox *outbox,
1006 struct mlx4_cmd_info *cmd);
1007 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1008 int *base, u8 flags);
1009 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1010 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1011 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1012 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1013 int start_index, int npages, u64 *page_list);
1014 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1015 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1016 int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port,
1017 struct mlx4_counter *data);
1018 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1019 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1021 void mlx4_start_catas_poll(struct mlx4_dev *dev);
1022 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
1023 int mlx4_catas_init(struct mlx4_dev *dev);
1024 void mlx4_catas_end(struct mlx4_dev *dev);
1025 int mlx4_restart_one(struct pci_dev *pdev);
1026 int mlx4_register_device(struct mlx4_dev *dev);
1027 void mlx4_unregister_device(struct mlx4_dev *dev);
1028 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
1029 unsigned long param);
1031 struct mlx4_dev_cap;
1032 struct mlx4_init_hca_param;
1034 u64 mlx4_make_profile(struct mlx4_dev *dev,
1035 struct mlx4_profile *request,
1036 struct mlx4_dev_cap *dev_cap,
1037 struct mlx4_init_hca_param *init_hca);
1038 void mlx4_master_comm_channel(struct work_struct *work);
1039 void mlx4_gen_slave_eqe(struct work_struct *work);
1040 void mlx4_master_handle_slave_flr(struct work_struct *work);
1042 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
1043 struct mlx4_vhcr *vhcr,
1044 struct mlx4_cmd_mailbox *inbox,
1045 struct mlx4_cmd_mailbox *outbox,
1046 struct mlx4_cmd_info *cmd);
1047 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
1048 struct mlx4_vhcr *vhcr,
1049 struct mlx4_cmd_mailbox *inbox,
1050 struct mlx4_cmd_mailbox *outbox,
1051 struct mlx4_cmd_info *cmd);
1052 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
1053 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1054 struct mlx4_cmd_mailbox *outbox,
1055 struct mlx4_cmd_info *cmd);
1056 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1057 struct mlx4_vhcr *vhcr,
1058 struct mlx4_cmd_mailbox *inbox,
1059 struct mlx4_cmd_mailbox *outbox,
1060 struct mlx4_cmd_info *cmd);
1061 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1062 struct mlx4_vhcr *vhcr,
1063 struct mlx4_cmd_mailbox *inbox,
1064 struct mlx4_cmd_mailbox *outbox,
1065 struct mlx4_cmd_info *cmd);
1066 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1067 struct mlx4_vhcr *vhcr,
1068 struct mlx4_cmd_mailbox *inbox,
1069 struct mlx4_cmd_mailbox *outbox,
1070 struct mlx4_cmd_info *cmd);
1071 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1072 struct mlx4_vhcr *vhcr,
1073 struct mlx4_cmd_mailbox *inbox,
1074 struct mlx4_cmd_mailbox *outbox,
1075 struct mlx4_cmd_info *cmd);
1076 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1077 struct mlx4_vhcr *vhcr,
1078 struct mlx4_cmd_mailbox *inbox,
1079 struct mlx4_cmd_mailbox *outbox,
1080 struct mlx4_cmd_info *cmd);
1081 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1082 struct mlx4_vhcr *vhcr,
1083 struct mlx4_cmd_mailbox *inbox,
1084 struct mlx4_cmd_mailbox *outbox,
1085 struct mlx4_cmd_info *cmd);
1086 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1087 struct mlx4_vhcr *vhcr,
1088 struct mlx4_cmd_mailbox *inbox,
1089 struct mlx4_cmd_mailbox *outbox,
1090 struct mlx4_cmd_info *cmd);
1091 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1092 struct mlx4_vhcr *vhcr,
1093 struct mlx4_cmd_mailbox *inbox,
1094 struct mlx4_cmd_mailbox *outbox,
1095 struct mlx4_cmd_info *cmd);
1096 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1097 struct mlx4_vhcr *vhcr,
1098 struct mlx4_cmd_mailbox *inbox,
1099 struct mlx4_cmd_mailbox *outbox,
1100 struct mlx4_cmd_info *cmd);
1101 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1102 struct mlx4_vhcr *vhcr,
1103 struct mlx4_cmd_mailbox *inbox,
1104 struct mlx4_cmd_mailbox *outbox,
1105 struct mlx4_cmd_info *cmd);
1106 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1107 struct mlx4_vhcr *vhcr,
1108 struct mlx4_cmd_mailbox *inbox,
1109 struct mlx4_cmd_mailbox *outbox,
1110 struct mlx4_cmd_info *cmd);
1111 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1112 struct mlx4_vhcr *vhcr,
1113 struct mlx4_cmd_mailbox *inbox,
1114 struct mlx4_cmd_mailbox *outbox,
1115 struct mlx4_cmd_info *cmd);
1116 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1117 struct mlx4_vhcr *vhcr,
1118 struct mlx4_cmd_mailbox *inbox,
1119 struct mlx4_cmd_mailbox *outbox,
1120 struct mlx4_cmd_info *cmd);
1121 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1122 struct mlx4_vhcr *vhcr,
1123 struct mlx4_cmd_mailbox *inbox,
1124 struct mlx4_cmd_mailbox *outbox,
1125 struct mlx4_cmd_info *cmd);
1126 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1127 struct mlx4_vhcr *vhcr,
1128 struct mlx4_cmd_mailbox *inbox,
1129 struct mlx4_cmd_mailbox *outbox,
1130 struct mlx4_cmd_info *cmd);
1131 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1132 struct mlx4_vhcr *vhcr,
1133 struct mlx4_cmd_mailbox *inbox,
1134 struct mlx4_cmd_mailbox *outbox,
1135 struct mlx4_cmd_info *cmd);
1136 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1137 struct mlx4_vhcr *vhcr,
1138 struct mlx4_cmd_mailbox *inbox,
1139 struct mlx4_cmd_mailbox *outbox,
1140 struct mlx4_cmd_info *cmd);
1141 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1142 struct mlx4_vhcr *vhcr,
1143 struct mlx4_cmd_mailbox *inbox,
1144 struct mlx4_cmd_mailbox *outbox,
1145 struct mlx4_cmd_info *cmd);
1146 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1147 struct mlx4_vhcr *vhcr,
1148 struct mlx4_cmd_mailbox *inbox,
1149 struct mlx4_cmd_mailbox *outbox,
1150 struct mlx4_cmd_info *cmd);
1151 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1152 struct mlx4_vhcr *vhcr,
1153 struct mlx4_cmd_mailbox *inbox,
1154 struct mlx4_cmd_mailbox *outbox,
1155 struct mlx4_cmd_info *cmd);
1156 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1157 struct mlx4_vhcr *vhcr,
1158 struct mlx4_cmd_mailbox *inbox,
1159 struct mlx4_cmd_mailbox *outbox,
1160 struct mlx4_cmd_info *cmd);
1161 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1162 struct mlx4_vhcr *vhcr,
1163 struct mlx4_cmd_mailbox *inbox,
1164 struct mlx4_cmd_mailbox *outbox,
1165 struct mlx4_cmd_info *cmd);
1166 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1167 struct mlx4_vhcr *vhcr,
1168 struct mlx4_cmd_mailbox *inbox,
1169 struct mlx4_cmd_mailbox *outbox,
1170 struct mlx4_cmd_info *cmd);
1171 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1172 struct mlx4_vhcr *vhcr,
1173 struct mlx4_cmd_mailbox *inbox,
1174 struct mlx4_cmd_mailbox *outbox,
1175 struct mlx4_cmd_info *cmd);
1177 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1180 MLX4_CMD_CLEANUP_STRUCT = 1UL << 0,
1181 MLX4_CMD_CLEANUP_POOL = 1UL << 1,
1182 MLX4_CMD_CLEANUP_HCR = 1UL << 2,
1183 MLX4_CMD_CLEANUP_VHCR = 1UL << 3,
1184 MLX4_CMD_CLEANUP_ALL = (MLX4_CMD_CLEANUP_VHCR << 1) - 1
1187 int mlx4_cmd_init(struct mlx4_dev *dev);
1188 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask);
1189 int mlx4_multi_func_init(struct mlx4_dev *dev);
1190 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev);
1191 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1192 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1193 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1194 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1196 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1197 u16 op, unsigned long timeout);
1199 void mlx4_cq_tasklet_cb(unsigned long data);
1200 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1201 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1203 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1205 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1207 void mlx4_enter_error_state(struct mlx4_dev_persistent *persist);
1209 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1210 enum mlx4_port_type *type);
1211 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1212 enum mlx4_port_type *stype,
1213 enum mlx4_port_type *defaults);
1214 void mlx4_start_sense(struct mlx4_dev *dev);
1215 void mlx4_stop_sense(struct mlx4_dev *dev);
1216 void mlx4_sense_init(struct mlx4_dev *dev);
1217 int mlx4_check_port_params(struct mlx4_dev *dev,
1218 enum mlx4_port_type *port_type);
1219 int mlx4_change_port_types(struct mlx4_dev *dev,
1220 enum mlx4_port_type *port_types);
1222 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1223 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1224 void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
1225 struct mlx4_roce_gid_table *table);
1226 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1227 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1229 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1230 /* resource tracker functions*/
1231 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1232 enum mlx4_resource resource_type,
1233 u64 resource_id, int *slave);
1234 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1235 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave);
1236 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1238 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1239 enum mlx4_res_tracker_free_type type);
1241 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1242 struct mlx4_vhcr *vhcr,
1243 struct mlx4_cmd_mailbox *inbox,
1244 struct mlx4_cmd_mailbox *outbox,
1245 struct mlx4_cmd_info *cmd);
1246 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1247 struct mlx4_vhcr *vhcr,
1248 struct mlx4_cmd_mailbox *inbox,
1249 struct mlx4_cmd_mailbox *outbox,
1250 struct mlx4_cmd_info *cmd);
1251 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1252 struct mlx4_vhcr *vhcr,
1253 struct mlx4_cmd_mailbox *inbox,
1254 struct mlx4_cmd_mailbox *outbox,
1255 struct mlx4_cmd_info *cmd);
1256 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1257 struct mlx4_vhcr *vhcr,
1258 struct mlx4_cmd_mailbox *inbox,
1259 struct mlx4_cmd_mailbox *outbox,
1260 struct mlx4_cmd_info *cmd);
1261 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1262 struct mlx4_vhcr *vhcr,
1263 struct mlx4_cmd_mailbox *inbox,
1264 struct mlx4_cmd_mailbox *outbox,
1265 struct mlx4_cmd_info *cmd);
1266 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1267 struct mlx4_vhcr *vhcr,
1268 struct mlx4_cmd_mailbox *inbox,
1269 struct mlx4_cmd_mailbox *outbox,
1270 struct mlx4_cmd_info *cmd);
1271 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1273 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1274 int *gid_tbl_len, int *pkey_tbl_len);
1276 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1277 struct mlx4_vhcr *vhcr,
1278 struct mlx4_cmd_mailbox *inbox,
1279 struct mlx4_cmd_mailbox *outbox,
1280 struct mlx4_cmd_info *cmd);
1282 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
1283 struct mlx4_vhcr *vhcr,
1284 struct mlx4_cmd_mailbox *inbox,
1285 struct mlx4_cmd_mailbox *outbox,
1286 struct mlx4_cmd_info *cmd);
1288 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1289 struct mlx4_vhcr *vhcr,
1290 struct mlx4_cmd_mailbox *inbox,
1291 struct mlx4_cmd_mailbox *outbox,
1292 struct mlx4_cmd_info *cmd);
1293 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1294 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1295 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1296 int block_mcast_loopback, enum mlx4_protocol prot,
1297 enum mlx4_steer_type steer);
1298 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1299 u8 gid[16], u8 port,
1300 int block_mcast_loopback,
1301 enum mlx4_protocol prot, u64 *reg_id);
1302 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1303 struct mlx4_vhcr *vhcr,
1304 struct mlx4_cmd_mailbox *inbox,
1305 struct mlx4_cmd_mailbox *outbox,
1306 struct mlx4_cmd_info *cmd);
1307 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1308 struct mlx4_vhcr *vhcr,
1309 struct mlx4_cmd_mailbox *inbox,
1310 struct mlx4_cmd_mailbox *outbox,
1311 struct mlx4_cmd_info *cmd);
1312 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1313 int port, void *buf);
1314 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1315 struct mlx4_cmd_mailbox *outbox);
1316 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1317 struct mlx4_vhcr *vhcr,
1318 struct mlx4_cmd_mailbox *inbox,
1319 struct mlx4_cmd_mailbox *outbox,
1320 struct mlx4_cmd_info *cmd);
1321 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1322 struct mlx4_vhcr *vhcr,
1323 struct mlx4_cmd_mailbox *inbox,
1324 struct mlx4_cmd_mailbox *outbox,
1325 struct mlx4_cmd_info *cmd);
1326 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1327 struct mlx4_vhcr *vhcr,
1328 struct mlx4_cmd_mailbox *inbox,
1329 struct mlx4_cmd_mailbox *outbox,
1330 struct mlx4_cmd_info *cmd);
1331 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1332 struct mlx4_vhcr *vhcr,
1333 struct mlx4_cmd_mailbox *inbox,
1334 struct mlx4_cmd_mailbox *outbox,
1335 struct mlx4_cmd_info *cmd);
1336 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1337 struct mlx4_vhcr *vhcr,
1338 struct mlx4_cmd_mailbox *inbox,
1339 struct mlx4_cmd_mailbox *outbox,
1340 struct mlx4_cmd_info *cmd);
1341 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
1342 struct mlx4_vhcr *vhcr,
1343 struct mlx4_cmd_mailbox *inbox,
1344 struct mlx4_cmd_mailbox *outbox,
1345 struct mlx4_cmd_info *cmd);
1347 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1348 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1350 static inline void set_param_l(u64 *arg, u32 val)
1352 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1355 static inline void set_param_h(u64 *arg, u32 val)
1357 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1360 static inline u32 get_param_l(u64 *arg)
1362 return (u32) (*arg & 0xffffffff);
1365 static inline u32 get_param_h(u64 *arg)
1367 return (u32)(*arg >> 32);
1370 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1372 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1375 #define NOT_MASKED_PD_BITS 17
1377 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1379 void mlx4_init_quotas(struct mlx4_dev *dev);
1381 /* for VFs, replace zero MACs with randomly-generated MACs at driver start */
1382 void mlx4_replace_zero_macs(struct mlx4_dev *dev);
1383 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);
1384 /* Returns the VF index of slave */
1385 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);
1386 int mlx4_config_mad_demux(struct mlx4_dev *dev);
1387 int mlx4_do_bond(struct mlx4_dev *dev, bool enable);
1389 enum mlx4_zone_flags {
1390 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO = 1UL << 0,
1391 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO = 1UL << 1,
1392 MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO = 1UL << 2,
1393 MLX4_ZONE_USE_RR = 1UL << 3,
1396 enum mlx4_zone_alloc_flags {
1397 /* No two objects could overlap between zones. UID
1398 * could be left unused. If this flag is given and
1399 * two overlapped zones are used, an object will be free'd
1400 * from the smallest possible matching zone.
1402 MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP = 1UL << 0,
1405 struct mlx4_zone_allocator;
1407 /* Create a new zone allocator */
1408 struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags);
1410 /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator
1411 * <zone_alloc>. Allocating an object from this zone adds an offset <offset>.
1412 * Similarly, when searching for an object to free, this offset it taken into
1413 * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap>
1414 * is given through the MLX4_ZONE_USE_RR flag in <flags>.
1415 * When an allocation fails, <zone_alloc> tries to allocate from other zones
1416 * according to the policy set by <flags>. <puid> is the unique identifier
1417 * received to this zone.
1419 int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc,
1420 struct mlx4_bitmap *bitmap,
1426 /* Remove bitmap indicated by <uid> from <zone_alloc> */
1427 int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid);
1429 /* Delete the zone allocator <zone_alloc. This function doesn't destroy
1430 * the attached bitmaps.
1432 void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc);
1434 /* Allocate <count> objects with align <align> and skip_mask <skip_mask>
1435 * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually
1436 * allocated from is returned in <puid>. If the allocation fails, a negative
1437 * number is returned. Otherwise, the offset of the first object is returned.
1439 u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count,
1440 int align, u32 skip_mask, u32 *puid);
1442 /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator
1445 u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones,
1446 u32 uid, u32 obj, u32 count);
1448 /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of
1449 * specifying the uid when freeing an object, zone allocator could figure it by
1450 * itself. Other parameters are similar to mlx4_zone_free.
1452 u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count);
1454 /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */
1455 struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid);