1 /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
3 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, see <http://www.gnu.org/licenses/>.
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/pci.h>
21 #include <linux/ptp_classify.h>
25 #define INCVALUE_MASK 0x7fffffff
26 #define ISGN 0x80000000
28 /* The 82580 timesync updates the system timer every 8ns by 8ns,
29 * and this update value cannot be reprogrammed.
31 * Neither the 82576 nor the 82580 offer registers wide enough to hold
32 * nanoseconds time values for very long. For the 82580, SYSTIM always
33 * counts nanoseconds, but the upper 24 bits are not available. The
34 * frequency is adjusted by changing the 32 bit fractional nanoseconds
37 * For the 82576, the SYSTIM register time unit is affect by the
38 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
39 * field are needed to provide the nominal 16 nanosecond period,
40 * leaving 19 bits for fractional nanoseconds.
42 * We scale the NIC clock cycle by a large factor so that relatively
43 * small clock corrections can be added or subtracted at each clock
44 * tick. The drawbacks of a large factor are a) that the clock
45 * register overflows more quickly (not such a big deal) and b) that
46 * the increment per tick has to fit into 24 bits. As a result we
47 * need to use a shift of 19 so we can fit a value of 16 into the
52 * +--------------+ +---+---+------+
53 * 82576 | 32 | | 8 | 5 | 19 |
54 * +--------------+ +---+---+------+
55 * \________ 45 bits _______/ fract
57 * +----------+---+ +--------------+
58 * 82580 | 24 | 8 | | 32 |
59 * +----------+---+ +--------------+
60 * reserved \______ 40 bits _____/
63 * The 45 bit 82576 SYSTIM overflows every
64 * 2^45 * 10^-9 / 3600 = 9.77 hours.
66 * The 40 bit 82580 SYSTIM overflows every
67 * 2^40 * 10^-9 / 60 = 18.3 minutes.
70 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
71 #define IGB_PTP_TX_TIMEOUT (HZ * 15)
72 #define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
73 #define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
74 #define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
75 #define IGB_NBITS_82580 40
77 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
79 /* SYSTIM read access for the 82576 */
80 static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc)
82 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
83 struct e1000_hw *hw = &igb->hw;
87 lo = rd32(E1000_SYSTIML);
88 hi = rd32(E1000_SYSTIMH);
90 val = ((u64) hi) << 32;
96 /* SYSTIM read access for the 82580 */
97 static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc)
99 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
100 struct e1000_hw *hw = &igb->hw;
104 /* The timestamp latches on lowest register read. For the 82580
105 * the lowest register is SYSTIMR instead of SYSTIML. However we only
106 * need to provide nanosecond resolution, so we just ignore it.
109 lo = rd32(E1000_SYSTIML);
110 hi = rd32(E1000_SYSTIMH);
112 val = ((u64) hi) << 32;
118 /* SYSTIM read access for I210/I211 */
119 static void igb_ptp_read_i210(struct igb_adapter *adapter,
120 struct timespec64 *ts)
122 struct e1000_hw *hw = &adapter->hw;
125 /* The timestamp latches on lowest register read. For I210/I211, the
126 * lowest register is SYSTIMR. Since we only need to provide nanosecond
127 * resolution, we can ignore it.
130 nsec = rd32(E1000_SYSTIML);
131 sec = rd32(E1000_SYSTIMH);
137 static void igb_ptp_write_i210(struct igb_adapter *adapter,
138 const struct timespec64 *ts)
140 struct e1000_hw *hw = &adapter->hw;
142 /* Writing the SYSTIMR register is not necessary as it only provides
143 * sub-nanosecond resolution.
145 wr32(E1000_SYSTIML, ts->tv_nsec);
146 wr32(E1000_SYSTIMH, (u32)ts->tv_sec);
150 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
151 * @adapter: board private structure
152 * @hwtstamps: timestamp structure to update
153 * @systim: unsigned 64bit system time value.
155 * We need to convert the system time value stored in the RX/TXSTMP registers
156 * into a hwtstamp which can be used by the upper level timestamping functions.
158 * The 'tmreg_lock' spinlock is used to protect the consistency of the
159 * system time value. This is needed because reading the 64 bit time
160 * value involves reading two (or three) 32 bit registers. The first
161 * read latches the value. Ditto for writing.
163 * In addition, here have extended the system time with an overflow
164 * counter in software.
166 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
167 struct skb_shared_hwtstamps *hwtstamps,
173 switch (adapter->hw.mac.type) {
178 spin_lock_irqsave(&adapter->tmreg_lock, flags);
180 ns = timecounter_cyc2time(&adapter->tc, systim);
182 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
184 memset(hwtstamps, 0, sizeof(*hwtstamps));
185 hwtstamps->hwtstamp = ns_to_ktime(ns);
189 memset(hwtstamps, 0, sizeof(*hwtstamps));
190 /* Upper 32 bits contain s, lower 32 bits contain ns. */
191 hwtstamps->hwtstamp = ktime_set(systim >> 32,
192 systim & 0xFFFFFFFF);
199 /* PTP clock operations */
200 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
202 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
204 struct e1000_hw *hw = &igb->hw;
215 rate = div_u64(rate, 1953125);
217 incvalue = 16 << IGB_82576_TSYNC_SHIFT;
224 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
229 static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb)
231 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
233 struct e1000_hw *hw = &igb->hw;
244 rate = div_u64(rate, 1953125);
246 inca = rate & INCVALUE_MASK;
250 wr32(E1000_TIMINCA, inca);
255 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
257 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
261 spin_lock_irqsave(&igb->tmreg_lock, flags);
262 timecounter_adjtime(&igb->tc, delta);
263 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
268 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
270 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
273 struct timespec64 now, then = ns_to_timespec64(delta);
275 spin_lock_irqsave(&igb->tmreg_lock, flags);
277 igb_ptp_read_i210(igb, &now);
278 now = timespec64_add(now, then);
279 igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
281 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
286 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
287 struct timespec64 *ts)
289 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
294 spin_lock_irqsave(&igb->tmreg_lock, flags);
296 ns = timecounter_read(&igb->tc);
298 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
300 *ts = ns_to_timespec64(ns);
305 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
306 struct timespec64 *ts)
308 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
312 spin_lock_irqsave(&igb->tmreg_lock, flags);
314 igb_ptp_read_i210(igb, ts);
316 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
321 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
322 const struct timespec64 *ts)
324 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
329 ns = timespec64_to_ns(ts);
331 spin_lock_irqsave(&igb->tmreg_lock, flags);
333 timecounter_init(&igb->tc, &igb->cc, ns);
335 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
340 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
341 const struct timespec64 *ts)
343 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
347 spin_lock_irqsave(&igb->tmreg_lock, flags);
349 igb_ptp_write_i210(igb, ts);
351 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
356 static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
358 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
359 static const u32 mask[IGB_N_SDP] = {
362 E1000_CTRL_EXT_SDP2_DIR,
363 E1000_CTRL_EXT_SDP3_DIR,
372 static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
374 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
375 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
377 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
378 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
380 static const u32 ts_sdp_en[IGB_N_SDP] = {
381 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
383 struct e1000_hw *hw = &igb->hw;
384 u32 ctrl, ctrl_ext, tssdp = 0;
386 ctrl = rd32(E1000_CTRL);
387 ctrl_ext = rd32(E1000_CTRL_EXT);
388 tssdp = rd32(E1000_TSSDP);
390 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
392 /* Make sure this pin is not enabled as an output. */
393 tssdp &= ~ts_sdp_en[pin];
396 tssdp &= ~AUX1_SEL_SDP3;
397 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
399 tssdp &= ~AUX0_SEL_SDP3;
400 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
403 wr32(E1000_TSSDP, tssdp);
404 wr32(E1000_CTRL, ctrl);
405 wr32(E1000_CTRL_EXT, ctrl_ext);
408 static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
410 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
411 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
413 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
414 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
416 static const u32 ts_sdp_en[IGB_N_SDP] = {
417 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
419 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
420 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
421 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
423 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
424 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
425 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
427 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
428 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
429 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
431 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
432 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
433 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
435 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
436 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
437 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
439 struct e1000_hw *hw = &igb->hw;
440 u32 ctrl, ctrl_ext, tssdp = 0;
442 ctrl = rd32(E1000_CTRL);
443 ctrl_ext = rd32(E1000_CTRL_EXT);
444 tssdp = rd32(E1000_TSSDP);
446 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
448 /* Make sure this pin is not enabled as an input. */
449 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
450 tssdp &= ~AUX0_TS_SDP_EN;
452 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
453 tssdp &= ~AUX1_TS_SDP_EN;
455 tssdp &= ~ts_sdp_sel_clr[pin];
458 tssdp |= ts_sdp_sel_fc1[pin];
460 tssdp |= ts_sdp_sel_fc0[pin];
463 tssdp |= ts_sdp_sel_tt1[pin];
465 tssdp |= ts_sdp_sel_tt0[pin];
467 tssdp |= ts_sdp_en[pin];
469 wr32(E1000_TSSDP, tssdp);
470 wr32(E1000_CTRL, ctrl);
471 wr32(E1000_CTRL_EXT, ctrl_ext);
474 static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
475 struct ptp_clock_request *rq, int on)
477 struct igb_adapter *igb =
478 container_of(ptp, struct igb_adapter, ptp_caps);
479 struct e1000_hw *hw = &igb->hw;
480 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
482 struct timespec64 ts;
483 int use_freq = 0, pin = -1;
487 case PTP_CLK_REQ_EXTTS:
489 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
494 if (rq->extts.index == 1) {
495 tsauxc_mask = TSAUXC_EN_TS1;
496 tsim_mask = TSINTR_AUTT1;
498 tsauxc_mask = TSAUXC_EN_TS0;
499 tsim_mask = TSINTR_AUTT0;
501 spin_lock_irqsave(&igb->tmreg_lock, flags);
502 tsauxc = rd32(E1000_TSAUXC);
503 tsim = rd32(E1000_TSIM);
505 igb_pin_extts(igb, rq->extts.index, pin);
506 tsauxc |= tsauxc_mask;
509 tsauxc &= ~tsauxc_mask;
512 wr32(E1000_TSAUXC, tsauxc);
513 wr32(E1000_TSIM, tsim);
514 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
517 case PTP_CLK_REQ_PEROUT:
519 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
524 ts.tv_sec = rq->perout.period.sec;
525 ts.tv_nsec = rq->perout.period.nsec;
526 ns = timespec64_to_ns(&ts);
528 if (on && ns <= 70000000LL) {
533 ts = ns_to_timespec64(ns);
534 if (rq->perout.index == 1) {
536 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
539 tsauxc_mask = TSAUXC_EN_TT1;
540 tsim_mask = TSINTR_TT1;
542 trgttiml = E1000_TRGTTIML1;
543 trgttimh = E1000_TRGTTIMH1;
544 freqout = E1000_FREQOUT1;
547 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
550 tsauxc_mask = TSAUXC_EN_TT0;
551 tsim_mask = TSINTR_TT0;
553 trgttiml = E1000_TRGTTIML0;
554 trgttimh = E1000_TRGTTIMH0;
555 freqout = E1000_FREQOUT0;
557 spin_lock_irqsave(&igb->tmreg_lock, flags);
558 tsauxc = rd32(E1000_TSAUXC);
559 tsim = rd32(E1000_TSIM);
560 if (rq->perout.index == 1) {
561 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
564 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
568 int i = rq->perout.index;
569 igb_pin_perout(igb, i, pin, use_freq);
570 igb->perout[i].start.tv_sec = rq->perout.start.sec;
571 igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
572 igb->perout[i].period.tv_sec = ts.tv_sec;
573 igb->perout[i].period.tv_nsec = ts.tv_nsec;
574 wr32(trgttimh, rq->perout.start.sec);
575 wr32(trgttiml, rq->perout.start.nsec);
578 tsauxc |= tsauxc_mask;
581 wr32(E1000_TSAUXC, tsauxc);
582 wr32(E1000_TSIM, tsim);
583 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
586 case PTP_CLK_REQ_PPS:
587 spin_lock_irqsave(&igb->tmreg_lock, flags);
588 tsim = rd32(E1000_TSIM);
590 tsim |= TSINTR_SYS_WRAP;
592 tsim &= ~TSINTR_SYS_WRAP;
593 wr32(E1000_TSIM, tsim);
594 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
601 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
602 struct ptp_clock_request *rq, int on)
607 static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
608 enum ptp_pin_function func, unsigned int chan)
623 * @work: pointer to work struct
625 * This work function polls the TSYNCTXCTL valid bit to determine when a
626 * timestamp has been taken for the current stored skb.
628 static void igb_ptp_tx_work(struct work_struct *work)
630 struct igb_adapter *adapter = container_of(work, struct igb_adapter,
632 struct e1000_hw *hw = &adapter->hw;
635 if (!adapter->ptp_tx_skb)
638 if (time_is_before_jiffies(adapter->ptp_tx_start +
639 IGB_PTP_TX_TIMEOUT)) {
640 dev_kfree_skb_any(adapter->ptp_tx_skb);
641 adapter->ptp_tx_skb = NULL;
642 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
643 adapter->tx_hwtstamp_timeouts++;
644 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
648 tsynctxctl = rd32(E1000_TSYNCTXCTL);
649 if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
650 igb_ptp_tx_hwtstamp(adapter);
652 /* reschedule to check later */
653 schedule_work(&adapter->ptp_tx_work);
656 static void igb_ptp_overflow_check(struct work_struct *work)
658 struct igb_adapter *igb =
659 container_of(work, struct igb_adapter, ptp_overflow_work.work);
660 struct timespec64 ts;
662 igb->ptp_caps.gettime64(&igb->ptp_caps, &ts);
664 pr_debug("igb overflow check at %lld.%09lu\n",
665 (long long) ts.tv_sec, ts.tv_nsec);
667 schedule_delayed_work(&igb->ptp_overflow_work,
668 IGB_SYSTIM_OVERFLOW_PERIOD);
672 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
673 * @adapter: private network adapter structure
675 * This watchdog task is scheduled to detect error case where hardware has
676 * dropped an Rx packet that was timestamped when the ring is full. The
677 * particular error is rare but leaves the device in a state unable to timestamp
678 * any future packets.
680 void igb_ptp_rx_hang(struct igb_adapter *adapter)
682 struct e1000_hw *hw = &adapter->hw;
683 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
684 unsigned long rx_event;
686 if (hw->mac.type != e1000_82576)
689 /* If we don't have a valid timestamp in the registers, just update the
690 * timeout counter and exit
692 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
693 adapter->last_rx_ptp_check = jiffies;
697 /* Determine the most recent watchdog or rx_timestamp event */
698 rx_event = adapter->last_rx_ptp_check;
699 if (time_after(adapter->last_rx_timestamp, rx_event))
700 rx_event = adapter->last_rx_timestamp;
702 /* Only need to read the high RXSTMP register to clear the lock */
703 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
705 adapter->last_rx_ptp_check = jiffies;
706 adapter->rx_hwtstamp_cleared++;
707 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
712 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
713 * @adapter: Board private structure.
715 * If we were asked to do hardware stamping and such a time stamp is
716 * available, then it must have been for this skb here because we only
717 * allow only one such packet into the queue.
719 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
721 struct e1000_hw *hw = &adapter->hw;
722 struct skb_shared_hwtstamps shhwtstamps;
725 regval = rd32(E1000_TXSTMPL);
726 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
728 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
729 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
730 dev_kfree_skb_any(adapter->ptp_tx_skb);
731 adapter->ptp_tx_skb = NULL;
732 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
736 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
737 * @q_vector: Pointer to interrupt specific structure
738 * @va: Pointer to address containing Rx buffer
739 * @skb: Buffer containing timestamp and packet
741 * This function is meant to retrieve a timestamp from the first buffer of an
742 * incoming frame. The value is stored in little endian format starting on
745 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
749 __le64 *regval = (__le64 *)va;
751 /* The timestamp is recorded in little endian format.
753 * Field: Reserved Reserved SYSTIML SYSTIMH
755 igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
756 le64_to_cpu(regval[1]));
760 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
761 * @q_vector: Pointer to interrupt specific structure
762 * @skb: Buffer containing timestamp and packet
764 * This function is meant to retrieve a timestamp from the internal registers
765 * of the adapter and store it in the skb.
767 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
770 struct igb_adapter *adapter = q_vector->adapter;
771 struct e1000_hw *hw = &adapter->hw;
774 /* If this bit is set, then the RX registers contain the time stamp. No
775 * other packet will be time stamped until we read these registers, so
776 * read the registers to make them available again. Because only one
777 * packet can be time stamped at a time, we know that the register
778 * values must belong to this one here and therefore we don't need to
779 * compare any of the additional attributes stored for it.
781 * If nothing went wrong, then it should have a shared tx_flags that we
782 * can turn into a skb_shared_hwtstamps.
784 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
787 regval = rd32(E1000_RXSTMPL);
788 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
790 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
792 /* Update the last_rx_timestamp timer in order to enable watchdog check
793 * for error case of latched timestamp on a dropped packet.
795 adapter->last_rx_timestamp = jiffies;
799 * igb_ptp_get_ts_config - get hardware time stamping config
803 * Get the hwtstamp_config settings to return to the user. Rather than attempt
804 * to deconstruct the settings from the registers, just return a shadow copy
805 * of the last known settings.
807 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
809 struct igb_adapter *adapter = netdev_priv(netdev);
810 struct hwtstamp_config *config = &adapter->tstamp_config;
812 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
817 * igb_ptp_set_timestamp_mode - setup hardware for timestamping
818 * @adapter: networking device structure
819 * @config: hwtstamp configuration
821 * Outgoing time stamping can be enabled and disabled. Play nice and
822 * disable it when requested, although it shouldn't case any overhead
823 * when no packet needs it. At most one packet in the queue may be
824 * marked for time stamping, otherwise it would be impossible to tell
825 * for sure to which packet the hardware time stamp belongs.
827 * Incoming time stamping has to be configured via the hardware
828 * filters. Not all combinations are supported, in particular event
829 * type has to be specified. Matching the kind of event packet is
830 * not supported, with the exception of "all V2 events regardless of
833 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
834 struct hwtstamp_config *config)
836 struct e1000_hw *hw = &adapter->hw;
837 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
838 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
839 u32 tsync_rx_cfg = 0;
844 /* reserved for future extensions */
848 switch (config->tx_type) {
849 case HWTSTAMP_TX_OFF:
857 switch (config->rx_filter) {
858 case HWTSTAMP_FILTER_NONE:
861 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
862 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
863 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
866 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
867 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
868 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
871 case HWTSTAMP_FILTER_PTP_V2_EVENT:
872 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
873 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
874 case HWTSTAMP_FILTER_PTP_V2_SYNC:
875 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
876 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
877 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
878 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
879 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
880 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
881 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
885 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
886 case HWTSTAMP_FILTER_ALL:
887 /* 82576 cannot timestamp all packets, which it needs to do to
888 * support both V1 Sync and Delay_Req messages
890 if (hw->mac.type != e1000_82576) {
891 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
892 config->rx_filter = HWTSTAMP_FILTER_ALL;
897 config->rx_filter = HWTSTAMP_FILTER_NONE;
901 if (hw->mac.type == e1000_82575) {
902 if (tsync_rx_ctl | tsync_tx_ctl)
907 /* Per-packet timestamping only works if all packets are
908 * timestamped, so enable timestamping in all packets as
909 * long as one Rx filter was configured.
911 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
912 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
913 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
914 config->rx_filter = HWTSTAMP_FILTER_ALL;
918 if ((hw->mac.type == e1000_i210) ||
919 (hw->mac.type == e1000_i211)) {
920 regval = rd32(E1000_RXPBS);
921 regval |= E1000_RXPBS_CFG_TS_EN;
922 wr32(E1000_RXPBS, regval);
926 /* enable/disable TX */
927 regval = rd32(E1000_TSYNCTXCTL);
928 regval &= ~E1000_TSYNCTXCTL_ENABLED;
929 regval |= tsync_tx_ctl;
930 wr32(E1000_TSYNCTXCTL, regval);
932 /* enable/disable RX */
933 regval = rd32(E1000_TSYNCRXCTL);
934 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
935 regval |= tsync_rx_ctl;
936 wr32(E1000_TSYNCRXCTL, regval);
938 /* define which PTP packets are time stamped */
939 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
941 /* define ethertype filter for timestamped packets */
944 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
945 E1000_ETQF_1588 | /* enable timestamping */
946 ETH_P_1588)); /* 1588 eth protocol type */
948 wr32(E1000_ETQF(3), 0);
950 /* L4 Queue Filter[3]: filter by destination port and protocol */
952 u32 ftqf = (IPPROTO_UDP /* UDP */
953 | E1000_FTQF_VF_BP /* VF not compared */
954 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
955 | E1000_FTQF_MASK); /* mask all inputs */
956 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
958 wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
959 wr32(E1000_IMIREXT(3),
960 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
961 if (hw->mac.type == e1000_82576) {
962 /* enable source port check */
963 wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
964 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
966 wr32(E1000_FTQF(3), ftqf);
968 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
972 /* clear TX/RX time stamp registers, just to be sure */
973 regval = rd32(E1000_TXSTMPL);
974 regval = rd32(E1000_TXSTMPH);
975 regval = rd32(E1000_RXSTMPL);
976 regval = rd32(E1000_RXSTMPH);
982 * igb_ptp_set_ts_config - set hardware time stamping config
987 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
989 struct igb_adapter *adapter = netdev_priv(netdev);
990 struct hwtstamp_config config;
993 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
996 err = igb_ptp_set_timestamp_mode(adapter, &config);
1000 /* save these settings for future reference */
1001 memcpy(&adapter->tstamp_config, &config,
1002 sizeof(adapter->tstamp_config));
1004 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1008 void igb_ptp_init(struct igb_adapter *adapter)
1010 struct e1000_hw *hw = &adapter->hw;
1011 struct net_device *netdev = adapter->netdev;
1014 switch (hw->mac.type) {
1016 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1017 adapter->ptp_caps.owner = THIS_MODULE;
1018 adapter->ptp_caps.max_adj = 999999881;
1019 adapter->ptp_caps.n_ext_ts = 0;
1020 adapter->ptp_caps.pps = 0;
1021 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
1022 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1023 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1024 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1025 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1026 adapter->cc.read = igb_ptp_read_82576;
1027 adapter->cc.mask = CYCLECOUNTER_MASK(64);
1028 adapter->cc.mult = 1;
1029 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
1030 /* Dial the nominal frequency. */
1031 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1036 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1037 adapter->ptp_caps.owner = THIS_MODULE;
1038 adapter->ptp_caps.max_adj = 62499999;
1039 adapter->ptp_caps.n_ext_ts = 0;
1040 adapter->ptp_caps.pps = 0;
1041 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
1042 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1043 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1044 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1045 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1046 adapter->cc.read = igb_ptp_read_82580;
1047 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1048 adapter->cc.mult = 1;
1049 adapter->cc.shift = 0;
1050 /* Enable the timer functions by clearing bit 31. */
1051 wr32(E1000_TSAUXC, 0x0);
1055 for (i = 0; i < IGB_N_SDP; i++) {
1056 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1058 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1060 ppd->func = PTP_PF_NONE;
1062 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1063 adapter->ptp_caps.owner = THIS_MODULE;
1064 adapter->ptp_caps.max_adj = 62499999;
1065 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1066 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1067 adapter->ptp_caps.n_pins = IGB_N_SDP;
1068 adapter->ptp_caps.pps = 1;
1069 adapter->ptp_caps.pin_config = adapter->sdp_config;
1070 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
1071 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1072 adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210;
1073 adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1074 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1075 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1076 /* Enable the timer functions by clearing bit 31. */
1077 wr32(E1000_TSAUXC, 0x0);
1080 adapter->ptp_clock = NULL;
1086 spin_lock_init(&adapter->tmreg_lock);
1087 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1089 /* Initialize the clock and overflow work for devices that need it. */
1090 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1091 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1093 igb_ptp_settime_i210(&adapter->ptp_caps, &ts);
1095 timecounter_init(&adapter->tc, &adapter->cc,
1096 ktime_to_ns(ktime_get_real()));
1098 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1099 igb_ptp_overflow_check);
1101 schedule_delayed_work(&adapter->ptp_overflow_work,
1102 IGB_SYSTIM_OVERFLOW_PERIOD);
1105 /* Initialize the time sync interrupts for devices that support it. */
1106 if (hw->mac.type >= e1000_82580) {
1107 wr32(E1000_TSIM, TSYNC_INTERRUPTS);
1108 wr32(E1000_IMS, E1000_IMS_TS);
1111 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1112 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1114 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1115 &adapter->pdev->dev);
1116 if (IS_ERR(adapter->ptp_clock)) {
1117 adapter->ptp_clock = NULL;
1118 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1120 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1121 adapter->netdev->name);
1122 adapter->flags |= IGB_FLAG_PTP;
1127 * igb_ptp_stop - Disable PTP device and stop the overflow check.
1128 * @adapter: Board private structure.
1130 * This function stops the PTP support and cancels the delayed work.
1132 void igb_ptp_stop(struct igb_adapter *adapter)
1134 switch (adapter->hw.mac.type) {
1139 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1143 /* No delayed work to cancel. */
1149 cancel_work_sync(&adapter->ptp_tx_work);
1150 if (adapter->ptp_tx_skb) {
1151 dev_kfree_skb_any(adapter->ptp_tx_skb);
1152 adapter->ptp_tx_skb = NULL;
1153 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1156 if (adapter->ptp_clock) {
1157 ptp_clock_unregister(adapter->ptp_clock);
1158 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1159 adapter->netdev->name);
1160 adapter->flags &= ~IGB_FLAG_PTP;
1165 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1166 * @adapter: Board private structure.
1168 * This function handles the reset work required to re-enable the PTP device.
1170 void igb_ptp_reset(struct igb_adapter *adapter)
1172 struct e1000_hw *hw = &adapter->hw;
1173 unsigned long flags;
1175 if (!(adapter->flags & IGB_FLAG_PTP))
1178 /* reset the tstamp_config */
1179 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1181 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1183 switch (adapter->hw.mac.type) {
1185 /* Dial the nominal frequency. */
1186 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1193 wr32(E1000_TSAUXC, 0x0);
1194 wr32(E1000_TSSDP, 0x0);
1195 wr32(E1000_TSIM, TSYNC_INTERRUPTS);
1196 wr32(E1000_IMS, E1000_IMS_TS);
1199 /* No work to do. */
1203 /* Re-initialize the timer. */
1204 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1205 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1207 igb_ptp_write_i210(adapter, &ts);
1209 timecounter_init(&adapter->tc, &adapter->cc,
1210 ktime_to_ns(ktime_get_real()));
1213 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);