1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2014 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 #define E1000_DEV_ID_82571EB_COPPER 0x105E
31 #define E1000_DEV_ID_82571EB_FIBER 0x105F
32 #define E1000_DEV_ID_82571EB_SERDES 0x1060
33 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
34 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
35 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
36 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
37 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
38 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
39 #define E1000_DEV_ID_82572EI_COPPER 0x107D
40 #define E1000_DEV_ID_82572EI_FIBER 0x107E
41 #define E1000_DEV_ID_82572EI_SERDES 0x107F
42 #define E1000_DEV_ID_82572EI 0x10B9
43 #define E1000_DEV_ID_82573E 0x108B
44 #define E1000_DEV_ID_82573E_IAMT 0x108C
45 #define E1000_DEV_ID_82573L 0x109A
46 #define E1000_DEV_ID_82574L 0x10D3
47 #define E1000_DEV_ID_82574LA 0x10F6
48 #define E1000_DEV_ID_82583V 0x150C
49 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
50 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
51 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
52 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
53 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
54 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
55 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
56 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
57 #define E1000_DEV_ID_ICH8_IFE 0x104C
58 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
59 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
60 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
61 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
62 #define E1000_DEV_ID_ICH9_BM 0x10E5
63 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
64 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
65 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
66 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
67 #define E1000_DEV_ID_ICH9_IFE 0x10C0
68 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
69 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
70 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
71 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
72 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
73 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
74 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
75 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
76 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
77 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
78 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
79 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
80 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
81 #define E1000_DEV_ID_PCH2_LV_V 0x1503
82 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
83 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
84 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
85 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
86 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0
87 #define E1000_DEV_ID_PCH_I218_V2 0x15A1
88 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
89 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
90 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT PCH */
91 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */
92 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */
93 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */
95 #define E1000_REVISION_4 4
97 #define E1000_FUNC_1 1
99 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
100 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
102 enum e1000_mac_type {
118 enum e1000_media_type {
119 e1000_media_type_unknown = 0,
120 e1000_media_type_copper = 1,
121 e1000_media_type_fiber = 2,
122 e1000_media_type_internal_serdes = 3,
123 e1000_num_media_types
126 enum e1000_nvm_type {
127 e1000_nvm_unknown = 0,
129 e1000_nvm_eeprom_spi,
134 enum e1000_nvm_override {
135 e1000_nvm_override_none = 0,
136 e1000_nvm_override_spi_small,
137 e1000_nvm_override_spi_large
140 enum e1000_phy_type {
141 e1000_phy_unknown = 0,
156 enum e1000_bus_width {
157 e1000_bus_width_unknown = 0,
158 e1000_bus_width_pcie_x1,
159 e1000_bus_width_pcie_x2,
160 e1000_bus_width_pcie_x4 = 4,
161 e1000_bus_width_pcie_x8 = 8,
164 e1000_bus_width_reserved
167 enum e1000_1000t_rx_status {
168 e1000_1000t_rx_status_not_ok = 0,
169 e1000_1000t_rx_status_ok,
170 e1000_1000t_rx_status_undefined = 0xFF
173 enum e1000_rev_polarity {
174 e1000_rev_polarity_normal = 0,
175 e1000_rev_polarity_reversed,
176 e1000_rev_polarity_undefined = 0xFF
184 e1000_fc_default = 0xFF
188 e1000_ms_hw_default = 0,
189 e1000_ms_force_master,
190 e1000_ms_force_slave,
194 enum e1000_smart_speed {
195 e1000_smart_speed_default = 0,
196 e1000_smart_speed_on,
197 e1000_smart_speed_off
200 enum e1000_serdes_link_state {
201 e1000_serdes_link_down = 0,
202 e1000_serdes_link_autoneg_progress,
203 e1000_serdes_link_autoneg_complete,
204 e1000_serdes_link_forced_up
207 /* Receive Descriptor - Extended */
208 union e1000_rx_desc_extended {
215 __le32 mrq; /* Multiple Rx Queues */
217 __le32 rss; /* RSS Hash */
219 __le16 ip_id; /* IP id */
220 __le16 csum; /* Packet Checksum */
225 __le32 status_error; /* ext status/error */
227 __le16 vlan; /* VLAN tag */
229 } wb; /* writeback */
232 #define MAX_PS_BUFFERS 4
234 /* Number of packet split data buffers (not including the header buffer) */
235 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
237 /* Receive Descriptor - Packet Split */
238 union e1000_rx_desc_packet_split {
240 /* one buffer for protocol header(s), three data buffers */
241 __le64 buffer_addr[MAX_PS_BUFFERS];
245 __le32 mrq; /* Multiple Rx Queues */
247 __le32 rss; /* RSS Hash */
249 __le16 ip_id; /* IP id */
250 __le16 csum; /* Packet Checksum */
255 __le32 status_error; /* ext status/error */
256 __le16 length0; /* length of buffer 0 */
257 __le16 vlan; /* VLAN tag */
260 __le16 header_status;
261 /* length of buffers 1-3 */
262 __le16 length[PS_PAGE_BUFFERS];
265 } wb; /* writeback */
268 /* Transmit Descriptor */
269 struct e1000_tx_desc {
270 __le64 buffer_addr; /* Address of the descriptor's data buffer */
274 __le16 length; /* Data buffer length */
275 u8 cso; /* Checksum offset */
276 u8 cmd; /* Descriptor control */
282 u8 status; /* Descriptor status */
283 u8 css; /* Checksum start */
289 /* Offload Context Descriptor */
290 struct e1000_context_desc {
294 u8 ipcss; /* IP checksum start */
295 u8 ipcso; /* IP checksum offset */
296 __le16 ipcse; /* IP checksum end */
302 u8 tucss; /* TCP checksum start */
303 u8 tucso; /* TCP checksum offset */
304 __le16 tucse; /* TCP checksum end */
307 __le32 cmd_and_length;
311 u8 status; /* Descriptor status */
312 u8 hdr_len; /* Header length */
313 __le16 mss; /* Maximum segment size */
318 /* Offload data descriptor */
319 struct e1000_data_desc {
320 __le64 buffer_addr; /* Address of the descriptor's buffer address */
324 __le16 length; /* Data buffer length */
332 u8 status; /* Descriptor status */
333 u8 popts; /* Packet Options */
339 /* Statistics counters collected by the MAC */
340 struct e1000_hw_stats {
406 struct e1000_phy_stats {
411 struct e1000_host_mng_dhcp_cookie {
422 /* Host Interface "Rev 1" */
423 struct e1000_host_command_header {
430 #define E1000_HI_MAX_DATA_LENGTH 252
431 struct e1000_host_command_info {
432 struct e1000_host_command_header command_header;
433 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
436 /* Host Interface "Rev 2" */
437 struct e1000_host_mng_command_header {
445 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
446 struct e1000_host_mng_command_info {
447 struct e1000_host_mng_command_header command_header;
448 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
456 /* Function pointers for the MAC. */
457 struct e1000_mac_operations {
458 s32 (*id_led_init)(struct e1000_hw *);
459 s32 (*blink_led)(struct e1000_hw *);
460 bool (*check_mng_mode)(struct e1000_hw *);
461 s32 (*check_for_link)(struct e1000_hw *);
462 s32 (*cleanup_led)(struct e1000_hw *);
463 void (*clear_hw_cntrs)(struct e1000_hw *);
464 void (*clear_vfta)(struct e1000_hw *);
465 s32 (*get_bus_info)(struct e1000_hw *);
466 void (*set_lan_id)(struct e1000_hw *);
467 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
468 s32 (*led_on)(struct e1000_hw *);
469 s32 (*led_off)(struct e1000_hw *);
470 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
471 s32 (*reset_hw)(struct e1000_hw *);
472 s32 (*init_hw)(struct e1000_hw *);
473 s32 (*setup_link)(struct e1000_hw *);
474 s32 (*setup_physical_interface)(struct e1000_hw *);
475 s32 (*setup_led)(struct e1000_hw *);
476 void (*write_vfta)(struct e1000_hw *, u32, u32);
477 void (*config_collision_dist)(struct e1000_hw *);
478 int (*rar_set)(struct e1000_hw *, u8 *, u32);
479 s32 (*read_mac_addr)(struct e1000_hw *);
480 u32 (*rar_get_count)(struct e1000_hw *);
483 /* When to use various PHY register access functions:
486 * Function Does Does When to use
487 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
488 * X_reg L,P,A n/a for simple PHY reg accesses
489 * X_reg_locked P,A L for multiple accesses of different regs
491 * X_reg_page A L,P for multiple accesses of different regs
494 * Where X=[read|write], L=locking, P=sets page, A=register access
497 struct e1000_phy_operations {
498 s32 (*acquire)(struct e1000_hw *);
499 s32 (*cfg_on_link_up)(struct e1000_hw *);
500 s32 (*check_polarity)(struct e1000_hw *);
501 s32 (*check_reset_block)(struct e1000_hw *);
502 s32 (*commit)(struct e1000_hw *);
503 s32 (*force_speed_duplex)(struct e1000_hw *);
504 s32 (*get_cfg_done)(struct e1000_hw *hw);
505 s32 (*get_cable_length)(struct e1000_hw *);
506 s32 (*get_info)(struct e1000_hw *);
507 s32 (*set_page)(struct e1000_hw *, u16);
508 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
509 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
510 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
511 void (*release)(struct e1000_hw *);
512 s32 (*reset)(struct e1000_hw *);
513 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
514 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
515 s32 (*write_reg)(struct e1000_hw *, u32, u16);
516 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
517 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
518 void (*power_up)(struct e1000_hw *);
519 void (*power_down)(struct e1000_hw *);
522 /* Function pointers for the NVM. */
523 struct e1000_nvm_operations {
524 s32 (*acquire)(struct e1000_hw *);
525 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
526 void (*release)(struct e1000_hw *);
527 void (*reload)(struct e1000_hw *);
528 s32 (*update)(struct e1000_hw *);
529 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
530 s32 (*validate)(struct e1000_hw *);
531 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
534 struct e1000_mac_info {
535 struct e1000_mac_operations ops;
537 u8 perm_addr[ETH_ALEN];
539 enum e1000_mac_type type;
556 /* Maximum size of the MTA register table in all supported adapters */
557 #define MAX_MTA_REG 128
558 u32 mta_shadow[MAX_MTA_REG];
561 u8 forced_speed_duplex;
565 bool arc_subsystem_valid;
568 bool get_link_status;
570 bool serdes_has_link;
571 bool tx_pkt_filtering;
572 enum e1000_serdes_link_state serdes_link_state;
575 struct e1000_phy_info {
576 struct e1000_phy_operations ops;
578 enum e1000_phy_type type;
580 enum e1000_1000t_rx_status local_rx;
581 enum e1000_1000t_rx_status remote_rx;
582 enum e1000_ms_type ms_type;
583 enum e1000_ms_type original_ms_type;
584 enum e1000_rev_polarity cable_polarity;
585 enum e1000_smart_speed smart_speed;
589 u32 reset_delay_us; /* in usec */
592 enum e1000_media_type media_type;
594 u16 autoneg_advertised;
597 u16 max_cable_length;
598 u16 min_cable_length;
602 bool disable_polarity_correction;
604 bool polarity_correction;
605 bool speed_downgraded;
606 bool autoneg_wait_to_complete;
609 struct e1000_nvm_info {
610 struct e1000_nvm_operations ops;
612 enum e1000_nvm_type type;
613 enum e1000_nvm_override override;
625 struct e1000_bus_info {
626 enum e1000_bus_width width;
631 struct e1000_fc_info {
632 u32 high_water; /* Flow control high-water mark */
633 u32 low_water; /* Flow control low-water mark */
634 u16 pause_time; /* Flow control pause timer */
635 u16 refresh_time; /* Flow control refresh timer */
636 bool send_xon; /* Flow control send XON */
637 bool strict_ieee; /* Strict IEEE mode */
638 enum e1000_fc_mode current_mode; /* FC mode in effect */
639 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
642 struct e1000_dev_spec_82571 {
647 struct e1000_dev_spec_80003es2lan {
651 struct e1000_shadow_ram {
656 #define E1000_ICH8_SHADOW_RAM_WORDS 2048
658 /* I218 PHY Ultra Low Power (ULP) states */
659 enum e1000_ulp_state {
660 e1000_ulp_state_unknown,
665 struct e1000_dev_spec_ich8lan {
666 bool kmrn_lock_loss_workaround_enabled;
667 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
671 enum e1000_ulp_state ulp_state;
675 struct e1000_adapter *adapter;
677 void __iomem *hw_addr;
678 void __iomem *flash_address;
680 struct e1000_mac_info mac;
681 struct e1000_fc_info fc;
682 struct e1000_phy_info phy;
683 struct e1000_nvm_info nvm;
684 struct e1000_bus_info bus;
685 struct e1000_host_mng_dhcp_cookie mng_cookie;
688 struct e1000_dev_spec_82571 e82571;
689 struct e1000_dev_spec_80003es2lan e80003es2lan;
690 struct e1000_dev_spec_ich8lan ich8lan;
695 #include "80003es2lan.h"