2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
36 #define DRIVER_NAME "sdhci"
38 #define DBG(f, x...) \
39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43 #define SDHCI_USE_LEDS_CLASS
46 #define MAX_TUNING_LOOP 40
48 static unsigned int debug_quirks = 0;
49 static unsigned int debug_quirks2;
51 static void sdhci_finish_data(struct sdhci_host *);
53 static void sdhci_finish_command(struct sdhci_host *);
54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55 static void sdhci_tuning_timer(unsigned long data);
56 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
57 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
58 struct mmc_data *data,
59 struct sdhci_host_next *next);
60 static int sdhci_do_get_cd(struct sdhci_host *host);
63 static int sdhci_runtime_pm_get(struct sdhci_host *host);
64 static int sdhci_runtime_pm_put(struct sdhci_host *host);
65 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
66 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
68 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
72 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
76 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
79 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
84 static void sdhci_dumpregs(struct sdhci_host *host)
86 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
87 mmc_hostname(host->mmc));
89 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
90 sdhci_readl(host, SDHCI_DMA_ADDRESS),
91 sdhci_readw(host, SDHCI_HOST_VERSION));
92 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
93 sdhci_readw(host, SDHCI_BLOCK_SIZE),
94 sdhci_readw(host, SDHCI_BLOCK_COUNT));
95 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
96 sdhci_readl(host, SDHCI_ARGUMENT),
97 sdhci_readw(host, SDHCI_TRANSFER_MODE));
98 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
99 sdhci_readl(host, SDHCI_PRESENT_STATE),
100 sdhci_readb(host, SDHCI_HOST_CONTROL));
101 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
102 sdhci_readb(host, SDHCI_POWER_CONTROL),
103 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
104 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
105 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
106 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
107 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
108 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
109 sdhci_readl(host, SDHCI_INT_STATUS));
110 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
111 sdhci_readl(host, SDHCI_INT_ENABLE),
112 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
113 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
114 sdhci_readw(host, SDHCI_ACMD12_ERR),
115 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
116 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
117 sdhci_readl(host, SDHCI_CAPABILITIES),
118 sdhci_readl(host, SDHCI_CAPABILITIES_1));
119 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
120 sdhci_readw(host, SDHCI_COMMAND),
121 sdhci_readl(host, SDHCI_MAX_CURRENT));
122 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
123 sdhci_readw(host, SDHCI_HOST_CONTROL2));
125 if (host->flags & SDHCI_USE_ADMA) {
126 if (host->flags & SDHCI_USE_64_BIT_DMA)
127 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
128 readl(host->ioaddr + SDHCI_ADMA_ERROR),
129 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
130 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
132 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
133 readl(host->ioaddr + SDHCI_ADMA_ERROR),
134 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
137 pr_debug(DRIVER_NAME ": ===========================================\n");
140 /*****************************************************************************\
142 * Low level functions *
144 \*****************************************************************************/
146 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
150 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
151 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
155 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
158 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
159 SDHCI_INT_CARD_INSERT;
161 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
164 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
165 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
168 static void sdhci_enable_card_detection(struct sdhci_host *host)
170 sdhci_set_card_detection(host, true);
173 static void sdhci_disable_card_detection(struct sdhci_host *host)
175 sdhci_set_card_detection(host, false);
178 void sdhci_reset(struct sdhci_host *host, u8 mask)
180 unsigned long timeout;
182 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
184 if (mask & SDHCI_RESET_ALL) {
186 /* Reset-all turns off SD Bus Power */
187 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
188 sdhci_runtime_pm_bus_off(host);
191 /* Wait max 100 ms */
194 /* hw clears the bit when it's done */
195 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
197 pr_err("%s: Reset 0x%x never completed.\n",
198 mmc_hostname(host->mmc), (int)mask);
199 sdhci_dumpregs(host);
206 EXPORT_SYMBOL_GPL(sdhci_reset);
208 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
210 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
211 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
216 host->ops->reset(host, mask);
218 if (mask & SDHCI_RESET_ALL) {
219 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
220 if (host->ops->enable_dma)
221 host->ops->enable_dma(host);
224 /* Resetting the controller clears many */
225 host->preset_enabled = false;
229 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
231 static void sdhci_init(struct sdhci_host *host, int soft)
234 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
236 sdhci_do_reset(host, SDHCI_RESET_ALL);
238 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
239 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
240 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
241 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
244 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
245 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
248 /* force clock reconfiguration */
250 sdhci_set_ios(host->mmc, &host->mmc->ios);
254 static void sdhci_reinit(struct sdhci_host *host)
258 * Retuning stuffs are affected by different cards inserted and only
259 * applicable to UHS-I cards. So reset these fields to their initial
260 * value when card is removed.
262 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
263 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
265 del_timer_sync(&host->tuning_timer);
266 host->flags &= ~SDHCI_NEEDS_RETUNING;
268 sdhci_enable_card_detection(host);
271 static void sdhci_activate_led(struct sdhci_host *host)
275 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
276 ctrl |= SDHCI_CTRL_LED;
277 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
280 static void sdhci_deactivate_led(struct sdhci_host *host)
284 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
285 ctrl &= ~SDHCI_CTRL_LED;
286 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
289 #ifdef SDHCI_USE_LEDS_CLASS
290 static void sdhci_led_control(struct led_classdev *led,
291 enum led_brightness brightness)
293 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
296 spin_lock_irqsave(&host->lock, flags);
298 if (host->runtime_suspended)
301 if (brightness == LED_OFF)
302 sdhci_deactivate_led(host);
304 sdhci_activate_led(host);
306 spin_unlock_irqrestore(&host->lock, flags);
310 /*****************************************************************************\
314 \*****************************************************************************/
316 static void sdhci_read_block_pio(struct sdhci_host *host)
319 size_t blksize, len, chunk;
320 u32 uninitialized_var(scratch);
323 DBG("PIO reading\n");
325 blksize = host->data->blksz;
328 local_irq_save(flags);
331 if (!sg_miter_next(&host->sg_miter))
334 len = min(host->sg_miter.length, blksize);
337 host->sg_miter.consumed = len;
339 buf = host->sg_miter.addr;
343 scratch = sdhci_readl(host, SDHCI_BUFFER);
347 *buf = scratch & 0xFF;
356 sg_miter_stop(&host->sg_miter);
358 local_irq_restore(flags);
361 static void sdhci_write_block_pio(struct sdhci_host *host)
364 size_t blksize, len, chunk;
368 DBG("PIO writing\n");
370 blksize = host->data->blksz;
374 local_irq_save(flags);
377 if (!sg_miter_next(&host->sg_miter))
380 len = min(host->sg_miter.length, blksize);
383 host->sg_miter.consumed = len;
385 buf = host->sg_miter.addr;
388 scratch |= (u32)*buf << (chunk * 8);
394 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
395 sdhci_writel(host, scratch, SDHCI_BUFFER);
402 sg_miter_stop(&host->sg_miter);
404 local_irq_restore(flags);
407 static void sdhci_transfer_pio(struct sdhci_host *host)
413 if (host->blocks == 0)
416 if (host->data->flags & MMC_DATA_READ)
417 mask = SDHCI_DATA_AVAILABLE;
419 mask = SDHCI_SPACE_AVAILABLE;
422 * Some controllers (JMicron JMB38x) mess up the buffer bits
423 * for transfers < 4 bytes. As long as it is just one block,
424 * we can ignore the bits.
426 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
427 (host->data->blocks == 1))
430 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
431 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
434 if (host->data->flags & MMC_DATA_READ)
435 sdhci_read_block_pio(host);
437 sdhci_write_block_pio(host);
440 if (host->blocks == 0)
444 DBG("PIO transfer complete.\n");
447 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
449 local_irq_save(*flags);
450 return kmap_atomic(sg_page(sg)) + sg->offset;
453 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
455 kunmap_atomic(buffer);
456 local_irq_restore(*flags);
459 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
460 dma_addr_t addr, int len, unsigned cmd)
462 struct sdhci_adma2_64_desc *dma_desc = desc;
464 /* 32-bit and 64-bit descriptors have these members in same position */
465 dma_desc->cmd = cpu_to_le16(cmd);
466 dma_desc->len = cpu_to_le16(len);
467 dma_desc->addr_lo = cpu_to_le32((u32)addr);
469 if (host->flags & SDHCI_USE_64_BIT_DMA)
470 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
473 static void sdhci_adma_mark_end(void *desc)
475 struct sdhci_adma2_64_desc *dma_desc = desc;
477 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
478 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
481 static int sdhci_adma_table_pre(struct sdhci_host *host,
482 struct mmc_data *data)
489 dma_addr_t align_addr;
492 struct scatterlist *sg;
498 * The spec does not specify endianness of descriptor table.
499 * We currently guess that it is LE.
502 if (data->flags & MMC_DATA_READ)
503 direction = DMA_FROM_DEVICE;
505 direction = DMA_TO_DEVICE;
507 host->align_addr = dma_map_single(mmc_dev(host->mmc),
508 host->align_buffer, host->align_buffer_sz, direction);
509 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
511 BUG_ON(host->align_addr & host->align_mask);
513 host->sg_count = sdhci_pre_dma_transfer(host, data, NULL);
514 if (host->sg_count < 0)
517 desc = host->adma_table;
518 align = host->align_buffer;
520 align_addr = host->align_addr;
522 for_each_sg(data->sg, sg, host->sg_count, i) {
523 addr = sg_dma_address(sg);
524 len = sg_dma_len(sg);
527 * The SDHCI specification states that ADMA
528 * addresses must be 32-bit aligned. If they
529 * aren't, then we use a bounce buffer for
530 * the (up to three) bytes that screw up the
533 offset = (host->align_sz - (addr & host->align_mask)) &
536 if (data->flags & MMC_DATA_WRITE) {
537 buffer = sdhci_kmap_atomic(sg, &flags);
538 memcpy(align, buffer, offset);
539 sdhci_kunmap_atomic(buffer, &flags);
543 sdhci_adma_write_desc(host, desc, align_addr, offset,
546 BUG_ON(offset > 65536);
548 align += host->align_sz;
549 align_addr += host->align_sz;
551 desc += host->desc_sz;
560 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
561 desc += host->desc_sz;
564 * If this triggers then we have a calculation bug
567 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
570 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
572 * Mark the last descriptor as the terminating descriptor
574 if (desc != host->adma_table) {
575 desc -= host->desc_sz;
576 sdhci_adma_mark_end(desc);
580 * Add a terminating entry.
583 /* nop, end, valid */
584 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
588 * Resync align buffer as we might have changed it.
590 if (data->flags & MMC_DATA_WRITE) {
591 dma_sync_single_for_device(mmc_dev(host->mmc),
592 host->align_addr, host->align_buffer_sz, direction);
598 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
599 host->align_buffer_sz, direction);
604 static void sdhci_adma_table_post(struct sdhci_host *host,
605 struct mmc_data *data)
609 struct scatterlist *sg;
616 if (data->flags & MMC_DATA_READ)
617 direction = DMA_FROM_DEVICE;
619 direction = DMA_TO_DEVICE;
621 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
622 host->align_buffer_sz, direction);
624 /* Do a quick scan of the SG list for any unaligned mappings */
625 has_unaligned = false;
626 for_each_sg(data->sg, sg, host->sg_count, i)
627 if (sg_dma_address(sg) & host->align_mask) {
628 has_unaligned = true;
632 if (has_unaligned && data->flags & MMC_DATA_READ) {
633 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
634 data->sg_len, direction);
636 align = host->align_buffer;
638 for_each_sg(data->sg, sg, host->sg_count, i) {
639 if (sg_dma_address(sg) & host->align_mask) {
640 size = host->align_sz -
641 (sg_dma_address(sg) & host->align_mask);
643 buffer = sdhci_kmap_atomic(sg, &flags);
644 memcpy(buffer, align, size);
645 sdhci_kunmap_atomic(buffer, &flags);
647 align += host->align_sz;
652 if (!data->host_cookie)
653 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
654 data->sg_len, direction);
657 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
660 struct mmc_data *data = cmd->data;
661 unsigned target_timeout, current_timeout;
664 * If the host controller provides us with an incorrect timeout
665 * value, just skip the check and use 0xE. The hardware may take
666 * longer to time out, but that's much better than having a too-short
669 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
672 /* Unspecified timeout, assume max */
673 if (!data && !cmd->busy_timeout)
678 target_timeout = cmd->busy_timeout * 1000;
680 target_timeout = data->timeout_ns / 1000;
682 target_timeout += data->timeout_clks / host->clock;
686 * Figure out needed cycles.
687 * We do this in steps in order to fit inside a 32 bit int.
688 * The first step is the minimum timeout, which will have a
689 * minimum resolution of 6 bits:
690 * (1) 2^13*1000 > 2^22,
691 * (2) host->timeout_clk < 2^16
696 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
697 while (current_timeout < target_timeout) {
699 current_timeout <<= 1;
705 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
706 mmc_hostname(host->mmc), count, cmd->opcode);
713 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
715 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
716 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
718 if (host->flags & SDHCI_REQ_USE_DMA)
719 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
721 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
723 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
724 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
727 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
731 if (host->ops->set_timeout) {
732 host->ops->set_timeout(host, cmd);
734 count = sdhci_calc_timeout(host, cmd);
735 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
739 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
742 struct mmc_data *data = cmd->data;
747 if (data || (cmd->flags & MMC_RSP_BUSY))
748 sdhci_set_timeout(host, cmd);
754 BUG_ON(data->blksz * data->blocks > 524288);
755 BUG_ON(data->blksz > host->mmc->max_blk_size);
756 BUG_ON(data->blocks > 65535);
759 host->data_early = 0;
760 host->data->bytes_xfered = 0;
762 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
763 host->flags |= SDHCI_REQ_USE_DMA;
766 * FIXME: This doesn't account for merging when mapping the
769 if (host->flags & SDHCI_REQ_USE_DMA) {
771 struct scatterlist *sg;
774 if (host->flags & SDHCI_USE_ADMA) {
775 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
778 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
782 if (unlikely(broken)) {
783 for_each_sg(data->sg, sg, data->sg_len, i) {
784 if (sg->length & 0x3) {
785 DBG("Reverting to PIO because of "
786 "transfer size (%d)\n",
788 host->flags &= ~SDHCI_REQ_USE_DMA;
796 * The assumption here being that alignment is the same after
797 * translation to device address space.
799 if (host->flags & SDHCI_REQ_USE_DMA) {
801 struct scatterlist *sg;
804 if (host->flags & SDHCI_USE_ADMA) {
806 * As we use 3 byte chunks to work around
807 * alignment problems, we need to check this
810 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
813 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
817 if (unlikely(broken)) {
818 for_each_sg(data->sg, sg, data->sg_len, i) {
819 if (sg->offset & 0x3) {
820 DBG("Reverting to PIO because of "
822 host->flags &= ~SDHCI_REQ_USE_DMA;
829 if (host->flags & SDHCI_REQ_USE_DMA) {
830 if (host->flags & SDHCI_USE_ADMA) {
831 ret = sdhci_adma_table_pre(host, data);
834 * This only happens when someone fed
835 * us an invalid request.
838 host->flags &= ~SDHCI_REQ_USE_DMA;
840 sdhci_writel(host, host->adma_addr,
842 if (host->flags & SDHCI_USE_64_BIT_DMA)
844 (u64)host->adma_addr >> 32,
845 SDHCI_ADMA_ADDRESS_HI);
850 sg_cnt = sdhci_pre_dma_transfer(host, data, NULL);
853 * This only happens when someone fed
854 * us an invalid request.
857 host->flags &= ~SDHCI_REQ_USE_DMA;
859 WARN_ON(sg_cnt != 1);
860 sdhci_writel(host, sg_dma_address(data->sg),
867 * Always adjust the DMA selection as some controllers
868 * (e.g. JMicron) can't do PIO properly when the selection
871 if (host->version >= SDHCI_SPEC_200) {
872 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
873 ctrl &= ~SDHCI_CTRL_DMA_MASK;
874 if ((host->flags & SDHCI_REQ_USE_DMA) &&
875 (host->flags & SDHCI_USE_ADMA)) {
876 if (host->flags & SDHCI_USE_64_BIT_DMA)
877 ctrl |= SDHCI_CTRL_ADMA64;
879 ctrl |= SDHCI_CTRL_ADMA32;
881 ctrl |= SDHCI_CTRL_SDMA;
883 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
886 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
889 flags = SG_MITER_ATOMIC;
890 if (host->data->flags & MMC_DATA_READ)
891 flags |= SG_MITER_TO_SG;
893 flags |= SG_MITER_FROM_SG;
894 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
895 host->blocks = data->blocks;
898 sdhci_set_transfer_irqs(host);
900 /* Set the DMA boundary value and block size */
901 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
902 data->blksz), SDHCI_BLOCK_SIZE);
903 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
906 static void sdhci_set_transfer_mode(struct sdhci_host *host,
907 struct mmc_command *cmd)
910 struct mmc_data *data = cmd->data;
914 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
915 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
917 /* clear Auto CMD settings for no data CMDs */
918 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
919 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
920 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
925 WARN_ON(!host->data);
927 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
928 mode = SDHCI_TRNS_BLK_CNT_EN;
930 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
931 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
933 * If we are sending CMD23, CMD12 never gets sent
934 * on successful completion (so no Auto-CMD12).
936 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
937 (cmd->opcode != SD_IO_RW_EXTENDED))
938 mode |= SDHCI_TRNS_AUTO_CMD12;
939 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
940 mode |= SDHCI_TRNS_AUTO_CMD23;
941 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
945 if (data->flags & MMC_DATA_READ)
946 mode |= SDHCI_TRNS_READ;
947 if (host->flags & SDHCI_REQ_USE_DMA)
948 mode |= SDHCI_TRNS_DMA;
950 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
953 static void sdhci_finish_data(struct sdhci_host *host)
955 struct mmc_data *data;
962 if (host->flags & SDHCI_REQ_USE_DMA) {
963 if (host->flags & SDHCI_USE_ADMA)
964 sdhci_adma_table_post(host, data);
966 if (!data->host_cookie)
967 dma_unmap_sg(mmc_dev(host->mmc),
968 data->sg, data->sg_len,
969 (data->flags & MMC_DATA_READ) ?
970 DMA_FROM_DEVICE : DMA_TO_DEVICE);
975 * The specification states that the block count register must
976 * be updated, but it does not specify at what point in the
977 * data flow. That makes the register entirely useless to read
978 * back so we have to assume that nothing made it to the card
979 * in the event of an error.
982 data->bytes_xfered = 0;
984 data->bytes_xfered = data->blksz * data->blocks;
987 * Need to send CMD12 if -
988 * a) open-ended multiblock transfer (no CMD23)
989 * b) error in multiblock transfer
996 * The controller needs a reset of internal state machines
997 * upon error conditions.
1000 sdhci_do_reset(host, SDHCI_RESET_CMD);
1001 sdhci_do_reset(host, SDHCI_RESET_DATA);
1004 sdhci_send_command(host, data->stop);
1006 tasklet_schedule(&host->finish_tasklet);
1009 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1013 unsigned long timeout;
1017 /* Wait max 10 ms */
1020 mask = SDHCI_CMD_INHIBIT;
1021 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1022 mask |= SDHCI_DATA_INHIBIT;
1024 /* We shouldn't wait for data inihibit for stop commands, even
1025 though they might use busy signaling */
1026 if (host->mrq->data && (cmd == host->mrq->data->stop))
1027 mask &= ~SDHCI_DATA_INHIBIT;
1029 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1031 pr_err("%s: Controller never released "
1032 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1033 sdhci_dumpregs(host);
1035 tasklet_schedule(&host->finish_tasklet);
1043 if (!cmd->data && cmd->busy_timeout > 9000)
1044 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1047 mod_timer(&host->timer, timeout);
1050 host->busy_handle = 0;
1052 sdhci_prepare_data(host, cmd);
1054 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1056 sdhci_set_transfer_mode(host, cmd);
1058 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1059 pr_err("%s: Unsupported response type!\n",
1060 mmc_hostname(host->mmc));
1061 cmd->error = -EINVAL;
1062 tasklet_schedule(&host->finish_tasklet);
1066 if (!(cmd->flags & MMC_RSP_PRESENT))
1067 flags = SDHCI_CMD_RESP_NONE;
1068 else if (cmd->flags & MMC_RSP_136)
1069 flags = SDHCI_CMD_RESP_LONG;
1070 else if (cmd->flags & MMC_RSP_BUSY)
1071 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1073 flags = SDHCI_CMD_RESP_SHORT;
1075 if (cmd->flags & MMC_RSP_CRC)
1076 flags |= SDHCI_CMD_CRC;
1077 if (cmd->flags & MMC_RSP_OPCODE)
1078 flags |= SDHCI_CMD_INDEX;
1080 /* CMD19 is special in that the Data Present Select should be set */
1081 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1082 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1083 flags |= SDHCI_CMD_DATA;
1085 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1087 EXPORT_SYMBOL_GPL(sdhci_send_command);
1089 static void sdhci_finish_command(struct sdhci_host *host)
1093 BUG_ON(host->cmd == NULL);
1095 if (host->cmd->flags & MMC_RSP_PRESENT) {
1096 if (host->cmd->flags & MMC_RSP_136) {
1097 /* CRC is stripped so we need to do some shifting. */
1098 for (i = 0;i < 4;i++) {
1099 host->cmd->resp[i] = sdhci_readl(host,
1100 SDHCI_RESPONSE + (3-i)*4) << 8;
1102 host->cmd->resp[i] |=
1104 SDHCI_RESPONSE + (3-i)*4-1);
1107 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1111 host->cmd->error = 0;
1113 /* Finished CMD23, now send actual command. */
1114 if (host->cmd == host->mrq->sbc) {
1116 sdhci_send_command(host, host->mrq->cmd);
1119 /* Processed actual command. */
1120 if (host->data && host->data_early)
1121 sdhci_finish_data(host);
1123 if (!host->cmd->data)
1124 tasklet_schedule(&host->finish_tasklet);
1130 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1134 switch (host->timing) {
1135 case MMC_TIMING_UHS_SDR12:
1136 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1138 case MMC_TIMING_UHS_SDR25:
1139 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1141 case MMC_TIMING_UHS_SDR50:
1142 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1144 case MMC_TIMING_UHS_SDR104:
1145 case MMC_TIMING_MMC_HS200:
1146 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1148 case MMC_TIMING_UHS_DDR50:
1149 case MMC_TIMING_MMC_DDR52:
1150 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1152 case MMC_TIMING_MMC_HS400:
1153 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1156 pr_warn("%s: Invalid UHS-I mode selected\n",
1157 mmc_hostname(host->mmc));
1158 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1164 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1166 int div = 0; /* Initialized for compiler warning */
1167 int real_div = div, clk_mul = 1;
1169 unsigned long timeout;
1171 host->mmc->actual_clock = 0;
1173 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1178 if (host->version >= SDHCI_SPEC_300) {
1179 if (host->preset_enabled) {
1182 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1183 pre_val = sdhci_get_preset_value(host);
1184 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1185 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1186 if (host->clk_mul &&
1187 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1188 clk = SDHCI_PROG_CLOCK_MODE;
1190 clk_mul = host->clk_mul;
1192 real_div = max_t(int, 1, div << 1);
1198 * Check if the Host Controller supports Programmable Clock
1201 if (host->clk_mul) {
1202 for (div = 1; div <= 1024; div++) {
1203 if ((host->max_clk * host->clk_mul / div)
1208 * Set Programmable Clock Mode in the Clock
1211 clk = SDHCI_PROG_CLOCK_MODE;
1213 clk_mul = host->clk_mul;
1216 /* Version 3.00 divisors must be a multiple of 2. */
1217 if (host->max_clk <= clock)
1220 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1222 if ((host->max_clk / div) <= clock)
1230 /* Version 2.00 divisors must be a power of 2. */
1231 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1232 if ((host->max_clk / div) <= clock)
1241 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1242 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1243 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1244 << SDHCI_DIVIDER_HI_SHIFT;
1245 clk |= SDHCI_CLOCK_INT_EN;
1246 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1248 /* Wait max 20 ms */
1250 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1251 & SDHCI_CLOCK_INT_STABLE)) {
1253 pr_err("%s: Internal clock never "
1254 "stabilised.\n", mmc_hostname(host->mmc));
1255 sdhci_dumpregs(host);
1262 clk |= SDHCI_CLOCK_CARD_EN;
1263 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1265 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1267 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1270 struct mmc_host *mmc = host->mmc;
1273 if (!IS_ERR(mmc->supply.vmmc)) {
1274 spin_unlock_irq(&host->lock);
1275 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1276 spin_lock_irq(&host->lock);
1278 if (mode != MMC_POWER_OFF)
1279 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1281 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1286 if (mode != MMC_POWER_OFF) {
1288 case MMC_VDD_165_195:
1289 pwr = SDHCI_POWER_180;
1293 pwr = SDHCI_POWER_300;
1297 pwr = SDHCI_POWER_330;
1304 if (host->pwr == pwr)
1310 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1311 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1312 sdhci_runtime_pm_bus_off(host);
1316 * Spec says that we should clear the power reg before setting
1317 * a new value. Some controllers don't seem to like this though.
1319 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1320 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1323 * At least the Marvell CaFe chip gets confused if we set the
1324 * voltage and set turn on power at the same time, so set the
1327 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1328 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1330 pwr |= SDHCI_POWER_ON;
1332 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1334 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1335 sdhci_runtime_pm_bus_on(host);
1338 * Some controllers need an extra 10ms delay of 10ms before
1339 * they can apply clock after applying power
1341 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1346 /*****************************************************************************\
1350 \*****************************************************************************/
1352 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1354 struct sdhci_host *host;
1356 unsigned long flags;
1359 host = mmc_priv(mmc);
1361 sdhci_runtime_pm_get(host);
1363 /* Firstly check card presence */
1364 present = sdhci_do_get_cd(host);
1366 spin_lock_irqsave(&host->lock, flags);
1368 WARN_ON(host->mrq != NULL);
1370 #ifndef SDHCI_USE_LEDS_CLASS
1371 sdhci_activate_led(host);
1375 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1376 * requests if Auto-CMD12 is enabled.
1378 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1380 mrq->data->stop = NULL;
1387 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1388 host->mrq->cmd->error = -ENOMEDIUM;
1389 tasklet_schedule(&host->finish_tasklet);
1393 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1395 * Check if the re-tuning timer has already expired and there
1396 * is no on-going data transfer and DAT0 is not busy. If so,
1397 * we need to execute tuning procedure before sending command.
1399 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1400 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
1401 (present_state & SDHCI_DATA_0_LVL_MASK)) {
1403 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1405 mmc->card->type == MMC_TYPE_MMC ?
1406 MMC_SEND_TUNING_BLOCK_HS200 :
1407 MMC_SEND_TUNING_BLOCK;
1409 /* Here we need to set the host->mrq to NULL,
1410 * in case the pending finish_tasklet
1411 * finishes it incorrectly.
1415 spin_unlock_irqrestore(&host->lock, flags);
1416 sdhci_execute_tuning(mmc, tuning_opcode);
1417 spin_lock_irqsave(&host->lock, flags);
1419 /* Restore original mmc_request structure */
1424 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1425 sdhci_send_command(host, mrq->sbc);
1427 sdhci_send_command(host, mrq->cmd);
1431 spin_unlock_irqrestore(&host->lock, flags);
1434 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1438 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1439 if (width == MMC_BUS_WIDTH_8) {
1440 ctrl &= ~SDHCI_CTRL_4BITBUS;
1441 if (host->version >= SDHCI_SPEC_300)
1442 ctrl |= SDHCI_CTRL_8BITBUS;
1444 if (host->version >= SDHCI_SPEC_300)
1445 ctrl &= ~SDHCI_CTRL_8BITBUS;
1446 if (width == MMC_BUS_WIDTH_4)
1447 ctrl |= SDHCI_CTRL_4BITBUS;
1449 ctrl &= ~SDHCI_CTRL_4BITBUS;
1451 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1453 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1455 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1459 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1460 /* Select Bus Speed Mode for host */
1461 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1462 if ((timing == MMC_TIMING_MMC_HS200) ||
1463 (timing == MMC_TIMING_UHS_SDR104))
1464 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1465 else if (timing == MMC_TIMING_UHS_SDR12)
1466 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1467 else if (timing == MMC_TIMING_UHS_SDR25)
1468 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1469 else if (timing == MMC_TIMING_UHS_SDR50)
1470 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1471 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1472 (timing == MMC_TIMING_MMC_DDR52))
1473 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1474 else if (timing == MMC_TIMING_MMC_HS400)
1475 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1476 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1478 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1480 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1482 unsigned long flags;
1484 struct mmc_host *mmc = host->mmc;
1486 spin_lock_irqsave(&host->lock, flags);
1488 if (host->flags & SDHCI_DEVICE_DEAD) {
1489 spin_unlock_irqrestore(&host->lock, flags);
1490 if (!IS_ERR(mmc->supply.vmmc) &&
1491 ios->power_mode == MMC_POWER_OFF)
1492 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1497 * Reset the chip on each power off.
1498 * Should clear out any weird states.
1500 if (ios->power_mode == MMC_POWER_OFF) {
1501 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1505 if (host->version >= SDHCI_SPEC_300 &&
1506 (ios->power_mode == MMC_POWER_UP) &&
1507 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1508 sdhci_enable_preset_value(host, false);
1510 if (!ios->clock || ios->clock != host->clock) {
1511 host->ops->set_clock(host, ios->clock);
1512 host->clock = ios->clock;
1514 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1516 host->timeout_clk = host->mmc->actual_clock ?
1517 host->mmc->actual_clock / 1000 :
1519 host->mmc->max_busy_timeout =
1520 host->ops->get_max_timeout_count ?
1521 host->ops->get_max_timeout_count(host) :
1523 host->mmc->max_busy_timeout /= host->timeout_clk;
1527 sdhci_set_power(host, ios->power_mode, ios->vdd);
1529 if (host->ops->platform_send_init_74_clocks)
1530 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1532 host->ops->set_bus_width(host, ios->bus_width);
1534 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1536 if ((ios->timing == MMC_TIMING_SD_HS ||
1537 ios->timing == MMC_TIMING_MMC_HS)
1538 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1539 ctrl |= SDHCI_CTRL_HISPD;
1541 ctrl &= ~SDHCI_CTRL_HISPD;
1543 if (host->version >= SDHCI_SPEC_300) {
1546 /* In case of UHS-I modes, set High Speed Enable */
1547 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1548 (ios->timing == MMC_TIMING_MMC_HS200) ||
1549 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1550 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1551 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1552 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1553 (ios->timing == MMC_TIMING_UHS_SDR25))
1554 ctrl |= SDHCI_CTRL_HISPD;
1556 if (!host->preset_enabled) {
1557 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1559 * We only need to set Driver Strength if the
1560 * preset value enable is not set.
1562 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1563 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1564 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1565 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1566 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1567 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1569 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1572 * According to SDHC Spec v3.00, if the Preset Value
1573 * Enable in the Host Control 2 register is set, we
1574 * need to reset SD Clock Enable before changing High
1575 * Speed Enable to avoid generating clock gliches.
1578 /* Reset SD Clock Enable */
1579 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1580 clk &= ~SDHCI_CLOCK_CARD_EN;
1581 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1583 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1585 /* Re-enable SD Clock */
1586 host->ops->set_clock(host, host->clock);
1589 /* Reset SD Clock Enable */
1590 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1591 clk &= ~SDHCI_CLOCK_CARD_EN;
1592 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1594 host->ops->set_uhs_signaling(host, ios->timing);
1595 host->timing = ios->timing;
1597 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1598 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1599 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1600 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1601 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1602 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1603 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1606 sdhci_enable_preset_value(host, true);
1607 preset = sdhci_get_preset_value(host);
1608 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1609 >> SDHCI_PRESET_DRV_SHIFT;
1612 /* Re-enable SD Clock */
1613 host->ops->set_clock(host, host->clock);
1615 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1618 * Some (ENE) controllers go apeshit on some ios operation,
1619 * signalling timeout and CRC errors even on CMD0. Resetting
1620 * it on each ios seems to solve the problem.
1622 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1623 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1626 spin_unlock_irqrestore(&host->lock, flags);
1629 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1631 struct sdhci_host *host = mmc_priv(mmc);
1633 sdhci_runtime_pm_get(host);
1634 sdhci_do_set_ios(host, ios);
1635 sdhci_runtime_pm_put(host);
1638 static int sdhci_do_get_cd(struct sdhci_host *host)
1640 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1642 if (host->flags & SDHCI_DEVICE_DEAD)
1645 /* If polling/nonremovable, assume that the card is always present. */
1646 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1647 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1650 /* Try slot gpio detect */
1651 if (!IS_ERR_VALUE(gpio_cd))
1654 /* Host native card detect */
1655 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1658 static int sdhci_get_cd(struct mmc_host *mmc)
1660 struct sdhci_host *host = mmc_priv(mmc);
1663 sdhci_runtime_pm_get(host);
1664 ret = sdhci_do_get_cd(host);
1665 sdhci_runtime_pm_put(host);
1669 static int sdhci_check_ro(struct sdhci_host *host)
1671 unsigned long flags;
1674 spin_lock_irqsave(&host->lock, flags);
1676 if (host->flags & SDHCI_DEVICE_DEAD)
1678 else if (host->ops->get_ro)
1679 is_readonly = host->ops->get_ro(host);
1681 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1682 & SDHCI_WRITE_PROTECT);
1684 spin_unlock_irqrestore(&host->lock, flags);
1686 /* This quirk needs to be replaced by a callback-function later */
1687 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1688 !is_readonly : is_readonly;
1691 #define SAMPLE_COUNT 5
1693 static int sdhci_do_get_ro(struct sdhci_host *host)
1697 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1698 return sdhci_check_ro(host);
1701 for (i = 0; i < SAMPLE_COUNT; i++) {
1702 if (sdhci_check_ro(host)) {
1703 if (++ro_count > SAMPLE_COUNT / 2)
1711 static void sdhci_hw_reset(struct mmc_host *mmc)
1713 struct sdhci_host *host = mmc_priv(mmc);
1715 if (host->ops && host->ops->hw_reset)
1716 host->ops->hw_reset(host);
1719 static int sdhci_get_ro(struct mmc_host *mmc)
1721 struct sdhci_host *host = mmc_priv(mmc);
1724 sdhci_runtime_pm_get(host);
1725 ret = sdhci_do_get_ro(host);
1726 sdhci_runtime_pm_put(host);
1730 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1732 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1734 host->ier |= SDHCI_INT_CARD_INT;
1736 host->ier &= ~SDHCI_INT_CARD_INT;
1738 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1739 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1744 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1746 struct sdhci_host *host = mmc_priv(mmc);
1747 unsigned long flags;
1749 sdhci_runtime_pm_get(host);
1751 spin_lock_irqsave(&host->lock, flags);
1753 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1755 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1757 sdhci_enable_sdio_irq_nolock(host, enable);
1758 spin_unlock_irqrestore(&host->lock, flags);
1760 sdhci_runtime_pm_put(host);
1763 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1764 struct mmc_ios *ios)
1766 struct mmc_host *mmc = host->mmc;
1771 * Signal Voltage Switching is only applicable for Host Controllers
1774 if (host->version < SDHCI_SPEC_300)
1777 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1779 switch (ios->signal_voltage) {
1780 case MMC_SIGNAL_VOLTAGE_330:
1781 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1782 ctrl &= ~SDHCI_CTRL_VDD_180;
1783 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1785 if (!IS_ERR(mmc->supply.vqmmc)) {
1786 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1789 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1795 usleep_range(5000, 5500);
1797 /* 3.3V regulator output should be stable within 5 ms */
1798 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1799 if (!(ctrl & SDHCI_CTRL_VDD_180))
1802 pr_warn("%s: 3.3V regulator output did not became stable\n",
1806 case MMC_SIGNAL_VOLTAGE_180:
1807 if (!IS_ERR(mmc->supply.vqmmc)) {
1808 ret = regulator_set_voltage(mmc->supply.vqmmc,
1811 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1818 * Enable 1.8V Signal Enable in the Host Control2
1821 ctrl |= SDHCI_CTRL_VDD_180;
1822 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1824 /* Some controller need to do more when switching */
1825 if (host->ops->voltage_switch)
1826 host->ops->voltage_switch(host);
1828 /* 1.8V regulator output should be stable within 5 ms */
1829 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1830 if (ctrl & SDHCI_CTRL_VDD_180)
1833 pr_warn("%s: 1.8V regulator output did not became stable\n",
1837 case MMC_SIGNAL_VOLTAGE_120:
1838 if (!IS_ERR(mmc->supply.vqmmc)) {
1839 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1842 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1849 /* No signal voltage switch required */
1854 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1855 struct mmc_ios *ios)
1857 struct sdhci_host *host = mmc_priv(mmc);
1860 if (host->version < SDHCI_SPEC_300)
1862 sdhci_runtime_pm_get(host);
1863 err = sdhci_do_start_signal_voltage_switch(host, ios);
1864 sdhci_runtime_pm_put(host);
1868 static int sdhci_card_busy(struct mmc_host *mmc)
1870 struct sdhci_host *host = mmc_priv(mmc);
1873 sdhci_runtime_pm_get(host);
1874 /* Check whether DAT[3:0] is 0000 */
1875 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1876 sdhci_runtime_pm_put(host);
1878 return !(present_state & SDHCI_DATA_LVL_MASK);
1881 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1883 struct sdhci_host *host = mmc_priv(mmc);
1884 unsigned long flags;
1886 spin_lock_irqsave(&host->lock, flags);
1887 host->flags |= SDHCI_HS400_TUNING;
1888 spin_unlock_irqrestore(&host->lock, flags);
1893 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1895 struct sdhci_host *host = mmc_priv(mmc);
1897 int tuning_loop_counter = MAX_TUNING_LOOP;
1899 unsigned long flags;
1900 unsigned int tuning_count = 0;
1903 sdhci_runtime_pm_get(host);
1904 spin_lock_irqsave(&host->lock, flags);
1906 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1907 host->flags &= ~SDHCI_HS400_TUNING;
1909 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1910 tuning_count = host->tuning_count;
1913 * The Host Controller needs tuning only in case of SDR104 mode
1914 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1915 * Capabilities register.
1916 * If the Host Controller supports the HS200 mode then the
1917 * tuning function has to be executed.
1919 switch (host->timing) {
1920 /* HS400 tuning is done in HS200 mode */
1921 case MMC_TIMING_MMC_HS400:
1925 case MMC_TIMING_MMC_HS200:
1927 * Periodic re-tuning for HS400 is not expected to be needed, so
1934 case MMC_TIMING_UHS_SDR104:
1937 case MMC_TIMING_UHS_SDR50:
1938 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1939 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1947 if (host->ops->platform_execute_tuning) {
1948 spin_unlock_irqrestore(&host->lock, flags);
1949 err = host->ops->platform_execute_tuning(host, opcode);
1950 sdhci_runtime_pm_put(host);
1954 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1955 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1956 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1957 ctrl |= SDHCI_CTRL_TUNED_CLK;
1958 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1961 * As per the Host Controller spec v3.00, tuning command
1962 * generates Buffer Read Ready interrupt, so enable that.
1964 * Note: The spec clearly says that when tuning sequence
1965 * is being performed, the controller does not generate
1966 * interrupts other than Buffer Read Ready interrupt. But
1967 * to make sure we don't hit a controller bug, we _only_
1968 * enable Buffer Read Ready interrupt here.
1970 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1971 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1974 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1975 * of loops reaches 40 times or a timeout of 150ms occurs.
1978 struct mmc_command cmd = {0};
1979 struct mmc_request mrq = {NULL};
1981 cmd.opcode = opcode;
1983 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1988 if (tuning_loop_counter-- == 0)
1995 * In response to CMD19, the card sends 64 bytes of tuning
1996 * block to the Host Controller. So we set the block size
1999 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2000 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2001 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2003 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2004 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2007 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2012 * The tuning block is sent by the card to the host controller.
2013 * So we set the TRNS_READ bit in the Transfer Mode register.
2014 * This also takes care of setting DMA Enable and Multi Block
2015 * Select in the same register to 0.
2017 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2019 sdhci_send_command(host, &cmd);
2024 spin_unlock_irqrestore(&host->lock, flags);
2025 /* Wait for Buffer Read Ready interrupt */
2026 wait_event_interruptible_timeout(host->buf_ready_int,
2027 (host->tuning_done == 1),
2028 msecs_to_jiffies(50));
2029 spin_lock_irqsave(&host->lock, flags);
2031 if (!host->tuning_done) {
2032 pr_info(DRIVER_NAME ": Timeout waiting for "
2033 "Buffer Read Ready interrupt during tuning "
2034 "procedure, falling back to fixed sampling "
2036 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2037 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2038 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2039 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2045 host->tuning_done = 0;
2047 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2049 /* eMMC spec does not require a delay between tuning cycles */
2050 if (opcode == MMC_SEND_TUNING_BLOCK)
2052 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2055 * The Host Driver has exhausted the maximum number of loops allowed,
2056 * so use fixed sampling frequency.
2058 if (tuning_loop_counter < 0) {
2059 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2060 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2062 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2063 pr_info(DRIVER_NAME ": Tuning procedure"
2064 " failed, falling back to fixed sampling"
2070 host->flags &= ~SDHCI_NEEDS_RETUNING;
2073 host->flags |= SDHCI_USING_RETUNING_TIMER;
2074 mod_timer(&host->tuning_timer, jiffies + tuning_count * HZ);
2078 * In case tuning fails, host controllers which support re-tuning can
2079 * try tuning again at a later time, when the re-tuning timer expires.
2080 * So for these controllers, we return 0. Since there might be other
2081 * controllers who do not have this capability, we return error for
2082 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2083 * a retuning timer to do the retuning for the card.
2085 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2088 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2089 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2091 spin_unlock_irqrestore(&host->lock, flags);
2092 sdhci_runtime_pm_put(host);
2098 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2100 /* Host Controller v3.00 defines preset value registers */
2101 if (host->version < SDHCI_SPEC_300)
2105 * We only enable or disable Preset Value if they are not already
2106 * enabled or disabled respectively. Otherwise, we bail out.
2108 if (host->preset_enabled != enable) {
2109 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2112 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2114 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2116 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2119 host->flags |= SDHCI_PV_ENABLED;
2121 host->flags &= ~SDHCI_PV_ENABLED;
2123 host->preset_enabled = enable;
2127 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2130 struct sdhci_host *host = mmc_priv(mmc);
2131 struct mmc_data *data = mrq->data;
2133 if (host->flags & SDHCI_REQ_USE_DMA) {
2134 if (data->host_cookie)
2135 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2136 data->flags & MMC_DATA_WRITE ?
2137 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2138 mrq->data->host_cookie = 0;
2142 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2143 struct mmc_data *data,
2144 struct sdhci_host_next *next)
2148 if (!next && data->host_cookie &&
2149 data->host_cookie != host->next_data.cookie) {
2150 pr_debug(DRIVER_NAME "[%s] invalid cookie: %d, next-cookie %d\n",
2151 __func__, data->host_cookie, host->next_data.cookie);
2152 data->host_cookie = 0;
2155 /* Check if next job is already prepared */
2157 (!next && data->host_cookie != host->next_data.cookie)) {
2158 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg,
2160 data->flags & MMC_DATA_WRITE ?
2161 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2164 sg_count = host->next_data.sg_count;
2165 host->next_data.sg_count = 0;
2173 next->sg_count = sg_count;
2174 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
2176 host->sg_count = sg_count;
2181 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2184 struct sdhci_host *host = mmc_priv(mmc);
2186 if (mrq->data->host_cookie) {
2187 mrq->data->host_cookie = 0;
2191 if (host->flags & SDHCI_REQ_USE_DMA)
2192 if (sdhci_pre_dma_transfer(host,
2194 &host->next_data) < 0)
2195 mrq->data->host_cookie = 0;
2198 static void sdhci_card_event(struct mmc_host *mmc)
2200 struct sdhci_host *host = mmc_priv(mmc);
2201 unsigned long flags;
2204 /* First check if client has provided their own card event */
2205 if (host->ops->card_event)
2206 host->ops->card_event(host);
2208 present = sdhci_do_get_cd(host);
2210 spin_lock_irqsave(&host->lock, flags);
2212 /* Check host->mrq first in case we are runtime suspended */
2213 if (host->mrq && !present) {
2214 pr_err("%s: Card removed during transfer!\n",
2215 mmc_hostname(host->mmc));
2216 pr_err("%s: Resetting controller.\n",
2217 mmc_hostname(host->mmc));
2219 sdhci_do_reset(host, SDHCI_RESET_CMD);
2220 sdhci_do_reset(host, SDHCI_RESET_DATA);
2222 host->mrq->cmd->error = -ENOMEDIUM;
2223 tasklet_schedule(&host->finish_tasklet);
2226 spin_unlock_irqrestore(&host->lock, flags);
2229 static const struct mmc_host_ops sdhci_ops = {
2230 .request = sdhci_request,
2231 .post_req = sdhci_post_req,
2232 .pre_req = sdhci_pre_req,
2233 .set_ios = sdhci_set_ios,
2234 .get_cd = sdhci_get_cd,
2235 .get_ro = sdhci_get_ro,
2236 .hw_reset = sdhci_hw_reset,
2237 .enable_sdio_irq = sdhci_enable_sdio_irq,
2238 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2239 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2240 .execute_tuning = sdhci_execute_tuning,
2241 .card_event = sdhci_card_event,
2242 .card_busy = sdhci_card_busy,
2245 /*****************************************************************************\
2249 \*****************************************************************************/
2251 static void sdhci_tasklet_finish(unsigned long param)
2253 struct sdhci_host *host;
2254 unsigned long flags;
2255 struct mmc_request *mrq;
2257 host = (struct sdhci_host*)param;
2259 spin_lock_irqsave(&host->lock, flags);
2262 * If this tasklet gets rescheduled while running, it will
2263 * be run again afterwards but without any active request.
2266 spin_unlock_irqrestore(&host->lock, flags);
2270 del_timer(&host->timer);
2275 * The controller needs a reset of internal state machines
2276 * upon error conditions.
2278 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2279 ((mrq->cmd && mrq->cmd->error) ||
2280 (mrq->sbc && mrq->sbc->error) ||
2281 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2282 (mrq->data->stop && mrq->data->stop->error))) ||
2283 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2285 /* Some controllers need this kick or reset won't work here */
2286 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2287 /* This is to force an update */
2288 host->ops->set_clock(host, host->clock);
2290 /* Spec says we should do both at the same time, but Ricoh
2291 controllers do not like that. */
2292 sdhci_do_reset(host, SDHCI_RESET_CMD);
2293 sdhci_do_reset(host, SDHCI_RESET_DATA);
2300 #ifndef SDHCI_USE_LEDS_CLASS
2301 sdhci_deactivate_led(host);
2305 spin_unlock_irqrestore(&host->lock, flags);
2307 mmc_request_done(host->mmc, mrq);
2308 sdhci_runtime_pm_put(host);
2311 static void sdhci_timeout_timer(unsigned long data)
2313 struct sdhci_host *host;
2314 unsigned long flags;
2316 host = (struct sdhci_host*)data;
2318 spin_lock_irqsave(&host->lock, flags);
2321 pr_err("%s: Timeout waiting for hardware "
2322 "interrupt.\n", mmc_hostname(host->mmc));
2323 sdhci_dumpregs(host);
2326 host->data->error = -ETIMEDOUT;
2327 sdhci_finish_data(host);
2330 host->cmd->error = -ETIMEDOUT;
2332 host->mrq->cmd->error = -ETIMEDOUT;
2334 tasklet_schedule(&host->finish_tasklet);
2339 spin_unlock_irqrestore(&host->lock, flags);
2342 static void sdhci_tuning_timer(unsigned long data)
2344 struct sdhci_host *host;
2345 unsigned long flags;
2347 host = (struct sdhci_host *)data;
2349 spin_lock_irqsave(&host->lock, flags);
2351 host->flags |= SDHCI_NEEDS_RETUNING;
2353 spin_unlock_irqrestore(&host->lock, flags);
2356 /*****************************************************************************\
2358 * Interrupt handling *
2360 \*****************************************************************************/
2362 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2364 BUG_ON(intmask == 0);
2367 pr_err("%s: Got command interrupt 0x%08x even "
2368 "though no command operation was in progress.\n",
2369 mmc_hostname(host->mmc), (unsigned)intmask);
2370 sdhci_dumpregs(host);
2374 if (intmask & SDHCI_INT_TIMEOUT)
2375 host->cmd->error = -ETIMEDOUT;
2376 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2378 host->cmd->error = -EILSEQ;
2380 if (host->cmd->error) {
2381 tasklet_schedule(&host->finish_tasklet);
2386 * The host can send and interrupt when the busy state has
2387 * ended, allowing us to wait without wasting CPU cycles.
2388 * Unfortunately this is overloaded on the "data complete"
2389 * interrupt, so we need to take some care when handling
2392 * Note: The 1.0 specification is a bit ambiguous about this
2393 * feature so there might be some problems with older
2396 if (host->cmd->flags & MMC_RSP_BUSY) {
2397 if (host->cmd->data)
2398 DBG("Cannot wait for busy signal when also "
2399 "doing a data transfer");
2400 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2401 && !host->busy_handle) {
2402 /* Mark that command complete before busy is ended */
2403 host->busy_handle = 1;
2407 /* The controller does not support the end-of-busy IRQ,
2408 * fall through and take the SDHCI_INT_RESPONSE */
2409 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2410 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2411 *mask &= ~SDHCI_INT_DATA_END;
2414 if (intmask & SDHCI_INT_RESPONSE)
2415 sdhci_finish_command(host);
2418 #ifdef CONFIG_MMC_DEBUG
2419 static void sdhci_adma_show_error(struct sdhci_host *host)
2421 const char *name = mmc_hostname(host->mmc);
2422 void *desc = host->adma_table;
2424 sdhci_dumpregs(host);
2427 struct sdhci_adma2_64_desc *dma_desc = desc;
2429 if (host->flags & SDHCI_USE_64_BIT_DMA)
2430 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2431 name, desc, le32_to_cpu(dma_desc->addr_hi),
2432 le32_to_cpu(dma_desc->addr_lo),
2433 le16_to_cpu(dma_desc->len),
2434 le16_to_cpu(dma_desc->cmd));
2436 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2437 name, desc, le32_to_cpu(dma_desc->addr_lo),
2438 le16_to_cpu(dma_desc->len),
2439 le16_to_cpu(dma_desc->cmd));
2441 desc += host->desc_sz;
2443 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2448 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2451 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2454 BUG_ON(intmask == 0);
2456 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2457 if (intmask & SDHCI_INT_DATA_AVAIL) {
2458 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2459 if (command == MMC_SEND_TUNING_BLOCK ||
2460 command == MMC_SEND_TUNING_BLOCK_HS200) {
2461 host->tuning_done = 1;
2462 wake_up(&host->buf_ready_int);
2469 * The "data complete" interrupt is also used to
2470 * indicate that a busy state has ended. See comment
2471 * above in sdhci_cmd_irq().
2473 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2474 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2475 host->cmd->error = -ETIMEDOUT;
2476 tasklet_schedule(&host->finish_tasklet);
2479 if (intmask & SDHCI_INT_DATA_END) {
2481 * Some cards handle busy-end interrupt
2482 * before the command completed, so make
2483 * sure we do things in the proper order.
2485 if (host->busy_handle)
2486 sdhci_finish_command(host);
2488 host->busy_handle = 1;
2493 pr_err("%s: Got data interrupt 0x%08x even "
2494 "though no data operation was in progress.\n",
2495 mmc_hostname(host->mmc), (unsigned)intmask);
2496 sdhci_dumpregs(host);
2501 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2502 host->data->error = -ETIMEDOUT;
2503 else if (intmask & SDHCI_INT_DATA_END_BIT)
2504 host->data->error = -EILSEQ;
2505 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2506 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2508 host->data->error = -EILSEQ;
2509 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2510 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2511 sdhci_adma_show_error(host);
2512 host->data->error = -EIO;
2513 if (host->ops->adma_workaround)
2514 host->ops->adma_workaround(host, intmask);
2517 if (host->data->error)
2518 sdhci_finish_data(host);
2520 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2521 sdhci_transfer_pio(host);
2524 * We currently don't do anything fancy with DMA
2525 * boundaries, but as we can't disable the feature
2526 * we need to at least restart the transfer.
2528 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2529 * should return a valid address to continue from, but as
2530 * some controllers are faulty, don't trust them.
2532 if (intmask & SDHCI_INT_DMA_END) {
2533 u32 dmastart, dmanow;
2534 dmastart = sg_dma_address(host->data->sg);
2535 dmanow = dmastart + host->data->bytes_xfered;
2537 * Force update to the next DMA block boundary.
2540 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2541 SDHCI_DEFAULT_BOUNDARY_SIZE;
2542 host->data->bytes_xfered = dmanow - dmastart;
2543 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2545 mmc_hostname(host->mmc), dmastart,
2546 host->data->bytes_xfered, dmanow);
2547 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2550 if (intmask & SDHCI_INT_DATA_END) {
2553 * Data managed to finish before the
2554 * command completed. Make sure we do
2555 * things in the proper order.
2557 host->data_early = 1;
2559 sdhci_finish_data(host);
2565 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2567 irqreturn_t result = IRQ_NONE;
2568 struct sdhci_host *host = dev_id;
2569 u32 intmask, mask, unexpected = 0;
2572 spin_lock(&host->lock);
2574 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2575 spin_unlock(&host->lock);
2579 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2580 if (!intmask || intmask == 0xffffffff) {
2586 /* Clear selected interrupts. */
2587 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2588 SDHCI_INT_BUS_POWER);
2589 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2591 DBG("*** %s got interrupt: 0x%08x\n",
2592 mmc_hostname(host->mmc), intmask);
2594 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2595 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2599 * There is a observation on i.mx esdhc. INSERT
2600 * bit will be immediately set again when it gets
2601 * cleared, if a card is inserted. We have to mask
2602 * the irq to prevent interrupt storm which will
2603 * freeze the system. And the REMOVE gets the
2606 * More testing are needed here to ensure it works
2607 * for other platforms though.
2609 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2610 SDHCI_INT_CARD_REMOVE);
2611 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2612 SDHCI_INT_CARD_INSERT;
2613 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2614 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2616 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2617 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2619 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2620 SDHCI_INT_CARD_REMOVE);
2621 result = IRQ_WAKE_THREAD;
2624 if (intmask & SDHCI_INT_CMD_MASK)
2625 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2628 if (intmask & SDHCI_INT_DATA_MASK)
2629 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2631 if (intmask & SDHCI_INT_BUS_POWER)
2632 pr_err("%s: Card is consuming too much power!\n",
2633 mmc_hostname(host->mmc));
2635 if (intmask & SDHCI_INT_CARD_INT) {
2636 sdhci_enable_sdio_irq_nolock(host, false);
2637 host->thread_isr |= SDHCI_INT_CARD_INT;
2638 result = IRQ_WAKE_THREAD;
2641 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2642 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2643 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2644 SDHCI_INT_CARD_INT);
2647 unexpected |= intmask;
2648 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2651 if (result == IRQ_NONE)
2652 result = IRQ_HANDLED;
2654 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2655 } while (intmask && --max_loops);
2657 spin_unlock(&host->lock);
2660 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2661 mmc_hostname(host->mmc), unexpected);
2662 sdhci_dumpregs(host);
2668 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2670 struct sdhci_host *host = dev_id;
2671 unsigned long flags;
2674 spin_lock_irqsave(&host->lock, flags);
2675 isr = host->thread_isr;
2676 host->thread_isr = 0;
2677 spin_unlock_irqrestore(&host->lock, flags);
2679 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2680 sdhci_card_event(host->mmc);
2681 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2684 if (isr & SDHCI_INT_CARD_INT) {
2685 sdio_run_irqs(host->mmc);
2687 spin_lock_irqsave(&host->lock, flags);
2688 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2689 sdhci_enable_sdio_irq_nolock(host, true);
2690 spin_unlock_irqrestore(&host->lock, flags);
2693 return isr ? IRQ_HANDLED : IRQ_NONE;
2696 /*****************************************************************************\
2700 \*****************************************************************************/
2703 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2706 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2707 | SDHCI_WAKE_ON_INT;
2709 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2711 /* Avoid fake wake up */
2712 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2713 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2714 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2716 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2718 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2721 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2722 | SDHCI_WAKE_ON_INT;
2724 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2726 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2729 int sdhci_suspend_host(struct sdhci_host *host)
2731 sdhci_disable_card_detection(host);
2733 /* Disable tuning since we are suspending */
2734 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2735 del_timer_sync(&host->tuning_timer);
2736 host->flags &= ~SDHCI_NEEDS_RETUNING;
2739 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2741 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2742 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2743 free_irq(host->irq, host);
2745 sdhci_enable_irq_wakeups(host);
2746 enable_irq_wake(host->irq);
2751 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2753 int sdhci_resume_host(struct sdhci_host *host)
2757 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2758 if (host->ops->enable_dma)
2759 host->ops->enable_dma(host);
2762 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2763 ret = request_threaded_irq(host->irq, sdhci_irq,
2764 sdhci_thread_irq, IRQF_SHARED,
2765 mmc_hostname(host->mmc), host);
2769 sdhci_disable_irq_wakeups(host);
2770 disable_irq_wake(host->irq);
2773 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2774 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2775 /* Card keeps power but host controller does not */
2776 sdhci_init(host, 0);
2779 sdhci_do_set_ios(host, &host->mmc->ios);
2781 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2785 sdhci_enable_card_detection(host);
2787 /* Set the re-tuning expiration flag */
2788 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2789 host->flags |= SDHCI_NEEDS_RETUNING;
2794 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2796 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2798 return pm_runtime_get_sync(host->mmc->parent);
2801 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2803 pm_runtime_mark_last_busy(host->mmc->parent);
2804 return pm_runtime_put_autosuspend(host->mmc->parent);
2807 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2809 if (host->runtime_suspended || host->bus_on)
2811 host->bus_on = true;
2812 pm_runtime_get_noresume(host->mmc->parent);
2815 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2817 if (host->runtime_suspended || !host->bus_on)
2819 host->bus_on = false;
2820 pm_runtime_put_noidle(host->mmc->parent);
2823 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2825 unsigned long flags;
2827 /* Disable tuning since we are suspending */
2828 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2829 del_timer_sync(&host->tuning_timer);
2830 host->flags &= ~SDHCI_NEEDS_RETUNING;
2833 spin_lock_irqsave(&host->lock, flags);
2834 host->ier &= SDHCI_INT_CARD_INT;
2835 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2836 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2837 spin_unlock_irqrestore(&host->lock, flags);
2839 synchronize_hardirq(host->irq);
2841 spin_lock_irqsave(&host->lock, flags);
2842 host->runtime_suspended = true;
2843 spin_unlock_irqrestore(&host->lock, flags);
2847 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2849 int sdhci_runtime_resume_host(struct sdhci_host *host)
2851 unsigned long flags;
2852 int host_flags = host->flags;
2854 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2855 if (host->ops->enable_dma)
2856 host->ops->enable_dma(host);
2859 sdhci_init(host, 0);
2861 /* Force clock and power re-program */
2864 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2865 sdhci_do_set_ios(host, &host->mmc->ios);
2867 if ((host_flags & SDHCI_PV_ENABLED) &&
2868 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2869 spin_lock_irqsave(&host->lock, flags);
2870 sdhci_enable_preset_value(host, true);
2871 spin_unlock_irqrestore(&host->lock, flags);
2874 /* Set the re-tuning expiration flag */
2875 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2876 host->flags |= SDHCI_NEEDS_RETUNING;
2878 spin_lock_irqsave(&host->lock, flags);
2880 host->runtime_suspended = false;
2882 /* Enable SDIO IRQ */
2883 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2884 sdhci_enable_sdio_irq_nolock(host, true);
2886 /* Enable Card Detection */
2887 sdhci_enable_card_detection(host);
2889 spin_unlock_irqrestore(&host->lock, flags);
2893 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2895 #endif /* CONFIG_PM */
2897 /*****************************************************************************\
2899 * Device allocation/registration *
2901 \*****************************************************************************/
2903 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2906 struct mmc_host *mmc;
2907 struct sdhci_host *host;
2909 WARN_ON(dev == NULL);
2911 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2913 return ERR_PTR(-ENOMEM);
2915 host = mmc_priv(mmc);
2921 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2923 int sdhci_add_host(struct sdhci_host *host)
2925 struct mmc_host *mmc;
2926 u32 caps[2] = {0, 0};
2927 u32 max_current_caps;
2928 unsigned int ocr_avail;
2929 unsigned int override_timeout_clk;
2932 WARN_ON(host == NULL);
2939 host->quirks = debug_quirks;
2941 host->quirks2 = debug_quirks2;
2943 override_timeout_clk = host->timeout_clk;
2945 sdhci_do_reset(host, SDHCI_RESET_ALL);
2947 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2948 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2949 >> SDHCI_SPEC_VER_SHIFT;
2950 if (host->version > SDHCI_SPEC_300) {
2951 pr_err("%s: Unknown controller version (%d). "
2952 "You may experience problems.\n", mmc_hostname(mmc),
2956 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2957 sdhci_readl(host, SDHCI_CAPABILITIES);
2959 if (host->version >= SDHCI_SPEC_300)
2960 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2962 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2964 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2965 host->flags |= SDHCI_USE_SDMA;
2966 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2967 DBG("Controller doesn't have SDMA capability\n");
2969 host->flags |= SDHCI_USE_SDMA;
2971 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2972 (host->flags & SDHCI_USE_SDMA)) {
2973 DBG("Disabling DMA as it is marked broken\n");
2974 host->flags &= ~SDHCI_USE_SDMA;
2977 if ((host->version >= SDHCI_SPEC_200) &&
2978 (caps[0] & SDHCI_CAN_DO_ADMA2))
2979 host->flags |= SDHCI_USE_ADMA;
2981 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2982 (host->flags & SDHCI_USE_ADMA)) {
2983 DBG("Disabling ADMA as it is marked broken\n");
2984 host->flags &= ~SDHCI_USE_ADMA;
2988 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2989 * and *must* do 64-bit DMA. A driver has the opportunity to change
2990 * that during the first call to ->enable_dma(). Similarly
2991 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2994 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2995 host->flags |= SDHCI_USE_64_BIT_DMA;
2997 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2998 if (host->ops->enable_dma) {
2999 if (host->ops->enable_dma(host)) {
3000 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3003 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3008 /* SDMA does not support 64-bit DMA */
3009 if (host->flags & SDHCI_USE_64_BIT_DMA)
3010 host->flags &= ~SDHCI_USE_SDMA;
3012 if (host->flags & SDHCI_USE_ADMA) {
3014 * The DMA descriptor table size is calculated as the maximum
3015 * number of segments times 2, to allow for an alignment
3016 * descriptor for each segment, plus 1 for a nop end descriptor,
3017 * all multipled by the descriptor size.
3019 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3020 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3021 SDHCI_ADMA2_64_DESC_SZ;
3022 host->align_buffer_sz = SDHCI_MAX_SEGS *
3023 SDHCI_ADMA2_64_ALIGN;
3024 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3025 host->align_sz = SDHCI_ADMA2_64_ALIGN;
3026 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
3028 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3029 SDHCI_ADMA2_32_DESC_SZ;
3030 host->align_buffer_sz = SDHCI_MAX_SEGS *
3031 SDHCI_ADMA2_32_ALIGN;
3032 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3033 host->align_sz = SDHCI_ADMA2_32_ALIGN;
3034 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
3036 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
3037 host->adma_table_sz,
3040 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
3041 if (!host->adma_table || !host->align_buffer) {
3042 if (host->adma_table)
3043 dma_free_coherent(mmc_dev(mmc),
3044 host->adma_table_sz,
3047 kfree(host->align_buffer);
3048 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3050 host->flags &= ~SDHCI_USE_ADMA;
3051 host->adma_table = NULL;
3052 host->align_buffer = NULL;
3053 } else if (host->adma_addr & host->align_mask) {
3054 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3056 host->flags &= ~SDHCI_USE_ADMA;
3057 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3058 host->adma_table, host->adma_addr);
3059 kfree(host->align_buffer);
3060 host->adma_table = NULL;
3061 host->align_buffer = NULL;
3066 * If we use DMA, then it's up to the caller to set the DMA
3067 * mask, but PIO does not need the hw shim so we set a new
3068 * mask here in that case.
3070 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3071 host->dma_mask = DMA_BIT_MASK(64);
3072 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3075 if (host->version >= SDHCI_SPEC_300)
3076 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3077 >> SDHCI_CLOCK_BASE_SHIFT;
3079 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3080 >> SDHCI_CLOCK_BASE_SHIFT;
3082 host->max_clk *= 1000000;
3083 if (host->max_clk == 0 || host->quirks &
3084 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3085 if (!host->ops->get_max_clock) {
3086 pr_err("%s: Hardware doesn't specify base clock "
3087 "frequency.\n", mmc_hostname(mmc));
3090 host->max_clk = host->ops->get_max_clock(host);
3093 host->next_data.cookie = 1;
3095 * In case of Host Controller v3.00, find out whether clock
3096 * multiplier is supported.
3098 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3099 SDHCI_CLOCK_MUL_SHIFT;
3102 * In case the value in Clock Multiplier is 0, then programmable
3103 * clock mode is not supported, otherwise the actual clock
3104 * multiplier is one more than the value of Clock Multiplier
3105 * in the Capabilities Register.
3111 * Set host parameters.
3113 mmc->ops = &sdhci_ops;
3114 mmc->f_max = host->max_clk;
3115 if (host->ops->get_min_clock)
3116 mmc->f_min = host->ops->get_min_clock(host);
3117 else if (host->version >= SDHCI_SPEC_300) {
3118 if (host->clk_mul) {
3119 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3120 mmc->f_max = host->max_clk * host->clk_mul;
3122 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3124 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3126 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3127 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3128 SDHCI_TIMEOUT_CLK_SHIFT;
3129 if (host->timeout_clk == 0) {
3130 if (host->ops->get_timeout_clock) {
3132 host->ops->get_timeout_clock(host);
3134 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3140 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3141 host->timeout_clk *= 1000;
3143 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3144 host->ops->get_max_timeout_count(host) : 1 << 27;
3145 mmc->max_busy_timeout /= host->timeout_clk;
3148 if (override_timeout_clk)
3149 host->timeout_clk = override_timeout_clk;
3151 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3152 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3154 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3155 host->flags |= SDHCI_AUTO_CMD12;
3157 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3158 if ((host->version >= SDHCI_SPEC_300) &&
3159 ((host->flags & SDHCI_USE_ADMA) ||
3160 !(host->flags & SDHCI_USE_SDMA)) &&
3161 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3162 host->flags |= SDHCI_AUTO_CMD23;
3163 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3165 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3169 * A controller may support 8-bit width, but the board itself
3170 * might not have the pins brought out. Boards that support
3171 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3172 * their platform code before calling sdhci_add_host(), and we
3173 * won't assume 8-bit width for hosts without that CAP.
3175 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3176 mmc->caps |= MMC_CAP_4_BIT_DATA;
3178 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3179 mmc->caps &= ~MMC_CAP_CMD23;
3181 if (caps[0] & SDHCI_CAN_DO_HISPD)
3182 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3184 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3185 !(mmc->caps & MMC_CAP_NONREMOVABLE))
3186 mmc->caps |= MMC_CAP_NEEDS_POLL;
3188 /* If there are external regulators, get them */
3189 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3190 return -EPROBE_DEFER;
3192 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3193 if (!IS_ERR(mmc->supply.vqmmc)) {
3194 ret = regulator_enable(mmc->supply.vqmmc);
3195 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3197 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3198 SDHCI_SUPPORT_SDR50 |
3199 SDHCI_SUPPORT_DDR50);
3201 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3202 mmc_hostname(mmc), ret);
3203 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3207 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3208 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3209 SDHCI_SUPPORT_DDR50);
3211 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3212 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3213 SDHCI_SUPPORT_DDR50))
3214 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3216 /* SDR104 supports also implies SDR50 support */
3217 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3218 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3219 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3220 * field can be promoted to support HS200.
3222 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3223 mmc->caps2 |= MMC_CAP2_HS200;
3224 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3225 mmc->caps |= MMC_CAP_UHS_SDR50;
3227 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3228 (caps[1] & SDHCI_SUPPORT_HS400))
3229 mmc->caps2 |= MMC_CAP2_HS400;
3231 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3232 (IS_ERR(mmc->supply.vqmmc) ||
3233 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3235 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3237 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3238 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3239 mmc->caps |= MMC_CAP_UHS_DDR50;
3241 /* Does the host need tuning for SDR50? */
3242 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3243 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3245 /* Does the host need tuning for SDR104 / HS200? */
3246 if (mmc->caps2 & MMC_CAP2_HS200)
3247 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3249 /* Driver Type(s) (A, C, D) supported by the host */
3250 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3251 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3252 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3253 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3254 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3255 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3257 /* Initial value for re-tuning timer count */
3258 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3259 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3262 * In case Re-tuning Timer is not disabled, the actual value of
3263 * re-tuning timer will be 2 ^ (n - 1).
3265 if (host->tuning_count)
3266 host->tuning_count = 1 << (host->tuning_count - 1);
3268 /* Re-tuning mode supported by the Host Controller */
3269 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3270 SDHCI_RETUNING_MODE_SHIFT;
3275 * According to SD Host Controller spec v3.00, if the Host System
3276 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3277 * the value is meaningful only if Voltage Support in the Capabilities
3278 * register is set. The actual current value is 4 times the register
3281 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3282 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3283 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3286 /* convert to SDHCI_MAX_CURRENT format */
3287 curr = curr/1000; /* convert to mA */
3288 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3290 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3292 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3293 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3294 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3298 if (caps[0] & SDHCI_CAN_VDD_330) {
3299 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3301 mmc->max_current_330 = ((max_current_caps &
3302 SDHCI_MAX_CURRENT_330_MASK) >>
3303 SDHCI_MAX_CURRENT_330_SHIFT) *
3304 SDHCI_MAX_CURRENT_MULTIPLIER;
3306 if (caps[0] & SDHCI_CAN_VDD_300) {
3307 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3309 mmc->max_current_300 = ((max_current_caps &
3310 SDHCI_MAX_CURRENT_300_MASK) >>
3311 SDHCI_MAX_CURRENT_300_SHIFT) *
3312 SDHCI_MAX_CURRENT_MULTIPLIER;
3314 if (caps[0] & SDHCI_CAN_VDD_180) {
3315 ocr_avail |= MMC_VDD_165_195;
3317 mmc->max_current_180 = ((max_current_caps &
3318 SDHCI_MAX_CURRENT_180_MASK) >>
3319 SDHCI_MAX_CURRENT_180_SHIFT) *
3320 SDHCI_MAX_CURRENT_MULTIPLIER;
3323 /* If OCR set by host, use it instead. */
3325 ocr_avail = host->ocr_mask;
3327 /* If OCR set by external regulators, give it highest prio. */
3329 ocr_avail = mmc->ocr_avail;
3331 mmc->ocr_avail = ocr_avail;
3332 mmc->ocr_avail_sdio = ocr_avail;
3333 if (host->ocr_avail_sdio)
3334 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3335 mmc->ocr_avail_sd = ocr_avail;
3336 if (host->ocr_avail_sd)
3337 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3338 else /* normal SD controllers don't support 1.8V */
3339 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3340 mmc->ocr_avail_mmc = ocr_avail;
3341 if (host->ocr_avail_mmc)
3342 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3344 if (mmc->ocr_avail == 0) {
3345 pr_err("%s: Hardware doesn't report any "
3346 "support voltages.\n", mmc_hostname(mmc));
3350 spin_lock_init(&host->lock);
3353 * Maximum number of segments. Depends on if the hardware
3354 * can do scatter/gather or not.
3356 if (host->flags & SDHCI_USE_ADMA)
3357 mmc->max_segs = SDHCI_MAX_SEGS;
3358 else if (host->flags & SDHCI_USE_SDMA)
3361 mmc->max_segs = SDHCI_MAX_SEGS;
3364 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3365 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3368 mmc->max_req_size = 524288;
3371 * Maximum segment size. Could be one segment with the maximum number
3372 * of bytes. When doing hardware scatter/gather, each entry cannot
3373 * be larger than 64 KiB though.
3375 if (host->flags & SDHCI_USE_ADMA) {
3376 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3377 mmc->max_seg_size = 65535;
3379 mmc->max_seg_size = 65536;
3381 mmc->max_seg_size = mmc->max_req_size;
3385 * Maximum block size. This varies from controller to controller and
3386 * is specified in the capabilities register.
3388 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3389 mmc->max_blk_size = 2;
3391 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3392 SDHCI_MAX_BLOCK_SHIFT;
3393 if (mmc->max_blk_size >= 3) {
3394 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3396 mmc->max_blk_size = 0;
3400 mmc->max_blk_size = 512 << mmc->max_blk_size;
3403 * Maximum block count.
3405 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3410 tasklet_init(&host->finish_tasklet,
3411 sdhci_tasklet_finish, (unsigned long)host);
3413 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3415 init_waitqueue_head(&host->buf_ready_int);
3417 if (host->version >= SDHCI_SPEC_300) {
3418 /* Initialize re-tuning timer */
3419 init_timer(&host->tuning_timer);
3420 host->tuning_timer.data = (unsigned long)host;
3421 host->tuning_timer.function = sdhci_tuning_timer;
3424 sdhci_init(host, 0);
3426 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3427 IRQF_SHARED, mmc_hostname(mmc), host);
3429 pr_err("%s: Failed to request IRQ %d: %d\n",
3430 mmc_hostname(mmc), host->irq, ret);
3434 #ifdef CONFIG_MMC_DEBUG
3435 sdhci_dumpregs(host);
3438 #ifdef SDHCI_USE_LEDS_CLASS
3439 snprintf(host->led_name, sizeof(host->led_name),
3440 "%s::", mmc_hostname(mmc));
3441 host->led.name = host->led_name;
3442 host->led.brightness = LED_OFF;
3443 host->led.default_trigger = mmc_hostname(mmc);
3444 host->led.brightness_set = sdhci_led_control;
3446 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3448 pr_err("%s: Failed to register LED device: %d\n",
3449 mmc_hostname(mmc), ret);
3458 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3459 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3460 (host->flags & SDHCI_USE_ADMA) ?
3461 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3462 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3464 sdhci_enable_card_detection(host);
3468 #ifdef SDHCI_USE_LEDS_CLASS
3470 sdhci_do_reset(host, SDHCI_RESET_ALL);
3471 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3472 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3473 free_irq(host->irq, host);
3476 tasklet_kill(&host->finish_tasklet);
3481 EXPORT_SYMBOL_GPL(sdhci_add_host);
3483 void sdhci_remove_host(struct sdhci_host *host, int dead)
3485 struct mmc_host *mmc = host->mmc;
3486 unsigned long flags;
3489 spin_lock_irqsave(&host->lock, flags);
3491 host->flags |= SDHCI_DEVICE_DEAD;
3494 pr_err("%s: Controller removed during "
3495 " transfer!\n", mmc_hostname(mmc));
3497 host->mrq->cmd->error = -ENOMEDIUM;
3498 tasklet_schedule(&host->finish_tasklet);
3501 spin_unlock_irqrestore(&host->lock, flags);
3504 sdhci_disable_card_detection(host);
3506 mmc_remove_host(mmc);
3508 #ifdef SDHCI_USE_LEDS_CLASS
3509 led_classdev_unregister(&host->led);
3513 sdhci_do_reset(host, SDHCI_RESET_ALL);
3515 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3516 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3517 free_irq(host->irq, host);
3519 del_timer_sync(&host->timer);
3521 tasklet_kill(&host->finish_tasklet);
3523 if (!IS_ERR(mmc->supply.vqmmc))
3524 regulator_disable(mmc->supply.vqmmc);
3526 if (host->adma_table)
3527 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3528 host->adma_table, host->adma_addr);
3529 kfree(host->align_buffer);
3531 host->adma_table = NULL;
3532 host->align_buffer = NULL;
3535 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3537 void sdhci_free_host(struct sdhci_host *host)
3539 mmc_free_host(host->mmc);
3542 EXPORT_SYMBOL_GPL(sdhci_free_host);
3544 /*****************************************************************************\
3546 * Driver init/exit *
3548 \*****************************************************************************/
3550 static int __init sdhci_drv_init(void)
3553 ": Secure Digital Host Controller Interface driver\n");
3554 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3559 static void __exit sdhci_drv_exit(void)
3563 module_init(sdhci_drv_init);
3564 module_exit(sdhci_drv_exit);
3566 module_param(debug_quirks, uint, 0444);
3567 module_param(debug_quirks2, uint, 0444);
3569 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3570 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3571 MODULE_LICENSE("GPL");
3573 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3574 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");