2 * Realtek RTL2832 DVB-T demodulator driver
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
5 * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #ifndef RTL2832_PRIV_H
23 #define RTL2832_PRIV_H
25 #include <linux/regmap.h>
26 #include <linux/math64.h>
27 #include <linux/bitops.h>
29 #include "dvb_frontend.h"
34 struct rtl2832_platform_data *pdata;
35 struct i2c_client *client;
36 struct mutex regmap_mutex;
37 struct regmap_config regmap_config;
38 struct regmap *regmap;
39 struct i2c_adapter *i2c_adapter_tuner;
40 struct dvb_frontend fe;
41 struct delayed_work stat_work;
42 fe_status_t fe_status;
43 u64 post_bit_error_prev; /* for old DVBv3 read_ber() calculation */
47 struct delayed_work i2c_gate_work;
48 unsigned long filters; /* PID filter */
51 struct rtl2832_reg_entry {
57 struct rtl2832_reg_value {
62 /* Demod register bit names */
63 enum DVBT_REG_BIT_NAME {
67 DVBT_RSD_BER_FAIL_VAL,
128 DVBT_CFREQ_OFF_RATIO,
163 DVBT_AGC_TARG_VAL_8_1,
194 DVBT_MPEG_IO_OPT_2_2,
195 DVBT_MPEG_IO_OPT_1_0,
252 DVBT_REG_BIT_NAME_ITEM_TERMINATOR,
255 static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = {
256 {DVBT_DAGC_TRG_VAL, 0x39},
257 {DVBT_AGC_TARG_VAL_0, 0x0},
258 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
259 {DVBT_AAGC_LOOP_GAIN, 0x16},
260 {DVBT_LOOP_GAIN2_3_0, 0x6},
261 {DVBT_LOOP_GAIN2_4, 0x1},
262 {DVBT_LOOP_GAIN3, 0x16},
270 {DVBT_IF_AGC_MIN, 0x80},
271 {DVBT_IF_AGC_MAX, 0x7f},
272 {DVBT_RF_AGC_MIN, 0x9c},
273 {DVBT_RF_AGC_MAX, 0x7f},
274 {DVBT_POLAR_RF_AGC, 0x0},
275 {DVBT_POLAR_IF_AGC, 0x0},
276 {DVBT_AD7_SETTING, 0xe9f4},
277 {DVBT_OPT_ADC_IQ, 0x1},
280 {DVBT_SPEC_INV, 0x0},
283 static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = {
284 {DVBT_DAGC_TRG_VAL, 0x5a},
285 {DVBT_AGC_TARG_VAL_0, 0x0},
286 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
287 {DVBT_AAGC_LOOP_GAIN, 0x16},
288 {DVBT_LOOP_GAIN2_3_0, 0x6},
289 {DVBT_LOOP_GAIN2_4, 0x1},
290 {DVBT_LOOP_GAIN3, 0x16},
298 {DVBT_IF_AGC_MIN, 0x80},
299 {DVBT_IF_AGC_MAX, 0x7f},
300 {DVBT_RF_AGC_MIN, 0x80},
301 {DVBT_RF_AGC_MAX, 0x7f},
302 {DVBT_POLAR_RF_AGC, 0x0},
303 {DVBT_POLAR_IF_AGC, 0x0},
304 {DVBT_AD7_SETTING, 0xe9bf},
305 {DVBT_EN_GI_PGA, 0x0},
306 {DVBT_THD_LOCK_UP, 0x0},
307 {DVBT_THD_LOCK_DW, 0x0},
308 {DVBT_THD_UP1, 0x11},
309 {DVBT_THD_DW1, 0xef},
310 {DVBT_INTER_CNT_LEN, 0xc},
311 {DVBT_GI_PGA_STATE, 0x0},
312 {DVBT_EN_AGC_PGA, 0x1},
313 {DVBT_IF_AGC_MAN, 0x0},
314 {DVBT_SPEC_INV, 0x0},
317 static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = {
318 {DVBT_DAGC_TRG_VAL, 0x5a},
319 {DVBT_AGC_TARG_VAL_0, 0x0},
320 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
321 {DVBT_AAGC_LOOP_GAIN, 0x18},
322 {DVBT_LOOP_GAIN2_3_0, 0x8},
323 {DVBT_LOOP_GAIN2_4, 0x1},
324 {DVBT_LOOP_GAIN3, 0x18},
332 {DVBT_IF_AGC_MIN, 0x80},
333 {DVBT_IF_AGC_MAX, 0x7f},
334 {DVBT_RF_AGC_MIN, 0x80},
335 {DVBT_RF_AGC_MAX, 0x7f},
336 {DVBT_POLAR_RF_AGC, 0x0},
337 {DVBT_POLAR_IF_AGC, 0x0},
338 {DVBT_AD7_SETTING, 0xe9d4},
339 {DVBT_EN_GI_PGA, 0x0},
340 {DVBT_THD_LOCK_UP, 0x0},
341 {DVBT_THD_LOCK_DW, 0x0},
342 {DVBT_THD_UP1, 0x14},
343 {DVBT_THD_DW1, 0xec},
344 {DVBT_INTER_CNT_LEN, 0xc},
345 {DVBT_GI_PGA_STATE, 0x0},
346 {DVBT_EN_AGC_PGA, 0x1},
349 {DVBT_REG_MONSEL, 0x1},
351 {DVBT_REG_4MSEL, 0x0},
352 {DVBT_SPEC_INV, 0x0},
355 static const struct rtl2832_reg_value rtl2832_tuner_init_r820t[] = {
356 {DVBT_DAGC_TRG_VAL, 0x39},
357 {DVBT_AGC_TARG_VAL_0, 0x0},
358 {DVBT_AGC_TARG_VAL_8_1, 0x40},
359 {DVBT_AAGC_LOOP_GAIN, 0x16},
360 {DVBT_LOOP_GAIN2_3_0, 0x8},
361 {DVBT_LOOP_GAIN2_4, 0x1},
362 {DVBT_LOOP_GAIN3, 0x18},
370 {DVBT_IF_AGC_MIN, 0x80},
371 {DVBT_IF_AGC_MAX, 0x7f},
372 {DVBT_RF_AGC_MIN, 0x80},
373 {DVBT_RF_AGC_MAX, 0x7f},
374 {DVBT_POLAR_RF_AGC, 0x0},
375 {DVBT_POLAR_IF_AGC, 0x0},
376 {DVBT_AD7_SETTING, 0xe9f4},
377 {DVBT_SPEC_INV, 0x1},
380 #endif /* RTL2832_PRIV_H */