2 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Interrupt architecture for the GIC:
10 * o There is one Interrupt Distributor, which receives interrupts
11 * from system devices and sends them to the Interrupt Controllers.
13 * o There is one CPU Interface per CPU, which sends interrupts sent
14 * by the Distributor, and interrupts generated locally, to the
15 * associated CPU. The base address of the CPU interface is usually
16 * aliased so that the same address points to different chips depending
17 * on the CPU it is accessed from.
19 * Note that IRQs 0-31 are special - they are local to each CPU.
20 * As such, the enable set/clear, pending set/clear and active bit
21 * registers are banked per-cpu for these sources.
23 #include <linux/init.h>
24 #include <linux/kernel.h>
25 #include <linux/err.h>
26 #include <linux/module.h>
27 #include <linux/list.h>
28 #include <linux/smp.h>
29 #include <linux/cpu.h>
30 #include <linux/cpu_pm.h>
31 #include <linux/cpumask.h>
34 #include <linux/of_address.h>
35 #include <linux/of_irq.h>
36 #include <linux/acpi.h>
37 #include <linux/irqdomain.h>
38 #include <linux/interrupt.h>
39 #include <linux/percpu.h>
40 #include <linux/slab.h>
41 #include <linux/irqchip.h>
42 #include <linux/irqchip/chained_irq.h>
43 #include <linux/irqchip/arm-gic.h>
45 #include <asm/cputype.h>
47 #include <asm/exception.h>
48 #include <asm/smp_plat.h>
51 #include "irq-gic-common.h"
54 #include <asm/cpufeature.h>
56 static void gic_check_cpu_features(void)
58 WARN_TAINT_ONCE(cpus_have_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
59 TAINT_CPU_OUT_OF_SPEC,
60 "GICv3 system registers enabled, broken firmware!\n");
63 #define gic_check_cpu_features() do { } while(0)
67 void __iomem *common_base;
68 void __percpu * __iomem *percpu_base;
71 struct gic_chip_data {
72 union gic_base dist_base;
73 union gic_base cpu_base;
75 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
76 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
77 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
78 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
79 u32 __percpu *saved_ppi_enable;
80 u32 __percpu *saved_ppi_active;
81 u32 __percpu *saved_ppi_conf;
83 struct irq_domain *domain;
84 unsigned int gic_irqs;
85 #ifdef CONFIG_GIC_NON_BANKED
86 void __iomem *(*get_base)(union gic_base *);
90 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
93 * The GIC mapping of CPU interfaces does not necessarily match
94 * the logical CPU numbering. Let's use a mapping as returned
97 #define NR_GIC_CPU_IF 8
98 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
100 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
106 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
108 #ifdef CONFIG_GIC_NON_BANKED
109 static void __iomem *gic_get_percpu_base(union gic_base *base)
111 return raw_cpu_read(*base->percpu_base);
114 static void __iomem *gic_get_common_base(union gic_base *base)
116 return base->common_base;
119 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
121 return data->get_base(&data->dist_base);
124 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
126 return data->get_base(&data->cpu_base);
129 static inline void gic_set_base_accessor(struct gic_chip_data *data,
130 void __iomem *(*f)(union gic_base *))
135 #define gic_data_dist_base(d) ((d)->dist_base.common_base)
136 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
137 #define gic_set_base_accessor(d, f)
140 static inline void __iomem *gic_dist_base(struct irq_data *d)
142 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
143 return gic_data_dist_base(gic_data);
146 static inline void __iomem *gic_cpu_base(struct irq_data *d)
148 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
149 return gic_data_cpu_base(gic_data);
152 static inline unsigned int gic_irq(struct irq_data *d)
157 static inline bool cascading_gic_irq(struct irq_data *d)
159 void *data = irq_data_get_irq_handler_data(d);
162 * If handler_data is set, this is a cascading interrupt, and
163 * it cannot possibly be forwarded.
169 * Routines to acknowledge, disable and enable interrupts
171 static void gic_poke_irq(struct irq_data *d, u32 offset)
173 u32 mask = 1 << (gic_irq(d) % 32);
174 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
177 static int gic_peek_irq(struct irq_data *d, u32 offset)
179 u32 mask = 1 << (gic_irq(d) % 32);
180 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
183 static void gic_mask_irq(struct irq_data *d)
185 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
188 static void gic_eoimode1_mask_irq(struct irq_data *d)
192 * When masking a forwarded interrupt, make sure it is
193 * deactivated as well.
195 * This ensures that an interrupt that is getting
196 * disabled/masked will not get "stuck", because there is
197 * noone to deactivate it (guest is being terminated).
199 if (irqd_is_forwarded_to_vcpu(d))
200 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
203 static void gic_unmask_irq(struct irq_data *d)
205 gic_poke_irq(d, GIC_DIST_ENABLE_SET);
208 static void gic_eoi_irq(struct irq_data *d)
210 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
213 static void gic_eoimode1_eoi_irq(struct irq_data *d)
215 /* Do not deactivate an IRQ forwarded to a vcpu. */
216 if (irqd_is_forwarded_to_vcpu(d))
219 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
222 static int gic_irq_set_irqchip_state(struct irq_data *d,
223 enum irqchip_irq_state which, bool val)
228 case IRQCHIP_STATE_PENDING:
229 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
232 case IRQCHIP_STATE_ACTIVE:
233 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
236 case IRQCHIP_STATE_MASKED:
237 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
244 gic_poke_irq(d, reg);
248 static int gic_irq_get_irqchip_state(struct irq_data *d,
249 enum irqchip_irq_state which, bool *val)
252 case IRQCHIP_STATE_PENDING:
253 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
256 case IRQCHIP_STATE_ACTIVE:
257 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
260 case IRQCHIP_STATE_MASKED:
261 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
271 static int gic_set_type(struct irq_data *d, unsigned int type)
273 void __iomem *base = gic_dist_base(d);
274 unsigned int gicirq = gic_irq(d);
276 /* Interrupt configuration for SGIs can't be changed */
280 /* SPIs have restrictions on the supported types */
281 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
282 type != IRQ_TYPE_EDGE_RISING)
285 return gic_configure_irq(gicirq, type, base, NULL);
288 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
290 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
291 if (cascading_gic_irq(d))
295 irqd_set_forwarded_to_vcpu(d);
297 irqd_clr_forwarded_to_vcpu(d);
302 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
305 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
306 unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
311 cpu = cpumask_any_and(mask_val, cpu_online_mask);
313 cpu = cpumask_first(mask_val);
315 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
318 raw_spin_lock_irqsave(&irq_controller_lock, flags);
319 mask = 0xff << shift;
320 bit = gic_cpu_map[cpu] << shift;
321 val = readl_relaxed(reg) & ~mask;
322 writel_relaxed(val | bit, reg);
323 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
325 return IRQ_SET_MASK_OK;
329 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
332 struct gic_chip_data *gic = &gic_data[0];
333 void __iomem *cpu_base = gic_data_cpu_base(gic);
336 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
337 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
339 if (likely(irqnr > 15 && irqnr < 1021)) {
340 if (static_key_true(&supports_deactivate))
341 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
342 handle_domain_irq(gic->domain, irqnr, regs);
346 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
347 if (static_key_true(&supports_deactivate))
348 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
351 * Ensure any shared data written by the CPU sending
352 * the IPI is read after we've read the ACK register
355 * Pairs with the write barrier in gic_raise_softirq
358 handle_IPI(irqnr, regs);
366 static void gic_handle_cascade_irq(struct irq_desc *desc)
368 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
369 struct irq_chip *chip = irq_desc_get_chip(desc);
370 unsigned int cascade_irq, gic_irq;
371 unsigned long status;
373 chained_irq_enter(chip, desc);
375 raw_spin_lock(&irq_controller_lock);
376 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
377 raw_spin_unlock(&irq_controller_lock);
379 gic_irq = (status & GICC_IAR_INT_ID_MASK);
380 if (gic_irq == GICC_INT_SPURIOUS)
383 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
384 if (unlikely(gic_irq < 32 || gic_irq > 1020))
385 handle_bad_irq(desc);
387 generic_handle_irq(cascade_irq);
390 chained_irq_exit(chip, desc);
393 static struct irq_chip gic_chip = {
395 .irq_mask = gic_mask_irq,
396 .irq_unmask = gic_unmask_irq,
397 .irq_eoi = gic_eoi_irq,
398 .irq_set_type = gic_set_type,
400 .irq_set_affinity = gic_set_affinity,
402 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
403 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
404 .flags = IRQCHIP_SET_TYPE_MASKED |
405 IRQCHIP_SKIP_SET_WAKE |
406 IRQCHIP_MASK_ON_SUSPEND,
409 static struct irq_chip gic_eoimode1_chip = {
411 .irq_mask = gic_eoimode1_mask_irq,
412 .irq_unmask = gic_unmask_irq,
413 .irq_eoi = gic_eoimode1_eoi_irq,
414 .irq_set_type = gic_set_type,
416 .irq_set_affinity = gic_set_affinity,
418 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
419 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
420 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
421 .flags = IRQCHIP_SET_TYPE_MASKED |
422 IRQCHIP_SKIP_SET_WAKE |
423 IRQCHIP_MASK_ON_SUSPEND,
426 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
428 if (gic_nr >= MAX_GIC_NR)
430 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
434 static u8 gic_get_cpumask(struct gic_chip_data *gic)
436 void __iomem *base = gic_data_dist_base(gic);
439 for (i = mask = 0; i < 32; i += 4) {
440 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
447 if (!mask && num_possible_cpus() > 1)
448 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
453 static void gic_cpu_if_up(struct gic_chip_data *gic)
455 void __iomem *cpu_base = gic_data_cpu_base(gic);
459 if (static_key_true(&supports_deactivate))
460 mode = GIC_CPU_CTRL_EOImodeNS;
463 * Preserve bypass disable bits to be written back later
465 bypass = readl(cpu_base + GIC_CPU_CTRL);
466 bypass &= GICC_DIS_BYPASS_MASK;
468 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
472 static void __init gic_dist_init(struct gic_chip_data *gic)
476 unsigned int gic_irqs = gic->gic_irqs;
477 void __iomem *base = gic_data_dist_base(gic);
479 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
482 * Set all global interrupts to this CPU only.
484 cpumask = gic_get_cpumask(gic);
485 cpumask |= cpumask << 8;
486 cpumask |= cpumask << 16;
487 for (i = 32; i < gic_irqs; i += 4)
488 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
490 gic_dist_config(base, gic_irqs, NULL);
492 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
495 static void gic_cpu_init(struct gic_chip_data *gic)
497 void __iomem *dist_base = gic_data_dist_base(gic);
498 void __iomem *base = gic_data_cpu_base(gic);
499 unsigned int cpu_mask, cpu = smp_processor_id();
503 * Setting up the CPU map is only relevant for the primary GIC
504 * because any nested/secondary GICs do not directly interface
507 if (gic == &gic_data[0]) {
509 * Get what the GIC says our CPU mask is.
511 BUG_ON(cpu >= NR_GIC_CPU_IF);
512 cpu_mask = gic_get_cpumask(gic);
513 gic_cpu_map[cpu] = cpu_mask;
516 * Clear our mask from the other map entries in case they're
519 for (i = 0; i < NR_GIC_CPU_IF; i++)
521 gic_cpu_map[i] &= ~cpu_mask;
524 gic_cpu_config(dist_base, NULL);
526 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
530 int gic_cpu_if_down(unsigned int gic_nr)
532 void __iomem *cpu_base;
535 if (gic_nr >= MAX_GIC_NR)
538 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
539 val = readl(cpu_base + GIC_CPU_CTRL);
541 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
548 * Saves the GIC distributor registers during suspend or idle. Must be called
549 * with interrupts disabled but before powering down the GIC. After calling
550 * this function, no interrupts will be delivered by the GIC, and another
551 * platform-specific wakeup source must be enabled.
553 static void gic_dist_save(unsigned int gic_nr)
555 unsigned int gic_irqs;
556 void __iomem *dist_base;
559 if (gic_nr >= MAX_GIC_NR)
562 gic_irqs = gic_data[gic_nr].gic_irqs;
563 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
568 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
569 gic_data[gic_nr].saved_spi_conf[i] =
570 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
572 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
573 gic_data[gic_nr].saved_spi_target[i] =
574 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
576 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
577 gic_data[gic_nr].saved_spi_enable[i] =
578 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
580 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
581 gic_data[gic_nr].saved_spi_active[i] =
582 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
586 * Restores the GIC distributor registers during resume or when coming out of
587 * idle. Must be called before enabling interrupts. If a level interrupt
588 * that occured while the GIC was suspended is still present, it will be
589 * handled normally, but any edge interrupts that occured will not be seen by
590 * the GIC and need to be handled by the platform-specific wakeup source.
592 static void gic_dist_restore(unsigned int gic_nr)
594 unsigned int gic_irqs;
596 void __iomem *dist_base;
598 if (gic_nr >= MAX_GIC_NR)
601 gic_irqs = gic_data[gic_nr].gic_irqs;
602 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
607 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
609 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
610 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
611 dist_base + GIC_DIST_CONFIG + i * 4);
613 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
614 writel_relaxed(GICD_INT_DEF_PRI_X4,
615 dist_base + GIC_DIST_PRI + i * 4);
617 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
618 writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
619 dist_base + GIC_DIST_TARGET + i * 4);
621 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
622 writel_relaxed(GICD_INT_EN_CLR_X32,
623 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
624 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
625 dist_base + GIC_DIST_ENABLE_SET + i * 4);
628 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
629 writel_relaxed(GICD_INT_EN_CLR_X32,
630 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
631 writel_relaxed(gic_data[gic_nr].saved_spi_active[i],
632 dist_base + GIC_DIST_ACTIVE_SET + i * 4);
635 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
638 static void gic_cpu_save(unsigned int gic_nr)
642 void __iomem *dist_base;
643 void __iomem *cpu_base;
645 if (gic_nr >= MAX_GIC_NR)
648 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
649 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
651 if (!dist_base || !cpu_base)
654 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
655 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
656 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
658 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_active);
659 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
660 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
662 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
663 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
664 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
668 static void gic_cpu_restore(unsigned int gic_nr)
672 void __iomem *dist_base;
673 void __iomem *cpu_base;
675 if (gic_nr >= MAX_GIC_NR)
678 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
679 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
681 if (!dist_base || !cpu_base)
684 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
685 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
686 writel_relaxed(GICD_INT_EN_CLR_X32,
687 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
688 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
691 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_active);
692 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
693 writel_relaxed(GICD_INT_EN_CLR_X32,
694 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
695 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
698 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
699 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
700 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
702 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
703 writel_relaxed(GICD_INT_DEF_PRI_X4,
704 dist_base + GIC_DIST_PRI + i * 4);
706 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
707 gic_cpu_if_up(&gic_data[gic_nr]);
710 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
714 for (i = 0; i < MAX_GIC_NR; i++) {
715 #ifdef CONFIG_GIC_NON_BANKED
716 /* Skip over unused GICs */
717 if (!gic_data[i].get_base)
724 case CPU_PM_ENTER_FAILED:
728 case CPU_CLUSTER_PM_ENTER:
731 case CPU_CLUSTER_PM_ENTER_FAILED:
732 case CPU_CLUSTER_PM_EXIT:
741 static struct notifier_block gic_notifier_block = {
742 .notifier_call = gic_notifier,
745 static void __init gic_pm_init(struct gic_chip_data *gic)
747 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
749 BUG_ON(!gic->saved_ppi_enable);
751 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
753 BUG_ON(!gic->saved_ppi_active);
755 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
757 BUG_ON(!gic->saved_ppi_conf);
759 if (gic == &gic_data[0])
760 cpu_pm_register_notifier(&gic_notifier_block);
763 static void __init gic_pm_init(struct gic_chip_data *gic)
769 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
772 unsigned long flags, map = 0;
774 raw_spin_lock_irqsave(&irq_controller_lock, flags);
776 /* Convert our logical CPU mask into a physical one. */
777 for_each_cpu(cpu, mask)
778 map |= gic_cpu_map[cpu];
781 * Ensure that stores to Normal memory are visible to the
782 * other CPUs before they observe us issuing the IPI.
786 /* this always happens on GIC0 */
787 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
789 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
793 #ifdef CONFIG_BL_SWITCHER
795 * gic_send_sgi - send a SGI directly to given CPU interface number
797 * cpu_id: the ID for the destination CPU interface
798 * irq: the IPI number to send a SGI for
800 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
802 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
803 cpu_id = 1 << cpu_id;
804 /* this always happens on GIC0 */
805 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
809 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
811 * @cpu: the logical CPU number to get the GIC ID for.
813 * Return the CPU interface ID for the given logical CPU number,
814 * or -1 if the CPU number is too large or the interface ID is
815 * unknown (more than one bit set).
817 int gic_get_cpu_id(unsigned int cpu)
819 unsigned int cpu_bit;
821 if (cpu >= NR_GIC_CPU_IF)
823 cpu_bit = gic_cpu_map[cpu];
824 if (cpu_bit & (cpu_bit - 1))
826 return __ffs(cpu_bit);
830 * gic_migrate_target - migrate IRQs to another CPU interface
832 * @new_cpu_id: the CPU target ID to migrate IRQs to
834 * Migrate all peripheral interrupts with a target matching the current CPU
835 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
836 * is also updated. Targets to other CPU interfaces are unchanged.
837 * This must be called with IRQs locally disabled.
839 void gic_migrate_target(unsigned int new_cpu_id)
841 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
842 void __iomem *dist_base;
843 int i, ror_val, cpu = smp_processor_id();
844 u32 val, cur_target_mask, active_mask;
846 if (gic_nr >= MAX_GIC_NR)
849 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
852 gic_irqs = gic_data[gic_nr].gic_irqs;
854 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
855 cur_target_mask = 0x01010101 << cur_cpu_id;
856 ror_val = (cur_cpu_id - new_cpu_id) & 31;
858 raw_spin_lock(&irq_controller_lock);
860 /* Update the target interface for this logical CPU */
861 gic_cpu_map[cpu] = 1 << new_cpu_id;
864 * Find all the peripheral interrupts targetting the current
865 * CPU interface and migrate them to the new CPU interface.
866 * We skip DIST_TARGET 0 to 7 as they are read-only.
868 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
869 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
870 active_mask = val & cur_target_mask;
873 val |= ror32(active_mask, ror_val);
874 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
878 raw_spin_unlock(&irq_controller_lock);
881 * Now let's migrate and clear any potential SGIs that might be
882 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
883 * is a banked register, we can only forward the SGI using
884 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
885 * doesn't use that information anyway.
887 * For the same reason we do not adjust SGI source information
888 * for previously sent SGIs by us to other CPUs either.
890 for (i = 0; i < 16; i += 4) {
892 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
895 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
896 for (j = i; j < i + 4; j++) {
898 writel_relaxed((1 << (new_cpu_id + 16)) | j,
899 dist_base + GIC_DIST_SOFTINT);
906 * gic_get_sgir_physaddr - get the physical address for the SGI register
908 * REturn the physical address of the SGI register to be used
909 * by some early assembly code when the kernel is not yet available.
911 static unsigned long gic_dist_physaddr;
913 unsigned long gic_get_sgir_physaddr(void)
915 if (!gic_dist_physaddr)
917 return gic_dist_physaddr + GIC_DIST_SOFTINT;
920 void __init gic_init_physaddr(struct device_node *node)
923 if (of_address_to_resource(node, 0, &res) == 0) {
924 gic_dist_physaddr = res.start;
925 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
930 #define gic_init_physaddr(node) do { } while (0)
933 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
936 struct irq_chip *chip = &gic_chip;
938 if (static_key_true(&supports_deactivate)) {
939 if (d->host_data == (void *)&gic_data[0])
940 chip = &gic_eoimode1_chip;
944 irq_set_percpu_devid(irq);
945 irq_domain_set_info(d, irq, hw, chip, d->host_data,
946 handle_percpu_devid_irq, NULL, NULL);
947 irq_set_status_flags(irq, IRQ_NOAUTOEN);
949 irq_domain_set_info(d, irq, hw, chip, d->host_data,
950 handle_fasteoi_irq, NULL, NULL);
956 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
960 static int gic_irq_domain_translate(struct irq_domain *d,
961 struct irq_fwspec *fwspec,
962 unsigned long *hwirq,
965 if (is_of_node(fwspec->fwnode)) {
966 if (fwspec->param_count < 3)
969 /* Get the interrupt number and add 16 to skip over SGIs */
970 *hwirq = fwspec->param[1] + 16;
973 * For SPIs, we need to add 16 more to get the GIC irq
976 if (!fwspec->param[0])
979 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
983 if (fwspec->fwnode->type == FWNODE_IRQCHIP) {
984 if(fwspec->param_count != 2)
987 *hwirq = fwspec->param[0];
988 *type = fwspec->param[1];
996 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action,
999 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
1000 gic_cpu_init(&gic_data[0]);
1005 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
1006 * priority because the GIC needs to be up before the ARM generic timers.
1008 static struct notifier_block gic_cpu_notifier = {
1009 .notifier_call = gic_secondary_init,
1014 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1015 unsigned int nr_irqs, void *arg)
1018 irq_hw_number_t hwirq;
1019 unsigned int type = IRQ_TYPE_NONE;
1020 struct irq_fwspec *fwspec = arg;
1022 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1026 for (i = 0; i < nr_irqs; i++)
1027 gic_irq_domain_map(domain, virq + i, hwirq + i);
1032 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
1033 .translate = gic_irq_domain_translate,
1034 .alloc = gic_irq_domain_alloc,
1035 .free = irq_domain_free_irqs_top,
1038 static const struct irq_domain_ops gic_irq_domain_ops = {
1039 .map = gic_irq_domain_map,
1040 .unmap = gic_irq_domain_unmap,
1043 static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
1044 void __iomem *dist_base, void __iomem *cpu_base,
1045 u32 percpu_offset, struct fwnode_handle *handle)
1047 irq_hw_number_t hwirq_base;
1048 struct gic_chip_data *gic;
1049 int gic_irqs, irq_base, i;
1051 BUG_ON(gic_nr >= MAX_GIC_NR);
1053 gic_check_cpu_features();
1055 gic = &gic_data[gic_nr];
1056 #ifdef CONFIG_GIC_NON_BANKED
1057 if (percpu_offset) { /* Frankein-GIC without banked registers... */
1060 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1061 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1062 if (WARN_ON(!gic->dist_base.percpu_base ||
1063 !gic->cpu_base.percpu_base)) {
1064 free_percpu(gic->dist_base.percpu_base);
1065 free_percpu(gic->cpu_base.percpu_base);
1069 for_each_possible_cpu(cpu) {
1070 u32 mpidr = cpu_logical_map(cpu);
1071 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1072 unsigned long offset = percpu_offset * core_id;
1073 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
1074 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
1077 gic_set_base_accessor(gic, gic_get_percpu_base);
1080 { /* Normal, sane GIC... */
1082 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1084 gic->dist_base.common_base = dist_base;
1085 gic->cpu_base.common_base = cpu_base;
1086 gic_set_base_accessor(gic, gic_get_common_base);
1090 * Find out how many interrupts are supported.
1091 * The GIC only supports up to 1020 interrupt sources.
1093 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1094 gic_irqs = (gic_irqs + 1) * 32;
1095 if (gic_irqs > 1020)
1097 gic->gic_irqs = gic_irqs;
1099 if (handle) { /* DT/ACPI */
1100 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1101 &gic_irq_domain_hierarchy_ops,
1103 } else { /* Legacy support */
1105 * For primary GICs, skip over SGIs.
1106 * For secondary GICs, skip over PPIs, too.
1108 if (gic_nr == 0 && (irq_start & 31) > 0) {
1110 if (irq_start != -1)
1111 irq_start = (irq_start & ~31) + 16;
1116 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
1118 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1120 if (IS_ERR_VALUE(irq_base)) {
1121 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1123 irq_base = irq_start;
1126 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1127 hwirq_base, &gic_irq_domain_ops, gic);
1130 if (WARN_ON(!gic->domain))
1135 * Initialize the CPU interface map to all CPUs.
1136 * It will be refined as each CPU probes its ID.
1137 * This is only necessary for the primary GIC.
1139 for (i = 0; i < NR_GIC_CPU_IF; i++)
1140 gic_cpu_map[i] = 0xff;
1142 set_smp_cross_call(gic_raise_softirq);
1143 register_cpu_notifier(&gic_cpu_notifier);
1145 set_handle_irq(gic_handle_irq);
1146 if (static_key_true(&supports_deactivate))
1147 pr_info("GIC: Using split EOI/Deactivate mode\n");
1155 void __init gic_init(unsigned int gic_nr, int irq_start,
1156 void __iomem *dist_base, void __iomem *cpu_base)
1159 * Non-DT/ACPI systems won't run a hypervisor, so let's not
1160 * bother with these...
1162 static_key_slow_dec(&supports_deactivate);
1163 __gic_init_bases(gic_nr, irq_start, dist_base, cpu_base, 0, NULL);
1167 static int gic_cnt __initdata;
1169 static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1171 struct resource cpuif_res;
1173 of_address_to_resource(node, 1, &cpuif_res);
1175 if (!is_hyp_mode_available())
1177 if (resource_size(&cpuif_res) < SZ_8K)
1179 if (resource_size(&cpuif_res) == SZ_128K) {
1180 u32 val_low, val_high;
1183 * Verify that we have the first 4kB of a GIC400
1184 * aliased over the first 64kB by checking the
1185 * GICC_IIDR register on both ends.
1187 val_low = readl_relaxed(*base + GIC_CPU_IDENT);
1188 val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000);
1189 if ((val_low & 0xffff0fff) != 0x0202043B ||
1190 val_low != val_high)
1194 * Move the base up by 60kB, so that we have a 8kB
1195 * contiguous region, which allows us to use GICC_DIR
1196 * at its normal offset. Please pass me that bucket.
1199 cpuif_res.start += 0xf000;
1200 pr_warn("GIC: Adjusting CPU interface base to %pa",
1208 gic_of_init(struct device_node *node, struct device_node *parent)
1210 void __iomem *cpu_base;
1211 void __iomem *dist_base;
1218 dist_base = of_iomap(node, 0);
1219 WARN(!dist_base, "unable to map gic dist registers\n");
1221 cpu_base = of_iomap(node, 1);
1222 WARN(!cpu_base, "unable to map gic cpu registers\n");
1225 * Disable split EOI/Deactivate if either HYP is not available
1226 * or the CPU interface is too small.
1228 if (gic_cnt == 0 && !gic_check_eoimode(node, &cpu_base))
1229 static_key_slow_dec(&supports_deactivate);
1231 if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
1234 __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset,
1237 gic_init_physaddr(node);
1240 irq = irq_of_parse_and_map(node, 0);
1241 gic_cascade_irq(gic_cnt, irq);
1244 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1245 gicv2m_of_init(node, gic_data[gic_cnt].domain);
1250 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1251 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1252 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1253 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1254 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1255 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1256 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1257 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1258 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1263 static phys_addr_t cpu_phy_base __initdata;
1266 gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
1267 const unsigned long end)
1269 struct acpi_madt_generic_interrupt *processor;
1270 phys_addr_t gic_cpu_base;
1271 static int cpu_base_assigned;
1273 processor = (struct acpi_madt_generic_interrupt *)header;
1275 if (BAD_MADT_GICC_ENTRY(processor, end))
1279 * There is no support for non-banked GICv1/2 register in ACPI spec.
1280 * All CPU interface addresses have to be the same.
1282 gic_cpu_base = processor->base_address;
1283 if (cpu_base_assigned && gic_cpu_base != cpu_phy_base)
1286 cpu_phy_base = gic_cpu_base;
1287 cpu_base_assigned = 1;
1291 /* The things you have to do to just *count* something... */
1292 static int __init acpi_dummy_func(struct acpi_subtable_header *header,
1293 const unsigned long end)
1298 static bool __init acpi_gic_redist_is_present(void)
1300 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1301 acpi_dummy_func, 0) > 0;
1304 static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1305 struct acpi_probe_entry *ape)
1307 struct acpi_madt_generic_distributor *dist;
1308 dist = (struct acpi_madt_generic_distributor *)header;
1310 return (dist->version == ape->driver_data &&
1311 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1312 !acpi_gic_redist_is_present()));
1315 #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
1316 #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
1318 static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
1319 const unsigned long end)
1321 struct acpi_madt_generic_distributor *dist;
1322 void __iomem *cpu_base, *dist_base;
1323 struct fwnode_handle *domain_handle;
1326 /* Collect CPU base addresses */
1327 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1328 gic_acpi_parse_madt_cpu, 0);
1330 pr_err("No valid GICC entries exist\n");
1334 cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1336 pr_err("Unable to map GICC registers\n");
1340 dist = (struct acpi_madt_generic_distributor *)header;
1341 dist_base = ioremap(dist->base_address, ACPI_GICV2_DIST_MEM_SIZE);
1343 pr_err("Unable to map GICD registers\n");
1349 * Disable split EOI/Deactivate if HYP is not available. ACPI
1350 * guarantees that we'll always have a GICv2, so the CPU
1351 * interface will always be the right size.
1353 if (!is_hyp_mode_available())
1354 static_key_slow_dec(&supports_deactivate);
1357 * Initialize GIC instance zero (no multi-GIC support).
1359 domain_handle = irq_domain_alloc_fwnode(dist_base);
1360 if (!domain_handle) {
1361 pr_err("Unable to allocate domain handle\n");
1367 __gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle);
1369 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1372 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1373 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1375 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1376 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,