2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "changf100.h"
27 #include <core/client.h>
28 #include <core/enum.h>
29 #include <core/gpuobj.h>
30 #include <subdev/bar.h>
31 #include <engine/sw.h>
33 #include <nvif/class.h>
36 gf100_fifo_uevent_init(struct nvkm_fifo *fifo)
38 struct nvkm_device *device = fifo->engine.subdev.device;
39 nvkm_mask(device, 0x002140, 0x80000000, 0x80000000);
43 gf100_fifo_uevent_fini(struct nvkm_fifo *fifo)
45 struct nvkm_device *device = fifo->engine.subdev.device;
46 nvkm_mask(device, 0x002140, 0x80000000, 0x00000000);
50 gf100_fifo_runlist_update(struct gf100_fifo *fifo)
52 struct gf100_fifo_chan *chan;
53 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
54 struct nvkm_device *device = subdev->device;
55 struct nvkm_memory *cur;
58 mutex_lock(&subdev->mutex);
59 cur = fifo->runlist.mem[fifo->runlist.active];
60 fifo->runlist.active = !fifo->runlist.active;
63 list_for_each_entry(chan, &fifo->chan, head) {
64 nvkm_wo32(cur, (nr * 8) + 0, chan->base.chid);
65 nvkm_wo32(cur, (nr * 8) + 4, 0x00000004);
70 nvkm_wr32(device, 0x002270, nvkm_memory_addr(cur) >> 12);
71 nvkm_wr32(device, 0x002274, 0x01f00000 | nr);
73 if (wait_event_timeout(fifo->runlist.wait,
74 !(nvkm_rd32(device, 0x00227c) & 0x00100000),
75 msecs_to_jiffies(2000)) == 0)
76 nvkm_error(subdev, "runlist update timeout\n");
77 mutex_unlock(&subdev->mutex);
81 gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn)
84 case NVKM_ENGINE_GR : engn = 0; break;
85 case NVKM_ENGINE_MSVLD : engn = 1; break;
86 case NVKM_ENGINE_MSPPP : engn = 2; break;
87 case NVKM_ENGINE_MSPDEC: engn = 3; break;
88 case NVKM_ENGINE_CE0 : engn = 4; break;
89 case NVKM_ENGINE_CE1 : engn = 5; break;
97 static inline struct nvkm_engine *
98 gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn)
100 struct nvkm_device *device = fifo->base.engine.subdev.device;
103 case 0: engn = NVKM_ENGINE_GR; break;
104 case 1: engn = NVKM_ENGINE_MSVLD; break;
105 case 2: engn = NVKM_ENGINE_MSPPP; break;
106 case 3: engn = NVKM_ENGINE_MSPDEC; break;
107 case 4: engn = NVKM_ENGINE_CE0; break;
108 case 5: engn = NVKM_ENGINE_CE1; break;
113 return nvkm_device_engine(device, engn);
117 gf100_fifo_recover_work(struct work_struct *work)
119 struct gf100_fifo *fifo = container_of(work, typeof(*fifo), fault);
120 struct nvkm_device *device = fifo->base.engine.subdev.device;
121 struct nvkm_engine *engine;
126 spin_lock_irqsave(&fifo->base.lock, flags);
129 spin_unlock_irqrestore(&fifo->base.lock, flags);
131 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn))
132 engm |= 1 << gf100_fifo_engidx(fifo, engn);
133 nvkm_mask(device, 0x002630, engm, engm);
135 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
136 if ((engine = nvkm_device_engine(device, engn))) {
137 nvkm_subdev_fini(&engine->subdev, false);
138 WARN_ON(nvkm_subdev_init(&engine->subdev));
142 gf100_fifo_runlist_update(fifo);
143 nvkm_wr32(device, 0x00262c, engm);
144 nvkm_mask(device, 0x002630, engm, 0x00000000);
148 gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine,
149 struct gf100_fifo_chan *chan)
151 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
152 struct nvkm_device *device = subdev->device;
153 u32 chid = chan->base.chid;
155 nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n",
156 nvkm_subdev_name[engine->subdev.index], chid);
157 assert_spin_locked(&fifo->base.lock);
159 nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000);
160 list_del_init(&chan->head);
163 fifo->mask |= 1ULL << engine->subdev.index;
164 schedule_work(&fifo->fault);
167 static const struct nvkm_enum
168 gf100_fifo_sched_reason[] = {
169 { 0x0a, "CTXSW_TIMEOUT" },
174 gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo)
176 struct nvkm_device *device = fifo->base.engine.subdev.device;
177 struct nvkm_engine *engine;
178 struct gf100_fifo_chan *chan;
182 spin_lock_irqsave(&fifo->base.lock, flags);
183 for (engn = 0; engn < 6; engn++) {
184 u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04));
185 u32 busy = (stat & 0x80000000);
186 u32 save = (stat & 0x00100000); /* maybe? */
187 u32 unk0 = (stat & 0x00040000);
188 u32 unk1 = (stat & 0x00001000);
189 u32 chid = (stat & 0x0000007f);
192 if (busy && unk0 && unk1) {
193 list_for_each_entry(chan, &fifo->chan, head) {
194 if (chan->base.chid == chid) {
195 engine = gf100_fifo_engine(fifo, engn);
198 gf100_fifo_recover(fifo, engine, chan);
204 spin_unlock_irqrestore(&fifo->base.lock, flags);
208 gf100_fifo_intr_sched(struct gf100_fifo *fifo)
210 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
211 struct nvkm_device *device = subdev->device;
212 u32 intr = nvkm_rd32(device, 0x00254c);
213 u32 code = intr & 0x000000ff;
214 const struct nvkm_enum *en;
216 en = nvkm_enum_find(gf100_fifo_sched_reason, code);
218 nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : "");
222 gf100_fifo_intr_sched_ctxsw(fifo);
229 static const struct nvkm_enum
230 gf100_fifo_fault_engine[] = {
231 { 0x00, "PGRAPH", NULL, NVKM_ENGINE_GR },
232 { 0x03, "PEEPHOLE", NULL, NVKM_ENGINE_IFB },
233 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
234 { 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM },
235 { 0x07, "PFIFO", NULL, NVKM_ENGINE_FIFO },
236 { 0x10, "PMSVLD", NULL, NVKM_ENGINE_MSVLD },
237 { 0x11, "PMSPPP", NULL, NVKM_ENGINE_MSPPP },
238 { 0x13, "PCOUNTER" },
239 { 0x14, "PMSPDEC", NULL, NVKM_ENGINE_MSPDEC },
240 { 0x15, "PCE0", NULL, NVKM_ENGINE_CE0 },
241 { 0x16, "PCE1", NULL, NVKM_ENGINE_CE1 },
246 static const struct nvkm_enum
247 gf100_fifo_fault_reason[] = {
248 { 0x00, "PT_NOT_PRESENT" },
249 { 0x01, "PT_TOO_SHORT" },
250 { 0x02, "PAGE_NOT_PRESENT" },
251 { 0x03, "VM_LIMIT_EXCEEDED" },
252 { 0x04, "NO_CHANNEL" },
253 { 0x05, "PAGE_SYSTEM_ONLY" },
254 { 0x06, "PAGE_READ_ONLY" },
255 { 0x0a, "COMPRESSED_SYSRAM" },
256 { 0x0c, "INVALID_STORAGE_TYPE" },
260 static const struct nvkm_enum
261 gf100_fifo_fault_hubclient[] = {
264 { 0x04, "DISPATCH" },
267 { 0x07, "BAR_READ" },
268 { 0x08, "BAR_WRITE" },
272 { 0x11, "PCOUNTER" },
275 { 0x15, "CCACHE_POST" },
279 static const struct nvkm_enum
280 gf100_fifo_fault_gpcclient[] = {
289 gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit)
291 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
292 struct nvkm_device *device = subdev->device;
293 u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
294 u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
295 u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
296 u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10));
297 u32 gpc = (stat & 0x1f000000) >> 24;
298 u32 client = (stat & 0x00001f00) >> 8;
299 u32 write = (stat & 0x00000080);
300 u32 hub = (stat & 0x00000040);
301 u32 reason = (stat & 0x0000000f);
302 const struct nvkm_enum *er, *eu, *ec;
303 struct nvkm_engine *engine = NULL;
304 struct nvkm_fifo_chan *chan;
308 er = nvkm_enum_find(gf100_fifo_fault_reason, reason);
309 eu = nvkm_enum_find(gf100_fifo_fault_engine, unit);
311 ec = nvkm_enum_find(gf100_fifo_fault_hubclient, client);
313 ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, client);
314 snprintf(gpcid, sizeof(gpcid), "GPC%d/", gpc);
319 case NVKM_SUBDEV_BAR:
320 nvkm_mask(device, 0x001704, 0x00000000, 0x00000000);
322 case NVKM_SUBDEV_INSTMEM:
323 nvkm_mask(device, 0x001714, 0x00000000, 0x00000000);
325 case NVKM_ENGINE_IFB:
326 nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
329 engine = nvkm_device_engine(device, eu->data2);
334 chan = nvkm_fifo_chan_inst(&fifo->base, (u64)inst << 12, &flags);
337 "%s fault at %010llx engine %02x [%s] client %02x [%s%s] "
338 "reason %02x [%s] on channel %d [%010llx %s]\n",
339 write ? "write" : "read", (u64)vahi << 32 | valo,
340 unit, eu ? eu->name : "", client, gpcid, ec ? ec->name : "",
341 reason, er ? er->name : "", chan ? chan->chid : -1,
343 chan ? chan->object.client->name : "unknown");
346 gf100_fifo_recover(fifo, engine, (void *)chan);
347 nvkm_fifo_chan_put(&fifo->base, flags, &chan);
350 static const struct nvkm_bitfield
351 gf100_fifo_pbdma_intr[] = {
352 /* { 0x00008000, "" } seen with null ib push */
353 { 0x00200000, "ILLEGAL_MTHD" },
354 { 0x00800000, "EMPTY_SUBC" },
359 gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit)
361 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
362 struct nvkm_device *device = subdev->device;
363 u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000));
364 u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000));
365 u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000));
366 u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0x7f;
367 u32 subc = (addr & 0x00070000) >> 16;
368 u32 mthd = (addr & 0x00003ffc);
369 struct nvkm_fifo_chan *chan;
374 if (stat & 0x00800000) {
376 if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data))
382 nvkm_snprintbf(msg, sizeof(msg), gf100_fifo_pbdma_intr, show);
383 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags);
384 nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%010llx %s] "
385 "subc %d mthd %04x data %08x\n",
386 unit, show, msg, chid, chan ? chan->inst->addr : 0,
387 chan ? chan->object.client->name : "unknown",
389 nvkm_fifo_chan_put(&fifo->base, flags, &chan);
392 nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008);
393 nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat);
397 gf100_fifo_intr_runlist(struct gf100_fifo *fifo)
399 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
400 struct nvkm_device *device = subdev->device;
401 u32 intr = nvkm_rd32(device, 0x002a00);
403 if (intr & 0x10000000) {
404 wake_up(&fifo->runlist.wait);
405 nvkm_wr32(device, 0x002a00, 0x10000000);
410 nvkm_error(subdev, "RUNLIST %08x\n", intr);
411 nvkm_wr32(device, 0x002a00, intr);
416 gf100_fifo_intr_engine_unit(struct gf100_fifo *fifo, int engn)
418 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
419 struct nvkm_device *device = subdev->device;
420 u32 intr = nvkm_rd32(device, 0x0025a8 + (engn * 0x04));
421 u32 inte = nvkm_rd32(device, 0x002628);
424 nvkm_wr32(device, 0x0025a8 + (engn * 0x04), intr);
426 for (unkn = 0; unkn < 8; unkn++) {
427 u32 ints = (intr >> (unkn * 0x04)) & inte;
429 nvkm_fifo_uevent(&fifo->base);
433 nvkm_error(subdev, "ENGINE %d %d %01x",
435 nvkm_mask(device, 0x002628, ints, 0);
441 gf100_fifo_intr_engine(struct gf100_fifo *fifo)
443 struct nvkm_device *device = fifo->base.engine.subdev.device;
444 u32 mask = nvkm_rd32(device, 0x0025a4);
446 u32 unit = __ffs(mask);
447 gf100_fifo_intr_engine_unit(fifo, unit);
448 mask &= ~(1 << unit);
453 gf100_fifo_intr(struct nvkm_fifo *base)
455 struct gf100_fifo *fifo = gf100_fifo(base);
456 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
457 struct nvkm_device *device = subdev->device;
458 u32 mask = nvkm_rd32(device, 0x002140);
459 u32 stat = nvkm_rd32(device, 0x002100) & mask;
461 if (stat & 0x00000001) {
462 u32 intr = nvkm_rd32(device, 0x00252c);
463 nvkm_warn(subdev, "INTR 00000001: %08x\n", intr);
464 nvkm_wr32(device, 0x002100, 0x00000001);
468 if (stat & 0x00000100) {
469 gf100_fifo_intr_sched(fifo);
470 nvkm_wr32(device, 0x002100, 0x00000100);
474 if (stat & 0x00010000) {
475 u32 intr = nvkm_rd32(device, 0x00256c);
476 nvkm_warn(subdev, "INTR 00010000: %08x\n", intr);
477 nvkm_wr32(device, 0x002100, 0x00010000);
481 if (stat & 0x01000000) {
482 u32 intr = nvkm_rd32(device, 0x00258c);
483 nvkm_warn(subdev, "INTR 01000000: %08x\n", intr);
484 nvkm_wr32(device, 0x002100, 0x01000000);
488 if (stat & 0x10000000) {
489 u32 mask = nvkm_rd32(device, 0x00259c);
491 u32 unit = __ffs(mask);
492 gf100_fifo_intr_fault(fifo, unit);
493 nvkm_wr32(device, 0x00259c, (1 << unit));
494 mask &= ~(1 << unit);
499 if (stat & 0x20000000) {
500 u32 mask = nvkm_rd32(device, 0x0025a0);
502 u32 unit = __ffs(mask);
503 gf100_fifo_intr_pbdma(fifo, unit);
504 nvkm_wr32(device, 0x0025a0, (1 << unit));
505 mask &= ~(1 << unit);
510 if (stat & 0x40000000) {
511 gf100_fifo_intr_runlist(fifo);
515 if (stat & 0x80000000) {
516 gf100_fifo_intr_engine(fifo);
521 nvkm_error(subdev, "INTR %08x\n", stat);
522 nvkm_mask(device, 0x002140, stat, 0x00000000);
523 nvkm_wr32(device, 0x002100, stat);
528 gf100_fifo_oneinit(struct nvkm_fifo *base)
530 struct gf100_fifo *fifo = gf100_fifo(base);
531 struct nvkm_device *device = fifo->base.engine.subdev.device;
534 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000,
535 false, &fifo->runlist.mem[0]);
539 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000,
540 false, &fifo->runlist.mem[1]);
544 init_waitqueue_head(&fifo->runlist.wait);
546 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 0x1000,
547 0x1000, false, &fifo->user.mem);
551 ret = nvkm_bar_umap(device->bar, 128 * 0x1000, 12, &fifo->user.bar);
555 nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0);
560 gf100_fifo_fini(struct nvkm_fifo *base)
562 struct gf100_fifo *fifo = gf100_fifo(base);
563 flush_work(&fifo->fault);
567 gf100_fifo_init(struct nvkm_fifo *base)
569 struct gf100_fifo *fifo = gf100_fifo(base);
570 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
571 struct nvkm_device *device = subdev->device;
574 nvkm_wr32(device, 0x000204, 0xffffffff);
575 nvkm_wr32(device, 0x002204, 0xffffffff);
577 fifo->spoon_nr = hweight32(nvkm_rd32(device, 0x002204));
578 nvkm_debug(subdev, "%d PBDMA unit(s)\n", fifo->spoon_nr);
580 /* assign engines to PBDMAs */
581 if (fifo->spoon_nr >= 3) {
582 nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */
583 nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */
584 nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */
585 nvkm_wr32(device, 0x002214, ~(1 << 1)); /* PMSVLD */
586 nvkm_wr32(device, 0x002218, ~(1 << 2)); /* PCE0 */
587 nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */
591 for (i = 0; i < fifo->spoon_nr; i++) {
592 nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
593 nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
594 nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
597 nvkm_mask(device, 0x002200, 0x00000001, 0x00000001);
598 nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12);
600 nvkm_wr32(device, 0x002100, 0xffffffff);
601 nvkm_wr32(device, 0x002140, 0x7fffffff);
602 nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */
606 gf100_fifo_dtor(struct nvkm_fifo *base)
608 struct gf100_fifo *fifo = gf100_fifo(base);
609 nvkm_vm_put(&fifo->user.bar);
610 nvkm_memory_del(&fifo->user.mem);
611 nvkm_memory_del(&fifo->runlist.mem[0]);
612 nvkm_memory_del(&fifo->runlist.mem[1]);
616 static const struct nvkm_fifo_func
618 .dtor = gf100_fifo_dtor,
619 .oneinit = gf100_fifo_oneinit,
620 .init = gf100_fifo_init,
621 .fini = gf100_fifo_fini,
622 .intr = gf100_fifo_intr,
623 .uevent_init = gf100_fifo_uevent_init,
624 .uevent_fini = gf100_fifo_uevent_fini,
626 &gf100_fifo_gpfifo_oclass,
632 gf100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
634 struct gf100_fifo *fifo;
636 if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
638 INIT_LIST_HEAD(&fifo->chan);
639 INIT_WORK(&fifo->fault, gf100_fifo_recover_work);
640 *pfifo = &fifo->base;
642 return nvkm_fifo_ctor(&gf100_fifo, device, index, 128, &fifo->base);