2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
29 #include "gmc/gmc_8_1_d.h"
30 #include "gmc/gmc_8_1_sh_mask.h"
32 #include "bif/bif_5_0_d.h"
33 #include "bif/bif_5_0_sh_mask.h"
35 #include "oss/oss_3_0_d.h"
36 #include "oss/oss_3_0_sh_mask.h"
42 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
43 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
45 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
47 static const u32 golden_settings_tonga_a11[] =
49 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
50 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
51 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
52 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
53 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
54 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
55 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
58 static const u32 tonga_mgcg_cgcg_init[] =
60 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
63 static const u32 golden_settings_fiji_a10[] =
65 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
66 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
67 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
68 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
71 static const u32 fiji_mgcg_cgcg_init[] =
73 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
76 static const u32 cz_mgcg_cgcg_init[] =
78 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
81 static const u32 stoney_mgcg_cgcg_init[] =
83 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
87 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
89 switch (adev->asic_type) {
91 amdgpu_program_register_sequence(adev,
93 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
94 amdgpu_program_register_sequence(adev,
95 golden_settings_fiji_a10,
96 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
99 amdgpu_program_register_sequence(adev,
100 tonga_mgcg_cgcg_init,
101 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
102 amdgpu_program_register_sequence(adev,
103 golden_settings_tonga_a11,
104 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
107 amdgpu_program_register_sequence(adev,
109 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
112 amdgpu_program_register_sequence(adev,
113 stoney_mgcg_cgcg_init,
114 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
122 * gmc8_mc_wait_for_idle - wait for MC idle callback.
124 * @adev: amdgpu_device pointer
126 * Wait for the MC (memory controller) to be idle.
128 * Returns 0 if the MC is idle, -1 if not.
130 int gmc_v8_0_mc_wait_for_idle(struct amdgpu_device *adev)
135 for (i = 0; i < adev->usec_timeout; i++) {
137 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__VMC_BUSY_MASK |
138 SRBM_STATUS__MCB_BUSY_MASK |
139 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
140 SRBM_STATUS__MCC_BUSY_MASK |
141 SRBM_STATUS__MCD_BUSY_MASK |
142 SRBM_STATUS__VMC1_BUSY_MASK);
150 void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
151 struct amdgpu_mode_mc_save *save)
155 if (adev->mode_info.num_crtc)
156 amdgpu_display_stop_mc_access(adev, save);
158 amdgpu_asic_wait_for_mc_idle(adev);
160 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
161 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
162 /* Block CPU access */
163 WREG32(mmBIF_FB_EN, 0);
164 /* blackout the MC */
165 blackout = REG_SET_FIELD(blackout,
166 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
167 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
169 /* wait for the MC to settle */
173 void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
174 struct amdgpu_mode_mc_save *save)
178 /* unblackout the MC */
179 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
180 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
181 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
182 /* allow CPU access */
183 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
184 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
185 WREG32(mmBIF_FB_EN, tmp);
187 if (adev->mode_info.num_crtc)
188 amdgpu_display_resume_mc_access(adev, save);
192 * gmc_v8_0_init_microcode - load ucode images from disk
194 * @adev: amdgpu_device pointer
196 * Use the firmware interface to load the ucode images into
197 * the driver (not loaded into hw).
198 * Returns 0 on success, error on failure.
200 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
202 const char *chip_name;
208 switch (adev->asic_type) {
219 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
220 err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
223 err = amdgpu_ucode_validate(adev->mc.fw);
228 "mc: Failed to load firmware \"%s\"\n",
230 release_firmware(adev->mc.fw);
237 * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
239 * @adev: amdgpu_device pointer
241 * Load the GDDR MC ucode into the hw (CIK).
242 * Returns 0 on success, error on failure.
244 static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev)
246 const struct mc_firmware_header_v1_0 *hdr;
247 const __le32 *fw_data = NULL;
248 const __le32 *io_mc_regs = NULL;
249 u32 running, blackout = 0;
250 int i, ucode_size, regs_size;
255 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
256 amdgpu_ucode_print_mc_hdr(&hdr->header);
258 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
259 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
260 io_mc_regs = (const __le32 *)
261 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
262 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
263 fw_data = (const __le32 *)
264 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
266 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
270 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
271 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
274 /* reset the engine and set to writable */
275 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
276 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
278 /* load mc io regs */
279 for (i = 0; i < regs_size; i++) {
280 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
281 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
283 /* load the MC ucode */
284 for (i = 0; i < ucode_size; i++)
285 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
287 /* put the engine back into the active state */
288 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
289 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
290 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
292 /* wait for training to complete */
293 for (i = 0; i < adev->usec_timeout; i++) {
294 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
295 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
299 for (i = 0; i < adev->usec_timeout; i++) {
300 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
301 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
307 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
313 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
314 struct amdgpu_mc *mc)
316 if (mc->mc_vram_size > 0xFFC0000000ULL) {
317 /* leave room for at least 1024M GTT */
318 dev_warn(adev->dev, "limiting VRAM\n");
319 mc->real_vram_size = 0xFFC0000000ULL;
320 mc->mc_vram_size = 0xFFC0000000ULL;
322 amdgpu_vram_location(adev, &adev->mc, 0);
323 adev->mc.gtt_base_align = 0;
324 amdgpu_gtt_location(adev, mc);
328 * gmc_v8_0_mc_program - program the GPU memory controller
330 * @adev: amdgpu_device pointer
332 * Set the location of vram, gart, and AGP in the GPU's
333 * physical address space (CIK).
335 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
337 struct amdgpu_mode_mc_save save;
342 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
343 WREG32((0xb05 + j), 0x00000000);
344 WREG32((0xb06 + j), 0x00000000);
345 WREG32((0xb07 + j), 0x00000000);
346 WREG32((0xb08 + j), 0x00000000);
347 WREG32((0xb09 + j), 0x00000000);
349 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
351 if (adev->mode_info.num_crtc)
352 amdgpu_display_set_vga_render_state(adev, false);
354 gmc_v8_0_mc_stop(adev, &save);
355 if (amdgpu_asic_wait_for_mc_idle(adev)) {
356 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
358 /* Update configuration */
359 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
360 adev->mc.vram_start >> 12);
361 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
362 adev->mc.vram_end >> 12);
363 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
364 adev->vram_scratch.gpu_addr >> 12);
365 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
366 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
367 WREG32(mmMC_VM_FB_LOCATION, tmp);
368 /* XXX double check these! */
369 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
370 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
371 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
372 WREG32(mmMC_VM_AGP_BASE, 0);
373 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
374 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
375 if (amdgpu_asic_wait_for_mc_idle(adev)) {
376 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
378 gmc_v8_0_mc_resume(adev, &save);
380 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
382 tmp = RREG32(mmHDP_MISC_CNTL);
383 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
384 WREG32(mmHDP_MISC_CNTL, tmp);
386 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
387 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
391 * gmc_v8_0_mc_init - initialize the memory controller driver params
393 * @adev: amdgpu_device pointer
395 * Look up the amount of vram, vram width, and decide how to place
396 * vram and gart within the GPU's physical address space (CIK).
397 * Returns 0 for success.
399 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
402 int chansize, numchan;
404 /* Get VRAM informations */
405 tmp = RREG32(mmMC_ARB_RAMCFG);
406 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
411 tmp = RREG32(mmMC_SHARED_CHMAP);
412 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
442 adev->mc.vram_width = numchan * chansize;
443 /* Could aper size report 0 ? */
444 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
445 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
446 /* size in MB on si */
447 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
448 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
449 adev->mc.visible_vram_size = adev->mc.aper_size;
451 /* unless the user had overridden it, set the gart
452 * size equal to the 1024 or vram, whichever is larger.
454 if (amdgpu_gart_size == -1)
455 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
457 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
459 gmc_v8_0_vram_gtt_location(adev, &adev->mc);
466 * VMID 0 is the physical GPU addresses as used by the kernel.
467 * VMIDs 1-15 are used for userspace clients and are handled
468 * by the amdgpu vm/hsa code.
472 * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
474 * @adev: amdgpu_device pointer
475 * @vmid: vm instance to flush
477 * Flush the TLB for the requested page table (CIK).
479 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
482 /* flush hdp cache */
483 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
485 /* bits 0-15 are the VM contexts0-15 */
486 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
490 * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
492 * @adev: amdgpu_device pointer
493 * @cpu_pt_addr: cpu address of the page table
494 * @gpu_page_idx: entry in the page table to update
495 * @addr: dst addr to write into pte/pde
496 * @flags: access flags
498 * Update the page tables using the CPU.
500 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
502 uint32_t gpu_page_idx,
506 void __iomem *ptr = (void *)cpu_pt_addr;
512 * 39:12 4k physical page base address
523 * 63:59 block fragment size
525 * 39:1 physical base address of PTE
526 * bits 5:1 must be 0.
529 value = addr & 0x000000FFFFFFF000ULL;
531 writeq(value, ptr + (gpu_page_idx * 8));
537 * gmc_v8_0_set_fault_enable_default - update VM fault handling
539 * @adev: amdgpu_device pointer
540 * @value: true redirects VM faults to the default page
542 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
547 tmp = RREG32(mmVM_CONTEXT1_CNTL);
548 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
549 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
550 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
551 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
552 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
553 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
554 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
555 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
556 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
557 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
558 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
559 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
560 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
561 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
562 WREG32(mmVM_CONTEXT1_CNTL, tmp);
566 * gmc_v8_0_gart_enable - gart enable
568 * @adev: amdgpu_device pointer
570 * This sets up the TLBs, programs the page tables for VMID0,
571 * sets up the hw for VMIDs 1-15 which are allocated on
572 * demand, and sets up the global locations for the LDS, GDS,
573 * and GPUVM for FSA64 clients (CIK).
574 * Returns 0 for success, errors for failure.
576 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
581 if (adev->gart.robj == NULL) {
582 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
585 r = amdgpu_gart_table_vram_pin(adev);
588 /* Setup TLB control */
589 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
590 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
591 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
592 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
593 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
594 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
595 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
597 tmp = RREG32(mmVM_L2_CNTL);
598 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
599 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
600 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
601 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
602 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
603 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
604 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
605 WREG32(mmVM_L2_CNTL, tmp);
606 tmp = RREG32(mmVM_L2_CNTL2);
607 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
608 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
609 WREG32(mmVM_L2_CNTL2, tmp);
610 tmp = RREG32(mmVM_L2_CNTL3);
611 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
612 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
613 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
614 WREG32(mmVM_L2_CNTL3, tmp);
615 /* XXX: set to enable PTE/PDE in system memory */
616 tmp = RREG32(mmVM_L2_CNTL4);
617 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
618 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
619 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
620 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
621 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
622 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
623 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
624 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
625 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
626 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
627 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
629 WREG32(mmVM_L2_CNTL4, tmp);
631 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
632 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
633 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
634 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
635 (u32)(adev->dummy_page.addr >> 12));
636 WREG32(mmVM_CONTEXT0_CNTL2, 0);
637 tmp = RREG32(mmVM_CONTEXT0_CNTL);
638 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
639 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
640 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
641 WREG32(mmVM_CONTEXT0_CNTL, tmp);
643 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
644 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
645 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
647 /* empty context1-15 */
648 /* FIXME start with 4G, once using 2 level pt switch to full
651 /* set vm size, must be a multiple of 4 */
652 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
653 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
654 for (i = 1; i < 16; i++) {
656 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
657 adev->gart.table_addr >> 12);
659 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
660 adev->gart.table_addr >> 12);
663 /* enable context1-15 */
664 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
665 (u32)(adev->dummy_page.addr >> 12));
666 WREG32(mmVM_CONTEXT1_CNTL2, 4);
667 tmp = RREG32(mmVM_CONTEXT1_CNTL);
668 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
669 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
670 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
671 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
672 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
673 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
674 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
675 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
676 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
677 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
678 amdgpu_vm_block_size - 9);
679 WREG32(mmVM_CONTEXT1_CNTL, tmp);
680 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
681 gmc_v8_0_set_fault_enable_default(adev, false);
683 gmc_v8_0_set_fault_enable_default(adev, true);
685 gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
686 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
687 (unsigned)(adev->mc.gtt_size >> 20),
688 (unsigned long long)adev->gart.table_addr);
689 adev->gart.ready = true;
693 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
697 if (adev->gart.robj) {
698 WARN(1, "R600 PCIE GART already initialized\n");
701 /* Initialize common gart structure */
702 r = amdgpu_gart_init(adev);
705 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
706 return amdgpu_gart_table_vram_alloc(adev);
710 * gmc_v8_0_gart_disable - gart disable
712 * @adev: amdgpu_device pointer
714 * This disables all VM page table (CIK).
716 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
720 /* Disable all tables */
721 WREG32(mmVM_CONTEXT0_CNTL, 0);
722 WREG32(mmVM_CONTEXT1_CNTL, 0);
723 /* Setup TLB control */
724 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
725 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
726 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
727 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
728 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
730 tmp = RREG32(mmVM_L2_CNTL);
731 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
732 WREG32(mmVM_L2_CNTL, tmp);
733 WREG32(mmVM_L2_CNTL2, 0);
734 amdgpu_gart_table_vram_unpin(adev);
738 * gmc_v8_0_gart_fini - vm fini callback
740 * @adev: amdgpu_device pointer
742 * Tears down the driver GART/VM setup (CIK).
744 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
746 amdgpu_gart_table_vram_free(adev);
747 amdgpu_gart_fini(adev);
752 * VMID 0 is the physical GPU addresses as used by the kernel.
753 * VMIDs 1-15 are used for userspace clients and are handled
754 * by the amdgpu vm/hsa code.
757 * gmc_v8_0_vm_init - cik vm init callback
759 * @adev: amdgpu_device pointer
761 * Inits cik specific vm parameters (number of VMs, base of vram for
763 * Returns 0 for success.
765 static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
769 * VMID 0 is reserved for System
770 * amdgpu graphics/compute will use VMIDs 1-7
771 * amdkfd will use VMIDs 8-15
773 adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
775 /* base offset of vram pages */
776 if (adev->flags & AMD_IS_APU) {
777 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
779 adev->vm_manager.vram_base_offset = tmp;
781 adev->vm_manager.vram_base_offset = 0;
787 * gmc_v8_0_vm_fini - cik vm fini callback
789 * @adev: amdgpu_device pointer
791 * Tear down any asic specific VM setup (CIK).
793 static void gmc_v8_0_vm_fini(struct amdgpu_device *adev)
798 * gmc_v8_0_vm_decode_fault - print human readable fault info
800 * @adev: amdgpu_device pointer
801 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
802 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
804 * Print human readable fault information (CIK).
806 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
807 u32 status, u32 addr, u32 mc_client)
810 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
811 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
813 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
814 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
816 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
819 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
820 protections, vmid, addr,
821 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
823 "write" : "read", block, mc_client, mc_id);
826 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
828 switch (mc_seq_vram_type) {
829 case MC_SEQ_MISC0__MT__GDDR1:
830 return AMDGPU_VRAM_TYPE_GDDR1;
831 case MC_SEQ_MISC0__MT__DDR2:
832 return AMDGPU_VRAM_TYPE_DDR2;
833 case MC_SEQ_MISC0__MT__GDDR3:
834 return AMDGPU_VRAM_TYPE_GDDR3;
835 case MC_SEQ_MISC0__MT__GDDR4:
836 return AMDGPU_VRAM_TYPE_GDDR4;
837 case MC_SEQ_MISC0__MT__GDDR5:
838 return AMDGPU_VRAM_TYPE_GDDR5;
839 case MC_SEQ_MISC0__MT__HBM:
840 return AMDGPU_VRAM_TYPE_HBM;
841 case MC_SEQ_MISC0__MT__DDR3:
842 return AMDGPU_VRAM_TYPE_DDR3;
844 return AMDGPU_VRAM_TYPE_UNKNOWN;
848 static int gmc_v8_0_early_init(void *handle)
850 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
852 gmc_v8_0_set_gart_funcs(adev);
853 gmc_v8_0_set_irq_funcs(adev);
858 static int gmc_v8_0_late_init(void *handle)
860 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
862 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
865 #define mmMC_SEQ_MISC0_FIJI 0xA71
867 static int gmc_v8_0_sw_init(void *handle)
871 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
873 r = amdgpu_gem_init(adev);
877 if (adev->flags & AMD_IS_APU) {
878 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
882 if (adev->asic_type == CHIP_FIJI)
883 tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
885 tmp = RREG32(mmMC_SEQ_MISC0);
886 tmp &= MC_SEQ_MISC0__MT__MASK;
887 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
890 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
894 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
898 /* Adjust VM size here.
899 * Currently set to 4GB ((1 << 20) 4k pages).
900 * Max GPUVM size for cayman and SI is 40 bits.
902 adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
904 /* Set the internal MC address mask
905 * This is the max address of the GPU's
906 * internal address space.
908 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
910 /* set DMA mask + need_dma32 flags.
911 * PCIE - can handle 40-bits.
912 * IGP - can handle 40-bits
913 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
915 adev->need_dma32 = false;
916 dma_bits = adev->need_dma32 ? 32 : 40;
917 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
919 adev->need_dma32 = true;
921 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
923 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
925 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
926 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
929 r = gmc_v8_0_init_microcode(adev);
931 DRM_ERROR("Failed to load mc firmware!\n");
935 r = gmc_v8_0_mc_init(adev);
940 r = amdgpu_bo_init(adev);
944 r = gmc_v8_0_gart_init(adev);
948 if (!adev->vm_manager.enabled) {
949 r = gmc_v8_0_vm_init(adev);
951 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
954 adev->vm_manager.enabled = true;
960 static int gmc_v8_0_sw_fini(void *handle)
962 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
964 if (adev->vm_manager.enabled) {
965 amdgpu_vm_manager_fini(adev);
966 gmc_v8_0_vm_fini(adev);
967 adev->vm_manager.enabled = false;
969 gmc_v8_0_gart_fini(adev);
970 amdgpu_gem_fini(adev);
971 amdgpu_bo_fini(adev);
976 static int gmc_v8_0_hw_init(void *handle)
979 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
981 gmc_v8_0_init_golden_registers(adev);
983 gmc_v8_0_mc_program(adev);
985 if (adev->asic_type == CHIP_TONGA) {
986 r = gmc_v8_0_mc_load_microcode(adev);
988 DRM_ERROR("Failed to load MC firmware!\n");
993 r = gmc_v8_0_gart_enable(adev);
1000 static int gmc_v8_0_hw_fini(void *handle)
1002 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1004 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1005 gmc_v8_0_gart_disable(adev);
1010 static int gmc_v8_0_suspend(void *handle)
1012 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1014 if (adev->vm_manager.enabled) {
1015 amdgpu_vm_manager_fini(adev);
1016 gmc_v8_0_vm_fini(adev);
1017 adev->vm_manager.enabled = false;
1019 gmc_v8_0_hw_fini(adev);
1024 static int gmc_v8_0_resume(void *handle)
1027 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1029 r = gmc_v8_0_hw_init(adev);
1033 if (!adev->vm_manager.enabled) {
1034 r = gmc_v8_0_vm_init(adev);
1036 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1039 adev->vm_manager.enabled = true;
1045 static bool gmc_v8_0_is_idle(void *handle)
1047 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1048 u32 tmp = RREG32(mmSRBM_STATUS);
1050 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1051 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1057 static int gmc_v8_0_wait_for_idle(void *handle)
1061 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1063 for (i = 0; i < adev->usec_timeout; i++) {
1064 /* read MC_STATUS */
1065 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1066 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1067 SRBM_STATUS__MCC_BUSY_MASK |
1068 SRBM_STATUS__MCD_BUSY_MASK |
1069 SRBM_STATUS__VMC_BUSY_MASK |
1070 SRBM_STATUS__VMC1_BUSY_MASK);
1079 static void gmc_v8_0_print_status(void *handle)
1082 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1084 dev_info(adev->dev, "GMC 8.x registers\n");
1085 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
1086 RREG32(mmSRBM_STATUS));
1087 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1088 RREG32(mmSRBM_STATUS2));
1090 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1091 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
1092 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1093 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
1094 dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
1095 RREG32(mmMC_VM_MX_L1_TLB_CNTL));
1096 dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n",
1097 RREG32(mmVM_L2_CNTL));
1098 dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n",
1099 RREG32(mmVM_L2_CNTL2));
1100 dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n",
1101 RREG32(mmVM_L2_CNTL3));
1102 dev_info(adev->dev, " VM_L2_CNTL4=0x%08X\n",
1103 RREG32(mmVM_L2_CNTL4));
1104 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
1105 RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
1106 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
1107 RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
1108 dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1109 RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
1110 dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n",
1111 RREG32(mmVM_CONTEXT0_CNTL2));
1112 dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n",
1113 RREG32(mmVM_CONTEXT0_CNTL));
1114 dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=0x%08X\n",
1115 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR));
1116 dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=0x%08X\n",
1117 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR));
1118 dev_info(adev->dev, " mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=0x%08X\n",
1119 RREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET));
1120 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
1121 RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
1122 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
1123 RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
1124 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1125 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
1126 dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n",
1127 RREG32(mmVM_CONTEXT1_CNTL2));
1128 dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n",
1129 RREG32(mmVM_CONTEXT1_CNTL));
1130 for (i = 0; i < 16; i++) {
1132 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1133 i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
1135 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1136 i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
1138 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
1139 RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
1140 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
1141 RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
1142 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
1143 RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
1144 dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n",
1145 RREG32(mmMC_VM_FB_LOCATION));
1146 dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n",
1147 RREG32(mmMC_VM_AGP_BASE));
1148 dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n",
1149 RREG32(mmMC_VM_AGP_TOP));
1150 dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n",
1151 RREG32(mmMC_VM_AGP_BOT));
1153 dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
1154 RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
1155 dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n",
1156 RREG32(mmHDP_NONSURFACE_BASE));
1157 dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n",
1158 RREG32(mmHDP_NONSURFACE_INFO));
1159 dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n",
1160 RREG32(mmHDP_NONSURFACE_SIZE));
1161 dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n",
1162 RREG32(mmHDP_MISC_CNTL));
1163 dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n",
1164 RREG32(mmHDP_HOST_PATH_CNTL));
1166 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
1167 dev_info(adev->dev, " %d:\n", i);
1168 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1169 0xb05 + j, RREG32(0xb05 + j));
1170 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1171 0xb06 + j, RREG32(0xb06 + j));
1172 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1173 0xb07 + j, RREG32(0xb07 + j));
1174 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1175 0xb08 + j, RREG32(0xb08 + j));
1176 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1177 0xb09 + j, RREG32(0xb09 + j));
1180 dev_info(adev->dev, " BIF_FB_EN=0x%08X\n",
1181 RREG32(mmBIF_FB_EN));
1184 static int gmc_v8_0_soft_reset(void *handle)
1186 struct amdgpu_mode_mc_save save;
1187 u32 srbm_soft_reset = 0;
1188 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1189 u32 tmp = RREG32(mmSRBM_STATUS);
1191 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1192 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1193 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1195 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1196 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1197 if (!(adev->flags & AMD_IS_APU))
1198 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1199 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1202 if (srbm_soft_reset) {
1203 gmc_v8_0_print_status((void *)adev);
1205 gmc_v8_0_mc_stop(adev, &save);
1206 if (gmc_v8_0_wait_for_idle(adev)) {
1207 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1211 tmp = RREG32(mmSRBM_SOFT_RESET);
1212 tmp |= srbm_soft_reset;
1213 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1214 WREG32(mmSRBM_SOFT_RESET, tmp);
1215 tmp = RREG32(mmSRBM_SOFT_RESET);
1219 tmp &= ~srbm_soft_reset;
1220 WREG32(mmSRBM_SOFT_RESET, tmp);
1221 tmp = RREG32(mmSRBM_SOFT_RESET);
1223 /* Wait a little for things to settle down */
1226 gmc_v8_0_mc_resume(adev, &save);
1229 gmc_v8_0_print_status((void *)adev);
1235 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1236 struct amdgpu_irq_src *src,
1238 enum amdgpu_interrupt_state state)
1241 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1242 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1243 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1244 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1245 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1246 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1247 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1250 case AMDGPU_IRQ_STATE_DISABLE:
1251 /* system context */
1252 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1254 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1256 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1258 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1260 case AMDGPU_IRQ_STATE_ENABLE:
1261 /* system context */
1262 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1264 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1266 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1268 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1277 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1278 struct amdgpu_irq_src *source,
1279 struct amdgpu_iv_entry *entry)
1281 u32 addr, status, mc_client;
1283 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1284 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1285 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1286 /* reset addr and status */
1287 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1289 if (!addr && !status)
1292 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1293 gmc_v8_0_set_fault_enable_default(adev, false);
1295 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1296 entry->src_id, entry->src_data);
1297 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1299 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1301 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1306 static int gmc_v8_0_set_clockgating_state(void *handle,
1307 enum amd_clockgating_state state)
1312 static int gmc_v8_0_set_powergating_state(void *handle,
1313 enum amd_powergating_state state)
1318 const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1319 .early_init = gmc_v8_0_early_init,
1320 .late_init = gmc_v8_0_late_init,
1321 .sw_init = gmc_v8_0_sw_init,
1322 .sw_fini = gmc_v8_0_sw_fini,
1323 .hw_init = gmc_v8_0_hw_init,
1324 .hw_fini = gmc_v8_0_hw_fini,
1325 .suspend = gmc_v8_0_suspend,
1326 .resume = gmc_v8_0_resume,
1327 .is_idle = gmc_v8_0_is_idle,
1328 .wait_for_idle = gmc_v8_0_wait_for_idle,
1329 .soft_reset = gmc_v8_0_soft_reset,
1330 .print_status = gmc_v8_0_print_status,
1331 .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1332 .set_powergating_state = gmc_v8_0_set_powergating_state,
1335 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1336 .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1337 .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1340 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1341 .set = gmc_v8_0_vm_fault_interrupt_state,
1342 .process = gmc_v8_0_process_interrupt,
1345 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1347 if (adev->gart.gart_funcs == NULL)
1348 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1351 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1353 adev->mc.vm_fault.num_types = 1;
1354 adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;