2 * Core driver for the Synopsys DesignWare DMA Controller
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
6 * Copyright (C) 2013 Intel Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/bitops.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmapool.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/pm_runtime.h>
27 #include "../dmaengine.h"
31 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
33 * of which use ARM any more). See the "Databook" from Synopsys for
34 * information beyond what licensees probably provide.
36 * The driver has been tested with the Atmel AT32AP7000, which does not
37 * support descriptor writeback.
40 #define DWC_DEFAULT_CTLLO(_chan) ({ \
41 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
42 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
43 bool _is_slave = is_slave_direction(_dwc->direction); \
44 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \
46 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \
49 (DWC_CTLL_DST_MSIZE(_dmsize) \
50 | DWC_CTLL_SRC_MSIZE(_smsize) \
53 | DWC_CTLL_DMS(_dwc->dst_master) \
54 | DWC_CTLL_SMS(_dwc->src_master)); \
58 * Number of descriptors to allocate for each channel. This should be
59 * made configurable somehow; preferably, the clients (at least the
60 * ones using slave transfers) should be able to give us a hint.
62 #define NR_DESCS_PER_CHANNEL 64
64 /* The set of bus widths supported by the DMA controller */
65 #define DW_DMA_BUSWIDTHS \
66 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
67 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
68 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
69 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
71 /*----------------------------------------------------------------------*/
73 static struct device *chan2dev(struct dma_chan *chan)
75 return &chan->dev->device;
78 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
80 return to_dw_desc(dwc->active_list.next);
83 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
85 struct dw_desc *desc, *_desc;
86 struct dw_desc *ret = NULL;
90 spin_lock_irqsave(&dwc->lock, flags);
91 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
93 if (async_tx_test_ack(&desc->txd)) {
94 list_del(&desc->desc_node);
98 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
100 spin_unlock_irqrestore(&dwc->lock, flags);
102 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
108 * Move a descriptor, including any children, to the free list.
109 * `desc' must not be on any lists.
111 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
116 struct dw_desc *child;
118 spin_lock_irqsave(&dwc->lock, flags);
119 list_for_each_entry(child, &desc->tx_list, desc_node)
120 dev_vdbg(chan2dev(&dwc->chan),
121 "moving child desc %p to freelist\n",
123 list_splice_init(&desc->tx_list, &dwc->free_list);
124 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
125 list_add(&desc->desc_node, &dwc->free_list);
126 spin_unlock_irqrestore(&dwc->lock, flags);
130 static void dwc_initialize(struct dw_dma_chan *dwc)
132 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
133 struct dw_dma_slave *dws = dwc->chan.private;
134 u32 cfghi = DWC_CFGH_FIFO_MODE;
135 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
137 if (dwc->initialized == true)
142 * We need controller-specific data to set up slave
145 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
147 cfghi |= DWC_CFGH_DST_PER(dws->dst_id);
148 cfghi |= DWC_CFGH_SRC_PER(dws->src_id);
150 cfghi |= DWC_CFGH_DST_PER(dwc->dst_id);
151 cfghi |= DWC_CFGH_SRC_PER(dwc->src_id);
154 channel_writel(dwc, CFG_LO, cfglo);
155 channel_writel(dwc, CFG_HI, cfghi);
157 /* Enable interrupts */
158 channel_set_bit(dw, MASK.XFER, dwc->mask);
159 channel_set_bit(dw, MASK.ERROR, dwc->mask);
161 dwc->initialized = true;
164 /*----------------------------------------------------------------------*/
166 static inline unsigned int dwc_fast_ffs(unsigned long long v)
169 * We can be a lot more clever here, but this should take care
170 * of the most common optimization.
181 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
183 dev_err(chan2dev(&dwc->chan),
184 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
185 channel_readl(dwc, SAR),
186 channel_readl(dwc, DAR),
187 channel_readl(dwc, LLP),
188 channel_readl(dwc, CTL_HI),
189 channel_readl(dwc, CTL_LO));
192 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
194 channel_clear_bit(dw, CH_EN, dwc->mask);
195 while (dma_readl(dw, CH_EN) & dwc->mask)
199 /*----------------------------------------------------------------------*/
201 /* Perform single block transfer */
202 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
203 struct dw_desc *desc)
205 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
209 * Software emulation of LLP mode relies on interrupts to continue
210 * multi block transfer.
212 ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
214 channel_writel(dwc, SAR, desc->lli.sar);
215 channel_writel(dwc, DAR, desc->lli.dar);
216 channel_writel(dwc, CTL_LO, ctllo);
217 channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
218 channel_set_bit(dw, CH_EN, dwc->mask);
220 /* Move pointer to next descriptor */
221 dwc->tx_node_active = dwc->tx_node_active->next;
224 /* Called with dwc->lock held and bh disabled */
225 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
227 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
228 unsigned long was_soft_llp;
230 /* ASSERT: channel is idle */
231 if (dma_readl(dw, CH_EN) & dwc->mask) {
232 dev_err(chan2dev(&dwc->chan),
233 "%s: BUG: Attempted to start non-idle channel\n",
235 dwc_dump_chan_regs(dwc);
237 /* The tasklet will hopefully advance the queue... */
242 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
245 dev_err(chan2dev(&dwc->chan),
246 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
252 dwc->residue = first->total_len;
253 dwc->tx_node_active = &first->tx_list;
255 /* Submit first block */
256 dwc_do_single_block(dwc, first);
263 channel_writel(dwc, LLP, first->txd.phys);
264 channel_writel(dwc, CTL_LO,
265 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
266 channel_writel(dwc, CTL_HI, 0);
267 channel_set_bit(dw, CH_EN, dwc->mask);
270 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
272 struct dw_desc *desc;
274 if (list_empty(&dwc->queue))
277 list_move(dwc->queue.next, &dwc->active_list);
278 desc = dwc_first_active(dwc);
279 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
280 dwc_dostart(dwc, desc);
283 /*----------------------------------------------------------------------*/
286 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
287 bool callback_required)
289 dma_async_tx_callback callback = NULL;
291 struct dma_async_tx_descriptor *txd = &desc->txd;
292 struct dw_desc *child;
295 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
297 spin_lock_irqsave(&dwc->lock, flags);
298 dma_cookie_complete(txd);
299 if (callback_required) {
300 callback = txd->callback;
301 param = txd->callback_param;
305 list_for_each_entry(child, &desc->tx_list, desc_node)
306 async_tx_ack(&child->txd);
307 async_tx_ack(&desc->txd);
309 list_splice_init(&desc->tx_list, &dwc->free_list);
310 list_move(&desc->desc_node, &dwc->free_list);
312 dma_descriptor_unmap(txd);
313 spin_unlock_irqrestore(&dwc->lock, flags);
319 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
321 struct dw_desc *desc, *_desc;
325 spin_lock_irqsave(&dwc->lock, flags);
326 if (dma_readl(dw, CH_EN) & dwc->mask) {
327 dev_err(chan2dev(&dwc->chan),
328 "BUG: XFER bit set, but channel not idle!\n");
330 /* Try to continue after resetting the channel... */
331 dwc_chan_disable(dw, dwc);
335 * Submit queued descriptors ASAP, i.e. before we go through
336 * the completed ones.
338 list_splice_init(&dwc->active_list, &list);
339 dwc_dostart_first_queued(dwc);
341 spin_unlock_irqrestore(&dwc->lock, flags);
343 list_for_each_entry_safe(desc, _desc, &list, desc_node)
344 dwc_descriptor_complete(dwc, desc, true);
347 /* Returns how many bytes were already received from source */
348 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
350 u32 ctlhi = channel_readl(dwc, CTL_HI);
351 u32 ctllo = channel_readl(dwc, CTL_LO);
353 return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
356 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
359 struct dw_desc *desc, *_desc;
360 struct dw_desc *child;
364 spin_lock_irqsave(&dwc->lock, flags);
365 llp = channel_readl(dwc, LLP);
366 status_xfer = dma_readl(dw, RAW.XFER);
368 if (status_xfer & dwc->mask) {
369 /* Everything we've submitted is done */
370 dma_writel(dw, CLEAR.XFER, dwc->mask);
372 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
373 struct list_head *head, *active = dwc->tx_node_active;
376 * We are inside first active descriptor.
377 * Otherwise something is really wrong.
379 desc = dwc_first_active(dwc);
381 head = &desc->tx_list;
382 if (active != head) {
383 /* Update desc to reflect last sent one */
384 if (active != head->next)
385 desc = to_dw_desc(active->prev);
387 dwc->residue -= desc->len;
389 child = to_dw_desc(active);
391 /* Submit next block */
392 dwc_do_single_block(dwc, child);
394 spin_unlock_irqrestore(&dwc->lock, flags);
398 /* We are done here */
399 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
404 spin_unlock_irqrestore(&dwc->lock, flags);
406 dwc_complete_all(dw, dwc);
410 if (list_empty(&dwc->active_list)) {
412 spin_unlock_irqrestore(&dwc->lock, flags);
416 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
417 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
418 spin_unlock_irqrestore(&dwc->lock, flags);
422 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
424 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
425 /* Initial residue value */
426 dwc->residue = desc->total_len;
428 /* Check first descriptors addr */
429 if (desc->txd.phys == llp) {
430 spin_unlock_irqrestore(&dwc->lock, flags);
434 /* Check first descriptors llp */
435 if (desc->lli.llp == llp) {
436 /* This one is currently in progress */
437 dwc->residue -= dwc_get_sent(dwc);
438 spin_unlock_irqrestore(&dwc->lock, flags);
442 dwc->residue -= desc->len;
443 list_for_each_entry(child, &desc->tx_list, desc_node) {
444 if (child->lli.llp == llp) {
445 /* Currently in progress */
446 dwc->residue -= dwc_get_sent(dwc);
447 spin_unlock_irqrestore(&dwc->lock, flags);
450 dwc->residue -= child->len;
454 * No descriptors so far seem to be in progress, i.e.
455 * this one must be done.
457 spin_unlock_irqrestore(&dwc->lock, flags);
458 dwc_descriptor_complete(dwc, desc, true);
459 spin_lock_irqsave(&dwc->lock, flags);
462 dev_err(chan2dev(&dwc->chan),
463 "BUG: All descriptors done, but channel not idle!\n");
465 /* Try to continue after resetting the channel... */
466 dwc_chan_disable(dw, dwc);
468 dwc_dostart_first_queued(dwc);
469 spin_unlock_irqrestore(&dwc->lock, flags);
472 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
474 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
475 lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
478 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
480 struct dw_desc *bad_desc;
481 struct dw_desc *child;
484 dwc_scan_descriptors(dw, dwc);
486 spin_lock_irqsave(&dwc->lock, flags);
489 * The descriptor currently at the head of the active list is
490 * borked. Since we don't have any way to report errors, we'll
491 * just have to scream loudly and try to carry on.
493 bad_desc = dwc_first_active(dwc);
494 list_del_init(&bad_desc->desc_node);
495 list_move(dwc->queue.next, dwc->active_list.prev);
497 /* Clear the error flag and try to restart the controller */
498 dma_writel(dw, CLEAR.ERROR, dwc->mask);
499 if (!list_empty(&dwc->active_list))
500 dwc_dostart(dwc, dwc_first_active(dwc));
503 * WARN may seem harsh, but since this only happens
504 * when someone submits a bad physical address in a
505 * descriptor, we should consider ourselves lucky that the
506 * controller flagged an error instead of scribbling over
507 * random memory locations.
509 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
510 " cookie: %d\n", bad_desc->txd.cookie);
511 dwc_dump_lli(dwc, &bad_desc->lli);
512 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
513 dwc_dump_lli(dwc, &child->lli);
515 spin_unlock_irqrestore(&dwc->lock, flags);
517 /* Pretend the descriptor completed successfully */
518 dwc_descriptor_complete(dwc, bad_desc, true);
521 /* --------------------- Cyclic DMA API extensions -------------------- */
523 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
525 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
526 return channel_readl(dwc, SAR);
528 EXPORT_SYMBOL(dw_dma_get_src_addr);
530 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
532 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
533 return channel_readl(dwc, DAR);
535 EXPORT_SYMBOL(dw_dma_get_dst_addr);
537 /* Called with dwc->lock held and all DMAC interrupts disabled */
538 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
539 u32 status_block, u32 status_err, u32 status_xfer)
543 if (status_block & dwc->mask) {
544 void (*callback)(void *param);
545 void *callback_param;
547 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
548 channel_readl(dwc, LLP));
549 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
551 callback = dwc->cdesc->period_callback;
552 callback_param = dwc->cdesc->period_callback_param;
555 callback(callback_param);
559 * Error and transfer complete are highly unlikely, and will most
560 * likely be due to a configuration error by the user.
562 if (unlikely(status_err & dwc->mask) ||
563 unlikely(status_xfer & dwc->mask)) {
566 dev_err(chan2dev(&dwc->chan),
567 "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
568 status_xfer ? "xfer" : "error");
570 spin_lock_irqsave(&dwc->lock, flags);
572 dwc_dump_chan_regs(dwc);
574 dwc_chan_disable(dw, dwc);
576 /* Make sure DMA does not restart by loading a new list */
577 channel_writel(dwc, LLP, 0);
578 channel_writel(dwc, CTL_LO, 0);
579 channel_writel(dwc, CTL_HI, 0);
581 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
582 dma_writel(dw, CLEAR.ERROR, dwc->mask);
583 dma_writel(dw, CLEAR.XFER, dwc->mask);
585 for (i = 0; i < dwc->cdesc->periods; i++)
586 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
588 spin_unlock_irqrestore(&dwc->lock, flags);
591 /* Re-enable interrupts */
592 channel_set_bit(dw, MASK.BLOCK, dwc->mask);
595 /* ------------------------------------------------------------------------- */
597 static void dw_dma_tasklet(unsigned long data)
599 struct dw_dma *dw = (struct dw_dma *)data;
600 struct dw_dma_chan *dwc;
606 status_block = dma_readl(dw, RAW.BLOCK);
607 status_xfer = dma_readl(dw, RAW.XFER);
608 status_err = dma_readl(dw, RAW.ERROR);
610 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
612 for (i = 0; i < dw->dma.chancnt; i++) {
614 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
615 dwc_handle_cyclic(dw, dwc, status_block, status_err,
617 else if (status_err & (1 << i))
618 dwc_handle_error(dw, dwc);
619 else if (status_xfer & (1 << i))
620 dwc_scan_descriptors(dw, dwc);
623 /* Re-enable interrupts */
624 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
625 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
628 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
630 struct dw_dma *dw = dev_id;
631 u32 status = dma_readl(dw, STATUS_INT);
633 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
635 /* Check if we have any interrupt from the DMAC */
636 if (!status || !dw->in_use)
640 * Just disable the interrupts. We'll turn them back on in the
643 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
644 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
645 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
647 status = dma_readl(dw, STATUS_INT);
650 "BUG: Unexpected interrupts pending: 0x%x\n",
654 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
655 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
656 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
657 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
658 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
661 tasklet_schedule(&dw->tasklet);
666 /*----------------------------------------------------------------------*/
668 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
670 struct dw_desc *desc = txd_to_dw_desc(tx);
671 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
675 spin_lock_irqsave(&dwc->lock, flags);
676 cookie = dma_cookie_assign(tx);
679 * REVISIT: We should attempt to chain as many descriptors as
680 * possible, perhaps even appending to those already submitted
681 * for DMA. But this is hard to do in a race-free manner.
684 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie);
685 list_add_tail(&desc->desc_node, &dwc->queue);
687 spin_unlock_irqrestore(&dwc->lock, flags);
692 static struct dma_async_tx_descriptor *
693 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
694 size_t len, unsigned long flags)
696 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
697 struct dw_dma *dw = to_dw_dma(chan->device);
698 struct dw_desc *desc;
699 struct dw_desc *first;
700 struct dw_desc *prev;
703 unsigned int src_width;
704 unsigned int dst_width;
705 unsigned int data_width;
708 dev_vdbg(chan2dev(chan),
709 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
710 &dest, &src, len, flags);
712 if (unlikely(!len)) {
713 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
717 dwc->direction = DMA_MEM_TO_MEM;
719 data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
720 dw->data_width[dwc->dst_master]);
722 src_width = dst_width = min_t(unsigned int, data_width,
723 dwc_fast_ffs(src | dest | len));
725 ctllo = DWC_DEFAULT_CTLLO(chan)
726 | DWC_CTLL_DST_WIDTH(dst_width)
727 | DWC_CTLL_SRC_WIDTH(src_width)
733 for (offset = 0; offset < len; offset += xfer_count << src_width) {
734 xfer_count = min_t(size_t, (len - offset) >> src_width,
737 desc = dwc_desc_get(dwc);
741 desc->lli.sar = src + offset;
742 desc->lli.dar = dest + offset;
743 desc->lli.ctllo = ctllo;
744 desc->lli.ctlhi = xfer_count;
745 desc->len = xfer_count << src_width;
750 prev->lli.llp = desc->txd.phys;
751 list_add_tail(&desc->desc_node,
757 if (flags & DMA_PREP_INTERRUPT)
758 /* Trigger interrupt after last block */
759 prev->lli.ctllo |= DWC_CTLL_INT_EN;
762 first->txd.flags = flags;
763 first->total_len = len;
768 dwc_desc_put(dwc, first);
772 static struct dma_async_tx_descriptor *
773 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
774 unsigned int sg_len, enum dma_transfer_direction direction,
775 unsigned long flags, void *context)
777 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
778 struct dw_dma *dw = to_dw_dma(chan->device);
779 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
780 struct dw_desc *prev;
781 struct dw_desc *first;
784 unsigned int reg_width;
785 unsigned int mem_width;
786 unsigned int data_width;
788 struct scatterlist *sg;
789 size_t total_len = 0;
791 dev_vdbg(chan2dev(chan), "%s\n", __func__);
793 if (unlikely(!is_slave_direction(direction) || !sg_len))
796 dwc->direction = direction;
802 reg_width = __ffs(sconfig->dst_addr_width);
803 reg = sconfig->dst_addr;
804 ctllo = (DWC_DEFAULT_CTLLO(chan)
805 | DWC_CTLL_DST_WIDTH(reg_width)
809 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
810 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
812 data_width = dw->data_width[dwc->src_master];
814 for_each_sg(sgl, sg, sg_len, i) {
815 struct dw_desc *desc;
818 mem = sg_dma_address(sg);
819 len = sg_dma_len(sg);
821 mem_width = min_t(unsigned int,
822 data_width, dwc_fast_ffs(mem | len));
824 slave_sg_todev_fill_desc:
825 desc = dwc_desc_get(dwc);
831 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
832 if ((len >> mem_width) > dwc->block_size) {
833 dlen = dwc->block_size << mem_width;
841 desc->lli.ctlhi = dlen >> mem_width;
847 prev->lli.llp = desc->txd.phys;
848 list_add_tail(&desc->desc_node,
855 goto slave_sg_todev_fill_desc;
859 reg_width = __ffs(sconfig->src_addr_width);
860 reg = sconfig->src_addr;
861 ctllo = (DWC_DEFAULT_CTLLO(chan)
862 | DWC_CTLL_SRC_WIDTH(reg_width)
866 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
867 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
869 data_width = dw->data_width[dwc->dst_master];
871 for_each_sg(sgl, sg, sg_len, i) {
872 struct dw_desc *desc;
875 mem = sg_dma_address(sg);
876 len = sg_dma_len(sg);
878 mem_width = min_t(unsigned int,
879 data_width, dwc_fast_ffs(mem | len));
881 slave_sg_fromdev_fill_desc:
882 desc = dwc_desc_get(dwc);
888 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
889 if ((len >> reg_width) > dwc->block_size) {
890 dlen = dwc->block_size << reg_width;
897 desc->lli.ctlhi = dlen >> reg_width;
903 prev->lli.llp = desc->txd.phys;
904 list_add_tail(&desc->desc_node,
911 goto slave_sg_fromdev_fill_desc;
918 if (flags & DMA_PREP_INTERRUPT)
919 /* Trigger interrupt after last block */
920 prev->lli.ctllo |= DWC_CTLL_INT_EN;
923 first->total_len = total_len;
928 dev_err(chan2dev(chan),
929 "not enough descriptors available. Direction %d\n", direction);
930 dwc_desc_put(dwc, first);
934 bool dw_dma_filter(struct dma_chan *chan, void *param)
936 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
937 struct dw_dma_slave *dws = param;
939 if (!dws || dws->dma_dev != chan->device->dev)
942 /* We have to copy data since dws can be temporary storage */
944 dwc->src_id = dws->src_id;
945 dwc->dst_id = dws->dst_id;
947 dwc->src_master = dws->src_master;
948 dwc->dst_master = dws->dst_master;
952 EXPORT_SYMBOL_GPL(dw_dma_filter);
955 * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
956 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
958 * NOTE: burst size 2 is not supported by controller.
960 * This can be done by finding least significant bit set: n & (n - 1)
962 static inline void convert_burst(u32 *maxburst)
965 *maxburst = fls(*maxburst) - 2;
970 static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
972 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
974 /* Check if chan will be configured for slave transfers */
975 if (!is_slave_direction(sconfig->direction))
978 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
979 dwc->direction = sconfig->direction;
981 convert_burst(&dwc->dma_sconfig.src_maxburst);
982 convert_burst(&dwc->dma_sconfig.dst_maxburst);
987 static int dwc_pause(struct dma_chan *chan)
989 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
991 unsigned int count = 20; /* timeout iterations */
994 spin_lock_irqsave(&dwc->lock, flags);
996 cfglo = channel_readl(dwc, CFG_LO);
997 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
998 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
1003 spin_unlock_irqrestore(&dwc->lock, flags);
1008 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
1010 u32 cfglo = channel_readl(dwc, CFG_LO);
1012 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1014 dwc->paused = false;
1017 static int dwc_resume(struct dma_chan *chan)
1019 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1020 unsigned long flags;
1025 spin_lock_irqsave(&dwc->lock, flags);
1027 dwc_chan_resume(dwc);
1029 spin_unlock_irqrestore(&dwc->lock, flags);
1034 static int dwc_terminate_all(struct dma_chan *chan)
1036 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1037 struct dw_dma *dw = to_dw_dma(chan->device);
1038 struct dw_desc *desc, *_desc;
1039 unsigned long flags;
1042 spin_lock_irqsave(&dwc->lock, flags);
1044 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1046 dwc_chan_disable(dw, dwc);
1048 dwc_chan_resume(dwc);
1050 /* active_list entries will end up before queued entries */
1051 list_splice_init(&dwc->queue, &list);
1052 list_splice_init(&dwc->active_list, &list);
1054 spin_unlock_irqrestore(&dwc->lock, flags);
1056 /* Flush all pending and queued descriptors */
1057 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1058 dwc_descriptor_complete(dwc, desc, false);
1063 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1065 unsigned long flags;
1068 spin_lock_irqsave(&dwc->lock, flags);
1070 residue = dwc->residue;
1071 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1072 residue -= dwc_get_sent(dwc);
1074 spin_unlock_irqrestore(&dwc->lock, flags);
1078 static enum dma_status
1079 dwc_tx_status(struct dma_chan *chan,
1080 dma_cookie_t cookie,
1081 struct dma_tx_state *txstate)
1083 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1084 enum dma_status ret;
1086 ret = dma_cookie_status(chan, cookie, txstate);
1087 if (ret == DMA_COMPLETE)
1090 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1092 ret = dma_cookie_status(chan, cookie, txstate);
1093 if (ret != DMA_COMPLETE)
1094 dma_set_residue(txstate, dwc_get_residue(dwc));
1096 if (dwc->paused && ret == DMA_IN_PROGRESS)
1102 static void dwc_issue_pending(struct dma_chan *chan)
1104 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1105 unsigned long flags;
1107 spin_lock_irqsave(&dwc->lock, flags);
1108 if (list_empty(&dwc->active_list))
1109 dwc_dostart_first_queued(dwc);
1110 spin_unlock_irqrestore(&dwc->lock, flags);
1113 /*----------------------------------------------------------------------*/
1115 static void dw_dma_off(struct dw_dma *dw)
1119 dma_writel(dw, CFG, 0);
1121 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1122 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1123 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1124 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1125 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1127 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1130 for (i = 0; i < dw->dma.chancnt; i++)
1131 dw->chan[i].initialized = false;
1134 static void dw_dma_on(struct dw_dma *dw)
1136 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1139 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1141 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1142 struct dw_dma *dw = to_dw_dma(chan->device);
1143 struct dw_desc *desc;
1145 unsigned long flags;
1147 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1149 /* ASSERT: channel is idle */
1150 if (dma_readl(dw, CH_EN) & dwc->mask) {
1151 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1155 dma_cookie_init(chan);
1158 * NOTE: some controllers may have additional features that we
1159 * need to initialize here, like "scatter-gather" (which
1160 * doesn't mean what you think it means), and status writeback.
1163 /* Enable controller here if needed */
1166 dw->in_use |= dwc->mask;
1168 spin_lock_irqsave(&dwc->lock, flags);
1169 i = dwc->descs_allocated;
1170 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1173 spin_unlock_irqrestore(&dwc->lock, flags);
1175 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1177 goto err_desc_alloc;
1179 memset(desc, 0, sizeof(struct dw_desc));
1181 INIT_LIST_HEAD(&desc->tx_list);
1182 dma_async_tx_descriptor_init(&desc->txd, chan);
1183 desc->txd.tx_submit = dwc_tx_submit;
1184 desc->txd.flags = DMA_CTRL_ACK;
1185 desc->txd.phys = phys;
1187 dwc_desc_put(dwc, desc);
1189 spin_lock_irqsave(&dwc->lock, flags);
1190 i = ++dwc->descs_allocated;
1193 spin_unlock_irqrestore(&dwc->lock, flags);
1195 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1200 dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1205 static void dwc_free_chan_resources(struct dma_chan *chan)
1207 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1208 struct dw_dma *dw = to_dw_dma(chan->device);
1209 struct dw_desc *desc, *_desc;
1210 unsigned long flags;
1213 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1214 dwc->descs_allocated);
1216 /* ASSERT: channel is idle */
1217 BUG_ON(!list_empty(&dwc->active_list));
1218 BUG_ON(!list_empty(&dwc->queue));
1219 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1221 spin_lock_irqsave(&dwc->lock, flags);
1222 list_splice_init(&dwc->free_list, &list);
1223 dwc->descs_allocated = 0;
1224 dwc->initialized = false;
1226 /* Disable interrupts */
1227 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1228 channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
1229 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1231 spin_unlock_irqrestore(&dwc->lock, flags);
1233 /* Disable controller in case it was a last user */
1234 dw->in_use &= ~dwc->mask;
1238 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1239 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1240 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1243 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1246 /* --------------------- Cyclic DMA API extensions -------------------- */
1249 * dw_dma_cyclic_start - start the cyclic DMA transfer
1250 * @chan: the DMA channel to start
1252 * Must be called with soft interrupts disabled. Returns zero on success or
1253 * -errno on failure.
1255 int dw_dma_cyclic_start(struct dma_chan *chan)
1257 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1258 struct dw_dma *dw = to_dw_dma(chan->device);
1259 unsigned long flags;
1261 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1262 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1266 spin_lock_irqsave(&dwc->lock, flags);
1268 /* Enable interrupts to perform cyclic transfer */
1269 channel_set_bit(dw, MASK.BLOCK, dwc->mask);
1271 dwc_dostart(dwc, dwc->cdesc->desc[0]);
1273 spin_unlock_irqrestore(&dwc->lock, flags);
1277 EXPORT_SYMBOL(dw_dma_cyclic_start);
1280 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1281 * @chan: the DMA channel to stop
1283 * Must be called with soft interrupts disabled.
1285 void dw_dma_cyclic_stop(struct dma_chan *chan)
1287 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1288 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1289 unsigned long flags;
1291 spin_lock_irqsave(&dwc->lock, flags);
1293 dwc_chan_disable(dw, dwc);
1295 spin_unlock_irqrestore(&dwc->lock, flags);
1297 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1300 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1301 * @chan: the DMA channel to prepare
1302 * @buf_addr: physical DMA address where the buffer starts
1303 * @buf_len: total number of bytes for the entire buffer
1304 * @period_len: number of bytes for each period
1305 * @direction: transfer direction, to or from device
1307 * Must be called before trying to start the transfer. Returns a valid struct
1308 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1310 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1311 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1312 enum dma_transfer_direction direction)
1314 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1315 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
1316 struct dw_cyclic_desc *cdesc;
1317 struct dw_cyclic_desc *retval = NULL;
1318 struct dw_desc *desc;
1319 struct dw_desc *last = NULL;
1320 unsigned long was_cyclic;
1321 unsigned int reg_width;
1322 unsigned int periods;
1324 unsigned long flags;
1326 spin_lock_irqsave(&dwc->lock, flags);
1328 spin_unlock_irqrestore(&dwc->lock, flags);
1329 dev_dbg(chan2dev(&dwc->chan),
1330 "channel doesn't support LLP transfers\n");
1331 return ERR_PTR(-EINVAL);
1334 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1335 spin_unlock_irqrestore(&dwc->lock, flags);
1336 dev_dbg(chan2dev(&dwc->chan),
1337 "queue and/or active list are not empty\n");
1338 return ERR_PTR(-EBUSY);
1341 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1342 spin_unlock_irqrestore(&dwc->lock, flags);
1344 dev_dbg(chan2dev(&dwc->chan),
1345 "channel already prepared for cyclic DMA\n");
1346 return ERR_PTR(-EBUSY);
1349 retval = ERR_PTR(-EINVAL);
1351 if (unlikely(!is_slave_direction(direction)))
1354 dwc->direction = direction;
1356 if (direction == DMA_MEM_TO_DEV)
1357 reg_width = __ffs(sconfig->dst_addr_width);
1359 reg_width = __ffs(sconfig->src_addr_width);
1361 periods = buf_len / period_len;
1363 /* Check for too big/unaligned periods and unaligned DMA buffer. */
1364 if (period_len > (dwc->block_size << reg_width))
1366 if (unlikely(period_len & ((1 << reg_width) - 1)))
1368 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1371 retval = ERR_PTR(-ENOMEM);
1373 if (periods > NR_DESCS_PER_CHANNEL)
1376 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1380 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1384 for (i = 0; i < periods; i++) {
1385 desc = dwc_desc_get(dwc);
1387 goto out_err_desc_get;
1389 switch (direction) {
1390 case DMA_MEM_TO_DEV:
1391 desc->lli.dar = sconfig->dst_addr;
1392 desc->lli.sar = buf_addr + (period_len * i);
1393 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1394 | DWC_CTLL_DST_WIDTH(reg_width)
1395 | DWC_CTLL_SRC_WIDTH(reg_width)
1400 desc->lli.ctllo |= sconfig->device_fc ?
1401 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1402 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1405 case DMA_DEV_TO_MEM:
1406 desc->lli.dar = buf_addr + (period_len * i);
1407 desc->lli.sar = sconfig->src_addr;
1408 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1409 | DWC_CTLL_SRC_WIDTH(reg_width)
1410 | DWC_CTLL_DST_WIDTH(reg_width)
1415 desc->lli.ctllo |= sconfig->device_fc ?
1416 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1417 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1424 desc->lli.ctlhi = (period_len >> reg_width);
1425 cdesc->desc[i] = desc;
1428 last->lli.llp = desc->txd.phys;
1433 /* Let's make a cyclic list */
1434 last->lli.llp = cdesc->desc[0]->txd.phys;
1436 dev_dbg(chan2dev(&dwc->chan),
1437 "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1438 &buf_addr, buf_len, period_len, periods);
1440 cdesc->periods = periods;
1447 dwc_desc_put(dwc, cdesc->desc[i]);
1451 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1452 return (struct dw_cyclic_desc *)retval;
1454 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1457 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1458 * @chan: the DMA channel to free
1460 void dw_dma_cyclic_free(struct dma_chan *chan)
1462 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1463 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1464 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1466 unsigned long flags;
1468 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1473 spin_lock_irqsave(&dwc->lock, flags);
1475 dwc_chan_disable(dw, dwc);
1477 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
1478 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1479 dma_writel(dw, CLEAR.XFER, dwc->mask);
1481 spin_unlock_irqrestore(&dwc->lock, flags);
1483 for (i = 0; i < cdesc->periods; i++)
1484 dwc_desc_put(dwc, cdesc->desc[i]);
1489 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1491 EXPORT_SYMBOL(dw_dma_cyclic_free);
1493 /*----------------------------------------------------------------------*/
1495 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1498 bool autocfg = false;
1499 unsigned int dw_params;
1500 unsigned int max_blk_size = 0;
1504 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1508 dw->regs = chip->regs;
1511 pm_runtime_get_sync(chip->dev);
1514 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1515 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1517 autocfg = dw_params >> DW_PARAMS_EN & 1;
1523 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1529 /* Get hardware configuration parameters */
1530 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
1531 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1532 for (i = 0; i < pdata->nr_masters; i++) {
1533 pdata->data_width[i] =
1534 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1536 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1538 /* Fill platform data with the default values */
1539 pdata->is_private = true;
1540 pdata->is_memcpy = true;
1541 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1542 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1543 } else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1548 dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
1555 /* Get hardware configuration parameters */
1556 dw->nr_masters = pdata->nr_masters;
1557 for (i = 0; i < dw->nr_masters; i++)
1558 dw->data_width[i] = pdata->data_width[i];
1560 /* Calculate all channel mask before DMA setup */
1561 dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1563 /* Force dma off, just in case */
1566 /* Create a pool of consistent memory blocks for hardware descriptors */
1567 dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1568 sizeof(struct dw_desc), 4, 0);
1569 if (!dw->desc_pool) {
1570 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1575 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1577 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1582 INIT_LIST_HEAD(&dw->dma.channels);
1583 for (i = 0; i < pdata->nr_channels; i++) {
1584 struct dw_dma_chan *dwc = &dw->chan[i];
1586 dwc->chan.device = &dw->dma;
1587 dma_cookie_init(&dwc->chan);
1588 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1589 list_add_tail(&dwc->chan.device_node,
1592 list_add(&dwc->chan.device_node, &dw->dma.channels);
1594 /* 7 is highest priority & 0 is lowest. */
1595 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1596 dwc->priority = pdata->nr_channels - i - 1;
1600 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1601 spin_lock_init(&dwc->lock);
1604 INIT_LIST_HEAD(&dwc->active_list);
1605 INIT_LIST_HEAD(&dwc->queue);
1606 INIT_LIST_HEAD(&dwc->free_list);
1608 channel_clear_bit(dw, CH_EN, dwc->mask);
1610 dwc->direction = DMA_TRANS_NONE;
1612 /* Hardware configuration */
1614 unsigned int dwc_params;
1615 unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1;
1616 void __iomem *addr = chip->regs + r * sizeof(u32);
1618 dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1620 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1624 * Decode maximum block size for given channel. The
1625 * stored 4 bit value represents blocks from 0x00 for 3
1626 * up to 0x0a for 4095.
1629 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1631 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1633 dwc->block_size = pdata->block_size;
1635 /* Check if channel supports multi block transfer */
1636 channel_writel(dwc, LLP, 0xfffffffc);
1638 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1639 channel_writel(dwc, LLP, 0);
1643 /* Clear all interrupts on all channels. */
1644 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1645 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1646 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1647 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1648 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1650 /* Set capabilities */
1651 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1652 if (pdata->is_private)
1653 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1654 if (pdata->is_memcpy)
1655 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1657 dw->dma.dev = chip->dev;
1658 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1659 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1661 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1662 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1664 dw->dma.device_config = dwc_config;
1665 dw->dma.device_pause = dwc_pause;
1666 dw->dma.device_resume = dwc_resume;
1667 dw->dma.device_terminate_all = dwc_terminate_all;
1669 dw->dma.device_tx_status = dwc_tx_status;
1670 dw->dma.device_issue_pending = dwc_issue_pending;
1672 /* DMA capabilities */
1673 dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
1674 dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
1675 dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1676 BIT(DMA_MEM_TO_MEM);
1677 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1679 err = dma_async_device_register(&dw->dma);
1681 goto err_dma_register;
1683 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1684 pdata->nr_channels);
1686 pm_runtime_put_sync_suspend(chip->dev);
1691 free_irq(chip->irq, dw);
1693 pm_runtime_put_sync_suspend(chip->dev);
1696 EXPORT_SYMBOL_GPL(dw_dma_probe);
1698 int dw_dma_remove(struct dw_dma_chip *chip)
1700 struct dw_dma *dw = chip->dw;
1701 struct dw_dma_chan *dwc, *_dwc;
1703 pm_runtime_get_sync(chip->dev);
1706 dma_async_device_unregister(&dw->dma);
1708 free_irq(chip->irq, dw);
1709 tasklet_kill(&dw->tasklet);
1711 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1713 list_del(&dwc->chan.device_node);
1714 channel_clear_bit(dw, CH_EN, dwc->mask);
1717 pm_runtime_put_sync_suspend(chip->dev);
1720 EXPORT_SYMBOL_GPL(dw_dma_remove);
1722 int dw_dma_disable(struct dw_dma_chip *chip)
1724 struct dw_dma *dw = chip->dw;
1729 EXPORT_SYMBOL_GPL(dw_dma_disable);
1731 int dw_dma_enable(struct dw_dma_chip *chip)
1733 struct dw_dma *dw = chip->dw;
1738 EXPORT_SYMBOL_GPL(dw_dma_enable);
1740 MODULE_LICENSE("GPL v2");
1741 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1742 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1743 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");