2 * Copyright 2013 Emilio López
4 * Emilio López <emilio@elopez.com.ar>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
20 #include <linux/of_address.h>
21 #include <linux/reset-controller.h>
22 #include <linux/spinlock.h>
23 #include <linux/log2.h>
25 #include "clk-factors.h"
27 static DEFINE_SPINLOCK(clk_lock);
30 * sun6i_a31_ahb1_clk_setup() - Setup function for a31 ahb1 composite clk
33 #define SUN6I_AHB1_MAX_PARENTS 4
34 #define SUN6I_AHB1_MUX_PARENT_PLL6 3
35 #define SUN6I_AHB1_MUX_SHIFT 12
36 /* un-shifted mask is what mux_clk expects */
37 #define SUN6I_AHB1_MUX_MASK 0x3
38 #define SUN6I_AHB1_MUX_GET_PARENT(reg) ((reg >> SUN6I_AHB1_MUX_SHIFT) & \
41 #define SUN6I_AHB1_DIV_SHIFT 4
42 #define SUN6I_AHB1_DIV_MASK (0x3 << SUN6I_AHB1_DIV_SHIFT)
43 #define SUN6I_AHB1_DIV_GET(reg) ((reg & SUN6I_AHB1_DIV_MASK) >> \
45 #define SUN6I_AHB1_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_DIV_MASK) | \
46 (div << SUN6I_AHB1_DIV_SHIFT))
47 #define SUN6I_AHB1_PLL6_DIV_SHIFT 6
48 #define SUN6I_AHB1_PLL6_DIV_MASK (0x3 << SUN6I_AHB1_PLL6_DIV_SHIFT)
49 #define SUN6I_AHB1_PLL6_DIV_GET(reg) ((reg & SUN6I_AHB1_PLL6_DIV_MASK) >> \
50 SUN6I_AHB1_PLL6_DIV_SHIFT)
51 #define SUN6I_AHB1_PLL6_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_PLL6_DIV_MASK) | \
52 (div << SUN6I_AHB1_PLL6_DIV_SHIFT))
54 struct sun6i_ahb1_clk {
59 #define to_sun6i_ahb1_clk(_hw) container_of(_hw, struct sun6i_ahb1_clk, hw)
61 static unsigned long sun6i_ahb1_clk_recalc_rate(struct clk_hw *hw,
62 unsigned long parent_rate)
64 struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
68 /* Fetch the register value */
69 reg = readl(ahb1->reg);
71 /* apply pre-divider first if parent is pll6 */
72 if (SUN6I_AHB1_MUX_GET_PARENT(reg) == SUN6I_AHB1_MUX_PARENT_PLL6)
73 parent_rate /= SUN6I_AHB1_PLL6_DIV_GET(reg) + 1;
76 rate = parent_rate >> SUN6I_AHB1_DIV_GET(reg);
81 static long sun6i_ahb1_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp,
82 u8 parent, unsigned long parent_rate)
84 u8 div, calcp, calcm = 1;
87 * clock can only divide, so we will never be able to achieve
88 * frequencies higher than the parent frequency
90 if (parent_rate && rate > parent_rate)
93 div = DIV_ROUND_UP(parent_rate, rate);
95 /* calculate pre-divider if parent is pll6 */
96 if (parent == SUN6I_AHB1_MUX_PARENT_PLL6) {
101 else if (div / 4 < 4)
106 calcm = DIV_ROUND_UP(div, 1 << calcp);
108 calcp = __roundup_pow_of_two(div);
109 calcp = calcp > 3 ? 3 : calcp;
112 /* we were asked to pass back divider values */
115 *pre_divp = calcm - 1;
118 return (parent_rate / calcm) >> calcp;
121 static long sun6i_ahb1_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
122 unsigned long min_rate,
123 unsigned long max_rate,
124 unsigned long *best_parent_rate,
125 struct clk_hw **best_parent_clk)
127 struct clk *clk = hw->clk, *parent, *best_parent = NULL;
129 unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
131 /* find the parent that can help provide the fastest rate <= rate */
132 num_parents = __clk_get_num_parents(clk);
133 for (i = 0; i < num_parents; i++) {
134 parent = clk_get_parent_by_index(clk, i);
137 if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
138 parent_rate = __clk_round_rate(parent, rate);
140 parent_rate = __clk_get_rate(parent);
142 child_rate = sun6i_ahb1_clk_round(rate, NULL, NULL, i,
145 if (child_rate <= rate && child_rate > best_child_rate) {
146 best_parent = parent;
148 best_child_rate = child_rate;
153 *best_parent_clk = __clk_get_hw(best_parent);
154 *best_parent_rate = best;
156 return best_child_rate;
159 static int sun6i_ahb1_clk_set_rate(struct clk_hw *hw, unsigned long rate,
160 unsigned long parent_rate)
162 struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
164 u8 div, pre_div, parent;
167 spin_lock_irqsave(&clk_lock, flags);
169 reg = readl(ahb1->reg);
171 /* need to know which parent is used to apply pre-divider */
172 parent = SUN6I_AHB1_MUX_GET_PARENT(reg);
173 sun6i_ahb1_clk_round(rate, &div, &pre_div, parent, parent_rate);
175 reg = SUN6I_AHB1_DIV_SET(reg, div);
176 reg = SUN6I_AHB1_PLL6_DIV_SET(reg, pre_div);
177 writel(reg, ahb1->reg);
179 spin_unlock_irqrestore(&clk_lock, flags);
184 static const struct clk_ops sun6i_ahb1_clk_ops = {
185 .determine_rate = sun6i_ahb1_clk_determine_rate,
186 .recalc_rate = sun6i_ahb1_clk_recalc_rate,
187 .set_rate = sun6i_ahb1_clk_set_rate,
190 static void __init sun6i_ahb1_clk_setup(struct device_node *node)
193 struct sun6i_ahb1_clk *ahb1;
195 const char *clk_name = node->name;
196 const char *parents[SUN6I_AHB1_MAX_PARENTS];
200 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
202 /* we have a mux, we will have >1 parents */
203 while (i < SUN6I_AHB1_MAX_PARENTS &&
204 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
207 of_property_read_string(node, "clock-output-names", &clk_name);
209 ahb1 = kzalloc(sizeof(struct sun6i_ahb1_clk), GFP_KERNEL);
213 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
219 /* set up clock properties */
221 mux->shift = SUN6I_AHB1_MUX_SHIFT;
222 mux->mask = SUN6I_AHB1_MUX_MASK;
223 mux->lock = &clk_lock;
226 clk = clk_register_composite(NULL, clk_name, parents, i,
227 &mux->hw, &clk_mux_ops,
228 &ahb1->hw, &sun6i_ahb1_clk_ops,
232 of_clk_add_provider(node, of_clk_src_simple_get, clk);
233 clk_register_clkdev(clk, clk_name, NULL);
236 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk", sun6i_ahb1_clk_setup);
238 /* Maximum number of parents our clocks have */
239 #define SUNXI_MAX_PARENTS 5
242 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
243 * PLL1 rate is calculated as follows
244 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
245 * parent_rate is always 24Mhz
248 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
249 u8 *n, u8 *k, u8 *m, u8 *p)
253 /* Normalize value to a 6M multiple */
254 div = *freq / 6000000;
255 *freq = 6000000 * div;
257 /* we were called to round the frequency, we can now return */
261 /* m is always zero for pll1 */
264 /* k is 1 only on these cases */
265 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
270 /* p will be 3 for divs under 10 */
274 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
275 else if (div < 20 || (div < 32 && (div & 1)))
278 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
279 * of divs between 40-62 */
280 else if (div < 40 || (div < 64 && (div & 2)))
283 /* any other entries have p = 0 */
287 /* calculate a suitable n based on k and p */
294 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
295 * PLL1 rate is calculated as follows
296 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
297 * parent_rate should always be 24MHz
299 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
300 u8 *n, u8 *k, u8 *m, u8 *p)
303 * We can operate only on MHz, this will make our life easier
306 u32 freq_mhz = *freq / 1000000;
307 u32 parent_freq_mhz = parent_rate / 1000000;
310 * Round down the frequency to the closest multiple of either
313 u32 round_freq_6 = round_down(freq_mhz, 6);
314 u32 round_freq_16 = round_down(freq_mhz, 16);
316 if (round_freq_6 > round_freq_16)
317 freq_mhz = round_freq_6;
319 freq_mhz = round_freq_16;
321 *freq = freq_mhz * 1000000;
324 * If the factors pointer are null, we were just called to
325 * round down the frequency.
331 /* If the frequency is a multiple of 32 MHz, k is always 3 */
332 if (!(freq_mhz % 32))
334 /* If the frequency is a multiple of 9 MHz, k is always 2 */
335 else if (!(freq_mhz % 9))
337 /* If the frequency is a multiple of 8 MHz, k is always 1 */
338 else if (!(freq_mhz % 8))
340 /* Otherwise, we don't use the k factor */
345 * If the frequency is a multiple of 2 but not a multiple of
346 * 3, m is 3. This is the first time we use 6 here, yet we
347 * will use it on several other places.
348 * We use this number because it's the lowest frequency we can
349 * generate (with n = 0, k = 0, m = 3), so every other frequency
350 * somehow relates to this frequency.
352 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
355 * If the frequency is a multiple of 6MHz, but the factor is
358 else if ((freq_mhz / 6) & 1)
360 /* Otherwise, we end up with m = 1 */
364 /* Calculate n thanks to the above factors we already got */
365 *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
368 * If n end up being outbound, and that we can still decrease
371 if ((*n + 1) > 31 && (*m + 1) > 1) {
372 *n = (*n + 1) / 2 - 1;
373 *m = (*m + 1) / 2 - 1;
378 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
379 * PLL1 rate is calculated as follows
380 * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
381 * parent_rate is always 24Mhz
384 static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate,
385 u8 *n, u8 *k, u8 *m, u8 *p)
389 /* Normalize value to a 6M multiple */
390 div = *freq / 6000000;
391 *freq = 6000000 * div;
393 /* we were called to round the frequency, we can now return */
397 /* m is always zero for pll1 */
400 /* k is 1 only on these cases */
401 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
406 /* p will be 2 for divs under 20 and odd divs under 32 */
407 if (div < 20 || (div < 32 && (div & 1)))
410 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
411 * of divs between 40-62 */
412 else if (div < 40 || (div < 64 && (div & 2)))
415 /* any other entries have p = 0 */
419 /* calculate a suitable n based on k and p */
426 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
427 * PLL5 rate is calculated as follows
428 * rate = parent_rate * n * (k + 1)
429 * parent_rate is always 24Mhz
432 static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
433 u8 *n, u8 *k, u8 *m, u8 *p)
437 /* Normalize value to a parent_rate multiple (24M) */
438 div = *freq / parent_rate;
439 *freq = parent_rate * div;
441 /* we were called to round the frequency, we can now return */
447 else if (div / 2 < 31)
449 else if (div / 3 < 31)
454 *n = DIV_ROUND_UP(div, (*k+1));
458 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
459 * PLL6x2 rate is calculated as follows
460 * rate = parent_rate * (n + 1) * (k + 1)
461 * parent_rate is always 24Mhz
464 static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
465 u8 *n, u8 *k, u8 *m, u8 *p)
469 /* Normalize value to a parent_rate multiple (24M) */
470 div = *freq / parent_rate;
471 *freq = parent_rate * div;
473 /* we were called to round the frequency, we can now return */
481 *n = DIV_ROUND_UP(div, (*k+1)) - 1;
485 * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
486 * AHB rate is calculated as follows
487 * rate = parent_rate >> p
490 static void sun5i_a13_get_ahb_factors(u32 *freq, u32 parent_rate,
491 u8 *n, u8 *k, u8 *m, u8 *p)
496 if (parent_rate < *freq)
500 * user manual says valid speed is 8k ~ 276M, but tests show it
501 * can work at speeds up to 300M, just after reparenting to pll6
505 if (*freq > 300000000)
508 div = order_base_2(DIV_ROUND_UP(parent_rate, *freq));
514 *freq = parent_rate >> div;
516 /* we were called to round the frequency, we can now return */
524 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
525 * APB1 rate is calculated as follows
526 * rate = (parent_rate >> p) / (m + 1);
529 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
530 u8 *n, u8 *k, u8 *m, u8 *p)
534 if (parent_rate < *freq)
537 parent_rate = DIV_ROUND_UP(parent_rate, *freq);
540 if (parent_rate > 32)
543 if (parent_rate <= 4)
545 else if (parent_rate <= 8)
547 else if (parent_rate <= 16)
552 calcm = (parent_rate >> calcp) - 1;
554 *freq = (parent_rate >> calcp) / (calcm + 1);
556 /* we were called to round the frequency, we can now return */
568 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
569 * CLK_OUT rate is calculated as follows
570 * rate = (parent_rate >> p) / (m + 1);
573 static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
574 u8 *n, u8 *k, u8 *m, u8 *p)
576 u8 div, calcm, calcp;
578 /* These clocks can only divide, so we will never be able to achieve
579 * frequencies higher than the parent frequency */
580 if (*freq > parent_rate)
583 div = DIV_ROUND_UP(parent_rate, *freq);
587 else if (div / 2 < 32)
589 else if (div / 4 < 32)
594 calcm = DIV_ROUND_UP(div, 1 << calcp);
596 *freq = (parent_rate >> calcp) / calcm;
598 /* we were called to round the frequency, we can now return */
607 * sunxi_factors_clk_setup() - Setup function for factor clocks
610 static struct clk_factors_config sun4i_pll1_config = {
621 static struct clk_factors_config sun6i_a31_pll1_config = {
631 static struct clk_factors_config sun8i_a23_pll1_config = {
643 static struct clk_factors_config sun4i_pll5_config = {
650 static struct clk_factors_config sun6i_a31_pll6_config = {
658 static struct clk_factors_config sun5i_a13_ahb_config = {
663 static struct clk_factors_config sun4i_apb1_config = {
670 /* user manual says "n" but it's really "p" */
671 static struct clk_factors_config sun7i_a20_out_config = {
678 static const struct factors_data sun4i_pll1_data __initconst = {
680 .table = &sun4i_pll1_config,
681 .getter = sun4i_get_pll1_factors,
684 static const struct factors_data sun6i_a31_pll1_data __initconst = {
686 .table = &sun6i_a31_pll1_config,
687 .getter = sun6i_a31_get_pll1_factors,
690 static const struct factors_data sun8i_a23_pll1_data __initconst = {
692 .table = &sun8i_a23_pll1_config,
693 .getter = sun8i_a23_get_pll1_factors,
696 static const struct factors_data sun7i_a20_pll4_data __initconst = {
698 .table = &sun4i_pll5_config,
699 .getter = sun4i_get_pll5_factors,
702 static const struct factors_data sun4i_pll5_data __initconst = {
704 .table = &sun4i_pll5_config,
705 .getter = sun4i_get_pll5_factors,
709 static const struct factors_data sun4i_pll6_data __initconst = {
711 .table = &sun4i_pll5_config,
712 .getter = sun4i_get_pll5_factors,
716 static const struct factors_data sun6i_a31_pll6_data __initconst = {
718 .table = &sun6i_a31_pll6_config,
719 .getter = sun6i_a31_get_pll6_factors,
723 static const struct factors_data sun5i_a13_ahb_data __initconst = {
725 .muxmask = BIT(1) | BIT(0),
726 .table = &sun5i_a13_ahb_config,
727 .getter = sun5i_a13_get_ahb_factors,
730 static const struct factors_data sun4i_apb1_data __initconst = {
732 .muxmask = BIT(1) | BIT(0),
733 .table = &sun4i_apb1_config,
734 .getter = sun4i_get_apb1_factors,
737 static const struct factors_data sun7i_a20_out_data __initconst = {
740 .muxmask = BIT(1) | BIT(0),
741 .table = &sun7i_a20_out_config,
742 .getter = sun7i_a20_get_out_factors,
745 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
746 const struct factors_data *data)
750 reg = of_iomap(node, 0);
752 pr_err("Could not get registers for factors-clk: %s\n",
757 return sunxi_factors_register(node, data, &clk_lock, reg);
763 * sunxi_mux_clk_setup() - Setup function for muxes
766 #define SUNXI_MUX_GATE_WIDTH 2
772 static const struct mux_data sun4i_cpu_mux_data __initconst = {
776 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
780 static void __init sunxi_mux_clk_setup(struct device_node *node,
781 struct mux_data *data)
784 const char *clk_name = node->name;
785 const char *parents[SUNXI_MAX_PARENTS];
789 reg = of_iomap(node, 0);
791 while (i < SUNXI_MAX_PARENTS &&
792 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
795 of_property_read_string(node, "clock-output-names", &clk_name);
797 clk = clk_register_mux(NULL, clk_name, parents, i,
798 CLK_SET_RATE_PARENT, reg,
799 data->shift, SUNXI_MUX_GATE_WIDTH,
803 of_clk_add_provider(node, of_clk_src_simple_get, clk);
804 clk_register_clkdev(clk, clk_name, NULL);
811 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
818 const struct clk_div_table *table;
821 static const struct div_data sun4i_axi_data __initconst = {
827 static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
828 { .val = 0, .div = 1 },
829 { .val = 1, .div = 2 },
830 { .val = 2, .div = 3 },
831 { .val = 3, .div = 4 },
832 { .val = 4, .div = 4 },
833 { .val = 5, .div = 4 },
834 { .val = 6, .div = 4 },
835 { .val = 7, .div = 4 },
839 static const struct div_data sun8i_a23_axi_data __initconst = {
841 .table = sun8i_a23_axi_table,
844 static const struct div_data sun4i_ahb_data __initconst = {
850 static const struct clk_div_table sun4i_apb0_table[] __initconst = {
851 { .val = 0, .div = 2 },
852 { .val = 1, .div = 2 },
853 { .val = 2, .div = 4 },
854 { .val = 3, .div = 8 },
858 static const struct div_data sun4i_apb0_data __initconst = {
862 .table = sun4i_apb0_table,
865 static void __init sunxi_divider_clk_setup(struct device_node *node,
866 struct div_data *data)
869 const char *clk_name = node->name;
870 const char *clk_parent;
873 reg = of_iomap(node, 0);
875 clk_parent = of_clk_get_parent_name(node, 0);
877 of_property_read_string(node, "clock-output-names", &clk_name);
879 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
880 reg, data->shift, data->width,
881 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
882 data->table, &clk_lock);
884 of_clk_add_provider(node, of_clk_src_simple_get, clk);
885 clk_register_clkdev(clk, clk_name, NULL);
892 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
895 #define SUNXI_GATES_MAX_SIZE 64
898 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
901 static const struct gates_data sun4i_axi_gates_data __initconst = {
905 static const struct gates_data sun4i_ahb_gates_data __initconst = {
906 .mask = {0x7F77FFF, 0x14FB3F},
909 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
910 .mask = {0x147667e7, 0x185915},
913 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
914 .mask = {0x107067e7, 0x185111},
917 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
918 .mask = {0xEDFE7F62, 0x794F931},
921 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
922 .mask = { 0x12f77fff, 0x16ff3f },
925 static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
926 .mask = {0x25386742, 0x2505111},
929 static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
933 static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
937 static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
941 static const struct gates_data sun4i_apb0_gates_data __initconst = {
945 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
949 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
953 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
957 static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
961 static const struct gates_data sun4i_apb1_gates_data __initconst = {
965 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
969 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
973 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
977 static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
981 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
985 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
986 .mask = { 0xff80ff },
989 static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
993 static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
997 static void __init sunxi_gates_clk_setup(struct device_node *node,
998 struct gates_data *data)
1000 struct clk_onecell_data *clk_data;
1001 const char *clk_parent;
1002 const char *clk_name;
1008 reg = of_iomap(node, 0);
1010 clk_parent = of_clk_get_parent_name(node, 0);
1012 /* Worst-case size approximation and memory allocation */
1013 qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
1014 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1017 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
1018 if (!clk_data->clks) {
1023 for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
1024 of_property_read_string_index(node, "clock-output-names",
1027 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
1029 reg + 4 * (i/32), i % 32,
1031 WARN_ON(IS_ERR(clk_data->clks[i]));
1032 clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
1037 /* Adjust to the real max */
1038 clk_data->clk_num = i;
1040 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1046 * sunxi_divs_clk_setup() helper data
1049 #define SUNXI_DIVS_MAX_QTY 4
1050 #define SUNXI_DIVISOR_WIDTH 2
1053 const struct factors_data *factors; /* data for the factor clock */
1054 int ndivs; /* number of outputs */
1056 * List of outputs. Refer to the diagram for sunxi_divs_clk_setup():
1057 * self or base factor clock refers to the output from the pll
1058 * itself. The remaining refer to fixed or configurable divider
1062 u8 self; /* is it the base factor clock? (only one) */
1063 u8 fixed; /* is it a fixed divisor? if not... */
1064 struct clk_div_table *table; /* is it a table based divisor? */
1065 u8 shift; /* otherwise it's a normal divisor with this shift */
1066 u8 pow; /* is it power-of-two based? */
1067 u8 gate; /* is it independently gateable? */
1068 } div[SUNXI_DIVS_MAX_QTY];
1071 static struct clk_div_table pll6_sata_tbl[] = {
1072 { .val = 0, .div = 6, },
1073 { .val = 1, .div = 12, },
1074 { .val = 2, .div = 18, },
1075 { .val = 3, .div = 24, },
1079 static const struct divs_data pll5_divs_data __initconst = {
1080 .factors = &sun4i_pll5_data,
1083 { .shift = 0, .pow = 0, }, /* M, DDR */
1084 { .shift = 16, .pow = 1, }, /* P, other */
1085 /* No output for the base factor clock */
1089 static const struct divs_data pll6_divs_data __initconst = {
1090 .factors = &sun4i_pll6_data,
1093 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
1094 { .fixed = 2 }, /* P, other */
1095 { .self = 1 }, /* base factor clock, 2x */
1096 { .fixed = 4 }, /* pll6 / 4, used as ahb input */
1100 static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
1101 .factors = &sun6i_a31_pll6_data,
1104 { .fixed = 2 }, /* normal output */
1105 { .self = 1 }, /* base factor clock, 2x */
1110 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
1112 * These clocks look something like this
1113 * ________________________
1114 * | ___divisor 1---|----> to consumer
1115 * parent >--| pll___/___divisor 2---|----> to consumer
1116 * | \_______________|____> to consumer
1117 * |________________________|
1120 static void __init sunxi_divs_clk_setup(struct device_node *node,
1121 struct divs_data *data)
1123 struct clk_onecell_data *clk_data;
1125 const char *clk_name;
1126 struct clk **clks, *pclk;
1127 struct clk_hw *gate_hw, *rate_hw;
1128 const struct clk_ops *rate_ops;
1129 struct clk_gate *gate = NULL;
1130 struct clk_fixed_factor *fix_factor;
1131 struct clk_divider *divider;
1133 int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
1134 int flags, clkflags;
1136 /* if number of children known, use it */
1138 ndivs = data->ndivs;
1140 /* Set up factor clock that we will be dividing */
1141 pclk = sunxi_factors_clk_setup(node, data->factors);
1142 parent = __clk_get_name(pclk);
1144 reg = of_iomap(node, 0);
1146 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1150 clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
1154 clk_data->clks = clks;
1156 /* It's not a good idea to have automatic reparenting changing
1158 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
1160 for (i = 0; i < ndivs; i++) {
1161 if (of_property_read_string_index(node, "clock-output-names",
1165 /* If this is the base factor clock, only update clks */
1166 if (data->div[i].self) {
1167 clk_data->clks[i] = pclk;
1175 /* If this leaf clock can be gated, create a gate */
1176 if (data->div[i].gate) {
1177 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1182 gate->bit_idx = data->div[i].gate;
1183 gate->lock = &clk_lock;
1185 gate_hw = &gate->hw;
1188 /* Leaves can be fixed or configurable divisors */
1189 if (data->div[i].fixed) {
1190 fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1194 fix_factor->mult = 1;
1195 fix_factor->div = data->div[i].fixed;
1197 rate_hw = &fix_factor->hw;
1198 rate_ops = &clk_fixed_factor_ops;
1200 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1204 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1207 divider->shift = data->div[i].shift;
1208 divider->width = SUNXI_DIVISOR_WIDTH;
1209 divider->flags = flags;
1210 divider->lock = &clk_lock;
1211 divider->table = data->div[i].table;
1213 rate_hw = ÷r->hw;
1214 rate_ops = &clk_divider_ops;
1217 /* Wrap the (potential) gate and the divisor on a composite
1218 * clock to unify them */
1219 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1222 gate_hw, &clk_gate_ops,
1225 WARN_ON(IS_ERR(clk_data->clks[i]));
1226 clk_register_clkdev(clks[i], clk_name, NULL);
1229 /* Adjust to the real max */
1230 clk_data->clk_num = i;
1232 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1246 /* Matches for factors clocks */
1247 static const struct of_device_id clk_factors_match[] __initconst = {
1248 {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
1249 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
1250 {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
1251 {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
1252 {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
1253 {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
1254 {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
1258 /* Matches for divider clocks */
1259 static const struct of_device_id clk_div_match[] __initconst = {
1260 {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
1261 {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
1262 {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
1263 {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
1267 /* Matches for divided outputs */
1268 static const struct of_device_id clk_divs_match[] __initconst = {
1269 {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
1270 {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
1271 {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
1275 /* Matches for mux clocks */
1276 static const struct of_device_id clk_mux_match[] __initconst = {
1277 {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
1278 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
1282 /* Matches for gate clocks */
1283 static const struct of_device_id clk_gates_match[] __initconst = {
1284 {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
1285 {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
1286 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
1287 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
1288 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
1289 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
1290 {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
1291 {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
1292 {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
1293 {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
1294 {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
1295 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
1296 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
1297 {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
1298 {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
1299 {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
1300 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
1301 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
1302 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
1303 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
1304 {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
1305 {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
1306 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1307 {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
1311 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
1314 struct device_node *np;
1315 const struct div_data *data;
1316 const struct of_device_id *match;
1317 void (*setup_function)(struct device_node *, const void *) = function;
1319 for_each_matching_node_and_match(np, clk_match, &match) {
1321 setup_function(np, data);
1325 static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
1329 /* Register divided output clocks */
1330 of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1332 /* Register factor clocks */
1333 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
1335 /* Register divider clocks */
1336 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
1338 /* Register mux clocks */
1339 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
1341 /* Register gate clocks */
1342 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
1344 /* Protect the clocks that needs to stay on */
1345 for (i = 0; i < nclocks; i++) {
1346 struct clk *clk = clk_get(NULL, clocks[i]);
1349 clk_prepare_enable(clk);
1353 static const char *sun4i_a10_critical_clocks[] __initdata = {
1358 static void __init sun4i_a10_init_clocks(struct device_node *node)
1360 sunxi_init_clocks(sun4i_a10_critical_clocks,
1361 ARRAY_SIZE(sun4i_a10_critical_clocks));
1363 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
1365 static const char *sun5i_critical_clocks[] __initdata = {
1371 static void __init sun5i_init_clocks(struct device_node *node)
1373 sunxi_init_clocks(sun5i_critical_clocks,
1374 ARRAY_SIZE(sun5i_critical_clocks));
1376 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks);
1377 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks);
1378 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
1380 static const char *sun6i_critical_clocks[] __initdata = {
1384 static void __init sun6i_init_clocks(struct device_node *node)
1386 sunxi_init_clocks(sun6i_critical_clocks,
1387 ARRAY_SIZE(sun6i_critical_clocks));
1389 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
1390 CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
1391 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
1393 static void __init sun9i_init_clocks(struct device_node *node)
1395 sunxi_init_clocks(NULL, 0);
1397 CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);