2 * clkgen-mux.c: ST GEN-MUX Clock driver
4 * Copyright (C) 2014 STMicroelectronics (R&D) Limited
6 * Authors: Stephen Gallimore <stephen.gallimore@st.com>
7 * Pankaj Dev <pankaj.dev@st.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
16 #include <linux/slab.h>
17 #include <linux/of_address.h>
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
22 static DEFINE_SPINLOCK(clkgena_divmux_lock);
23 static DEFINE_SPINLOCK(clkgenf_lock);
25 static const char ** __init clkgen_mux_get_parents(struct device_node *np,
31 nparents = of_clk_get_parent_count(np);
32 if (WARN_ON(nparents <= 0))
33 return ERR_PTR(-EINVAL);
35 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
37 return ERR_PTR(-ENOMEM);
39 *num_parents = of_clk_parent_fill(np, parents, nparents);
44 * DOC: Clock mux with a programmable divider on each of its three inputs.
45 * The mux has an input setting which effectively gates its output.
47 * Traits of this clock:
48 * prepare - clk_(un)prepare only ensures parent is (un)prepared
49 * enable - clk_enable and clk_disable are functional & control gating
50 * rate - set rate is supported
51 * parent - set/get parent
56 struct clkgena_divmux {
58 /* Subclassed mux and divider structures */
60 struct clk_divider div[NUM_INPUTS];
61 /* Enable/running feedback register bits for each input */
62 void __iomem *feedback_reg[NUM_INPUTS];
68 #define to_clkgena_divmux(_hw) container_of(_hw, struct clkgena_divmux, hw)
70 struct clkgena_divmux_data {
75 int div_offsets[NUM_INPUTS];
76 int fb_offsets[NUM_INPUTS];
80 #define CKGAX_CLKOPSRC_SWITCH_OFF 0x3
82 static int clkgena_divmux_is_running(struct clkgena_divmux *mux)
84 u32 regval = readl(mux->feedback_reg[mux->muxsel]);
85 u32 running = regval & BIT(mux->feedback_bit_idx);
89 static int clkgena_divmux_enable(struct clk_hw *hw)
91 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
92 struct clk_hw *mux_hw = &genamux->mux.hw;
93 unsigned long timeout;
96 __clk_hw_set_clk(mux_hw, hw);
98 ret = clk_mux_ops.set_parent(mux_hw, genamux->muxsel);
102 timeout = jiffies + msecs_to_jiffies(10);
104 while (!clkgena_divmux_is_running(genamux)) {
105 if (time_after(jiffies, timeout))
113 static void clkgena_divmux_disable(struct clk_hw *hw)
115 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
116 struct clk_hw *mux_hw = &genamux->mux.hw;
118 __clk_hw_set_clk(mux_hw, hw);
120 clk_mux_ops.set_parent(mux_hw, CKGAX_CLKOPSRC_SWITCH_OFF);
123 static int clkgena_divmux_is_enabled(struct clk_hw *hw)
125 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
126 struct clk_hw *mux_hw = &genamux->mux.hw;
128 __clk_hw_set_clk(mux_hw, hw);
130 return (s8)clk_mux_ops.get_parent(mux_hw) > 0;
133 static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
135 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
136 struct clk_hw *mux_hw = &genamux->mux.hw;
138 __clk_hw_set_clk(mux_hw, hw);
140 genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
141 if ((s8)genamux->muxsel < 0) {
142 pr_debug("%s: %s: Invalid parent, setting to default.\n",
143 __func__, clk_hw_get_name(hw));
147 return genamux->muxsel;
150 static int clkgena_divmux_set_parent(struct clk_hw *hw, u8 index)
152 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
154 if (index >= CKGAX_CLKOPSRC_SWITCH_OFF)
157 genamux->muxsel = index;
160 * If the mux is already enabled, call enable directly to set the
161 * new mux position and wait for it to start running again. Otherwise
164 if (clkgena_divmux_is_enabled(hw))
165 clkgena_divmux_enable(hw);
170 static unsigned long clkgena_divmux_recalc_rate(struct clk_hw *hw,
171 unsigned long parent_rate)
173 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
174 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
176 __clk_hw_set_clk(div_hw, hw);
178 return clk_divider_ops.recalc_rate(div_hw, parent_rate);
181 static int clkgena_divmux_set_rate(struct clk_hw *hw, unsigned long rate,
182 unsigned long parent_rate)
184 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
185 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
187 __clk_hw_set_clk(div_hw, hw);
189 return clk_divider_ops.set_rate(div_hw, rate, parent_rate);
192 static long clkgena_divmux_round_rate(struct clk_hw *hw, unsigned long rate,
193 unsigned long *prate)
195 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
196 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
198 __clk_hw_set_clk(div_hw, hw);
200 return clk_divider_ops.round_rate(div_hw, rate, prate);
203 static const struct clk_ops clkgena_divmux_ops = {
204 .enable = clkgena_divmux_enable,
205 .disable = clkgena_divmux_disable,
206 .is_enabled = clkgena_divmux_is_enabled,
207 .get_parent = clkgena_divmux_get_parent,
208 .set_parent = clkgena_divmux_set_parent,
209 .round_rate = clkgena_divmux_round_rate,
210 .recalc_rate = clkgena_divmux_recalc_rate,
211 .set_rate = clkgena_divmux_set_rate,
215 * clk_register_genamux - register a genamux clock with the clock framework
217 static struct clk * __init clk_register_genamux(const char *name,
218 const char **parent_names, u8 num_parents,
220 const struct clkgena_divmux_data *muxdata,
224 * Fixed constants across all ClockgenA variants
226 const int mux_width = 2;
227 const int divider_width = 5;
228 struct clkgena_divmux *genamux;
230 struct clk_init_data init;
233 genamux = kzalloc(sizeof(*genamux), GFP_KERNEL);
235 return ERR_PTR(-ENOMEM);
238 init.ops = &clkgena_divmux_ops;
239 init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
240 init.parent_names = parent_names;
241 init.num_parents = num_parents;
243 genamux->mux.lock = &clkgena_divmux_lock;
244 genamux->mux.mask = BIT(mux_width) - 1;
245 genamux->mux.shift = muxdata->mux_start_bit + (idx * mux_width);
246 if (genamux->mux.shift > 31) {
248 * We have spilled into the second mux register so
249 * adjust the register address and the bit shift accordingly
251 genamux->mux.reg = reg + muxdata->mux_offset2;
252 genamux->mux.shift -= 32;
254 genamux->mux.reg = reg + muxdata->mux_offset;
257 for (i = 0; i < NUM_INPUTS; i++) {
259 * Divider config for each input
261 void __iomem *divbase = reg + muxdata->div_offsets[i];
262 genamux->div[i].width = divider_width;
263 genamux->div[i].reg = divbase + (idx * sizeof(u32));
266 * Mux enabled/running feedback register for each input.
268 genamux->feedback_reg[i] = reg + muxdata->fb_offsets[i];
271 genamux->feedback_bit_idx = muxdata->fb_start_bit_idx + idx;
272 genamux->hw.init = &init;
274 clk = clk_register(NULL, &genamux->hw);
280 pr_debug("%s: parent %s rate %lu\n",
282 __clk_get_name(clk_get_parent(clk)),
288 static struct clkgena_divmux_data st_divmux_c65hs = {
292 .div_offsets = { 0x800, 0x900, 0xb00 },
293 .fb_offsets = { 0x18, 0x1c, 0x20 },
294 .fb_start_bit_idx = 0,
297 static struct clkgena_divmux_data st_divmux_c65ls = {
302 .div_offsets = { 0x810, 0xa10, 0xb10 },
303 .fb_offsets = { 0x18, 0x1c, 0x20 },
304 .fb_start_bit_idx = 4,
307 static struct clkgena_divmux_data st_divmux_c32odf0 = {
311 .div_offsets = { 0x800, 0x900, 0xa60 },
312 .fb_offsets = { 0x2c, 0x24, 0x28 },
313 .fb_start_bit_idx = 0,
316 static struct clkgena_divmux_data st_divmux_c32odf1 = {
320 .div_offsets = { 0x820, 0x980, 0xa80 },
321 .fb_offsets = { 0x2c, 0x24, 0x28 },
322 .fb_start_bit_idx = 8,
325 static struct clkgena_divmux_data st_divmux_c32odf2 = {
329 .div_offsets = { 0x840, 0xa20, 0xb10 },
330 .fb_offsets = { 0x2c, 0x24, 0x28 },
331 .fb_start_bit_idx = 16,
334 static struct clkgena_divmux_data st_divmux_c32odf3 = {
338 .div_offsets = { 0x860, 0xa40, 0xb30 },
339 .fb_offsets = { 0x2c, 0x24, 0x28 },
340 .fb_start_bit_idx = 24,
343 static const struct of_device_id clkgena_divmux_of_match[] = {
345 .compatible = "st,clkgena-divmux-c65-hs",
346 .data = &st_divmux_c65hs,
349 .compatible = "st,clkgena-divmux-c65-ls",
350 .data = &st_divmux_c65ls,
353 .compatible = "st,clkgena-divmux-c32-odf0",
354 .data = &st_divmux_c32odf0,
357 .compatible = "st,clkgena-divmux-c32-odf1",
358 .data = &st_divmux_c32odf1,
361 .compatible = "st,clkgena-divmux-c32-odf2",
362 .data = &st_divmux_c32odf2,
365 .compatible = "st,clkgena-divmux-c32-odf3",
366 .data = &st_divmux_c32odf3,
371 static void __iomem * __init clkgen_get_register_base(struct device_node *np)
373 struct device_node *pnode;
376 pnode = of_get_parent(np);
380 reg = of_iomap(pnode, 0);
386 static void __init st_of_clkgena_divmux_setup(struct device_node *np)
388 const struct of_device_id *match;
389 const struct clkgena_divmux_data *data;
390 struct clk_onecell_data *clk_data;
392 const char **parents;
393 int num_parents = 0, i;
395 match = of_match_node(clkgena_divmux_of_match, np);
401 reg = clkgen_get_register_base(np);
405 parents = clkgen_mux_get_parents(np, &num_parents);
409 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
413 clk_data->clk_num = data->num_outputs;
414 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
420 for (i = 0; i < clk_data->clk_num; i++) {
422 const char *clk_name;
424 if (of_property_read_string_index(np, "clock-output-names",
429 * If we read an empty clock name then the output is unused
431 if (*clk_name == '\0')
434 clk = clk_register_genamux(clk_name, parents, num_parents,
440 clk_data->clks[i] = clk;
445 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
448 kfree(clk_data->clks);
456 CLK_OF_DECLARE(clkgenadivmux, "st,clkgena-divmux", st_of_clkgena_divmux_setup);
458 struct clkgena_prediv_data {
461 struct clk_div_table *table;
464 static struct clk_div_table prediv_table16[] = {
465 { .val = 0, .div = 1 },
466 { .val = 1, .div = 16 },
470 static struct clkgena_prediv_data prediv_c65_data = {
473 .table = prediv_table16,
476 static struct clkgena_prediv_data prediv_c32_data = {
479 .table = prediv_table16,
482 static const struct of_device_id clkgena_prediv_of_match[] = {
483 { .compatible = "st,clkgena-prediv-c65", .data = &prediv_c65_data },
484 { .compatible = "st,clkgena-prediv-c32", .data = &prediv_c32_data },
488 static void __init st_of_clkgena_prediv_setup(struct device_node *np)
490 const struct of_device_id *match;
492 const char *parent_name, *clk_name;
494 const struct clkgena_prediv_data *data;
496 match = of_match_node(clkgena_prediv_of_match, np);
498 pr_err("%s: No matching data\n", __func__);
504 reg = clkgen_get_register_base(np);
508 parent_name = of_clk_get_parent_name(np, 0);
512 if (of_property_read_string_index(np, "clock-output-names",
516 clk = clk_register_divider_table(NULL, clk_name, parent_name,
517 CLK_GET_RATE_NOCACHE,
518 reg + data->offset, data->shift, 1,
519 0, data->table, NULL);
523 of_clk_add_provider(np, of_clk_src_simple_get, clk);
524 pr_debug("%s: parent %s rate %u\n",
526 __clk_get_name(clk_get_parent(clk)),
527 (unsigned int)clk_get_rate(clk));
533 CLK_OF_DECLARE(clkgenaprediv, "st,clkgena-prediv", st_of_clkgena_prediv_setup);
535 struct clkgen_mux_data {
540 unsigned long clk_flags;
544 static struct clkgen_mux_data clkgen_mux_c_vcc_hd_416 = {
550 static struct clkgen_mux_data clkgen_mux_f_vcc_fvdp_416 = {
556 static struct clkgen_mux_data clkgen_mux_f_vcc_hva_416 = {
562 static struct clkgen_mux_data clkgen_mux_f_vcc_hd_416 = {
566 .lock = &clkgenf_lock,
569 static struct clkgen_mux_data clkgen_mux_c_vcc_sd_416 = {
573 .lock = &clkgenf_lock,
576 static struct clkgen_mux_data stih415_a9_mux_data = {
580 .lock = &clkgen_a9_lock,
582 static struct clkgen_mux_data stih416_a9_mux_data = {
587 static struct clkgen_mux_data stih407_a9_mux_data = {
591 .lock = &clkgen_a9_lock,
594 static const struct of_device_id mux_of_match[] = {
596 .compatible = "st,stih416-clkgenc-vcc-hd",
597 .data = &clkgen_mux_c_vcc_hd_416,
600 .compatible = "st,stih416-clkgenf-vcc-fvdp",
601 .data = &clkgen_mux_f_vcc_fvdp_416,
604 .compatible = "st,stih416-clkgenf-vcc-hva",
605 .data = &clkgen_mux_f_vcc_hva_416,
608 .compatible = "st,stih416-clkgenf-vcc-hd",
609 .data = &clkgen_mux_f_vcc_hd_416,
612 .compatible = "st,stih416-clkgenf-vcc-sd",
613 .data = &clkgen_mux_c_vcc_sd_416,
616 .compatible = "st,stih415-clkgen-a9-mux",
617 .data = &stih415_a9_mux_data,
620 .compatible = "st,stih416-clkgen-a9-mux",
621 .data = &stih416_a9_mux_data,
624 .compatible = "st,stih407-clkgen-a9-mux",
625 .data = &stih407_a9_mux_data,
630 static void __init st_of_clkgen_mux_setup(struct device_node *np)
632 const struct of_device_id *match;
635 const char **parents;
637 const struct clkgen_mux_data *data;
639 match = of_match_node(mux_of_match, np);
641 pr_err("%s: No matching data\n", __func__);
647 reg = of_iomap(np, 0);
649 pr_err("%s: Failed to get base address\n", __func__);
653 parents = clkgen_mux_get_parents(np, &num_parents);
654 if (IS_ERR(parents)) {
655 pr_err("%s: Failed to get parents (%ld)\n",
656 __func__, PTR_ERR(parents));
660 clk = clk_register_mux(NULL, np->name, parents, num_parents,
661 data->clk_flags | CLK_SET_RATE_PARENT,
663 data->shift, data->width, data->mux_flags,
668 pr_debug("%s: parent %s rate %u\n",
670 __clk_get_name(clk_get_parent(clk)),
671 (unsigned int)clk_get_rate(clk));
674 of_clk_add_provider(np, of_clk_src_simple_get, clk);
682 CLK_OF_DECLARE(clkgen_mux, "st,clkgen-mux", st_of_clkgen_mux_setup);
684 #define VCC_MAX_CHANNELS 16
686 #define VCC_GATE_OFFSET 0x0
687 #define VCC_MUX_OFFSET 0x4
688 #define VCC_DIV_OFFSET 0x8
690 struct clkgen_vcc_data {
692 unsigned long clk_flags;
695 static struct clkgen_vcc_data st_clkgenc_vcc_416 = {
696 .clk_flags = CLK_SET_RATE_PARENT,
699 static struct clkgen_vcc_data st_clkgenf_vcc_416 = {
700 .lock = &clkgenf_lock,
703 static const struct of_device_id vcc_of_match[] = {
704 { .compatible = "st,stih416-clkgenc", .data = &st_clkgenc_vcc_416 },
705 { .compatible = "st,stih416-clkgenf", .data = &st_clkgenf_vcc_416 },
709 static void __init st_of_clkgen_vcc_setup(struct device_node *np)
711 const struct of_device_id *match;
713 const char **parents;
715 struct clk_onecell_data *clk_data;
716 const struct clkgen_vcc_data *data;
718 match = of_match_node(vcc_of_match, np);
723 reg = of_iomap(np, 0);
727 parents = clkgen_mux_get_parents(np, &num_parents);
731 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
735 clk_data->clk_num = VCC_MAX_CHANNELS;
736 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
742 for (i = 0; i < clk_data->clk_num; i++) {
744 const char *clk_name;
745 struct clk_gate *gate;
746 struct clk_divider *div;
749 if (of_property_read_string_index(np, "clock-output-names",
754 * If we read an empty clock name then the output is unused
756 if (*clk_name == '\0')
759 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
763 div = kzalloc(sizeof(*div), GFP_KERNEL);
769 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
776 gate->reg = reg + VCC_GATE_OFFSET;
778 gate->flags = CLK_GATE_SET_TO_DISABLE;
779 gate->lock = data->lock;
781 div->reg = reg + VCC_DIV_OFFSET;
784 div->flags = CLK_DIVIDER_POWER_OF_TWO |
785 CLK_DIVIDER_ROUND_CLOSEST;
787 mux->reg = reg + VCC_MUX_OFFSET;
791 clk = clk_register_composite(NULL, clk_name, parents,
793 &mux->hw, &clk_mux_ops,
794 &div->hw, &clk_divider_ops,
795 &gate->hw, &clk_gate_ops,
797 CLK_GET_RATE_NOCACHE);
805 pr_debug("%s: parent %s rate %u\n",
807 __clk_get_name(clk_get_parent(clk)),
808 (unsigned int)clk_get_rate(clk));
810 clk_data->clks[i] = clk;
815 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
819 for (i = 0; i < clk_data->clk_num; i++) {
820 struct clk_composite *composite;
822 if (!clk_data->clks[i])
825 composite = container_of(__clk_get_hw(clk_data->clks[i]),
826 struct clk_composite, hw);
827 kfree(container_of(composite->gate_hw, struct clk_gate, hw));
828 kfree(container_of(composite->rate_hw, struct clk_divider, hw));
829 kfree(container_of(composite->mux_hw, struct clk_mux, hw));
832 kfree(clk_data->clks);
840 CLK_OF_DECLARE(clkgen_vcc, "st,clkgen-vcc", st_of_clkgen_vcc_setup);