2 * Suspend support specific for i386/x86-64.
4 * Distribute under GPLv2
6 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
7 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
8 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
11 #include <linux/suspend.h>
12 #include <linux/export.h>
13 #include <linux/smp.h>
14 #include <linux/perf_event.h>
16 #include <asm/pgtable.h>
17 #include <asm/proto.h>
22 #include <asm/suspend.h>
23 #include <asm/debugreg.h>
24 #include <asm/fpu-internal.h> /* pcntxt_mask */
26 #include <asm/mmu_context.h>
29 __visible unsigned long saved_context_ebx;
30 __visible unsigned long saved_context_esp, saved_context_ebp;
31 __visible unsigned long saved_context_esi, saved_context_edi;
32 __visible unsigned long saved_context_eflags;
34 struct saved_context saved_context;
37 * __save_processor_state - save CPU registers before creating a
38 * hibernation image and before restoring the memory state from it
39 * @ctxt - structure to store the registers contents in
41 * NOTE: If there is a CPU register the modification of which by the
42 * boot kernel (ie. the kernel used for loading the hibernation image)
43 * might affect the operations of the restored target kernel (ie. the one
44 * saved in the hibernation image), then its contents must be saved by this
45 * function. In other words, if kernel A is hibernated and different
46 * kernel B is used for loading the hibernation image into memory, the
47 * kernel A's __save_processor_state() function must save all registers
48 * needed by kernel A, so that it can operate correctly after the resume
49 * regardless of what kernel B does in the meantime.
51 static void __save_processor_state(struct saved_context *ctxt)
54 mtrr_save_fixed_ranges(NULL);
62 store_idt(&ctxt->idt);
65 store_idt((struct desc_ptr *)&ctxt->idt_limit);
68 * We save it here, but restore it only in the hibernate case.
69 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
70 * mode in "secondary_startup_64". In 32-bit mode it is done via
71 * 'pmode_gdt' in wakeup_start.
73 ctxt->gdt_desc.size = GDT_SIZE - 1;
74 ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_table(smp_processor_id());
78 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
83 savesegment(es, ctxt->es);
84 savesegment(fs, ctxt->fs);
85 savesegment(gs, ctxt->gs);
86 savesegment(ss, ctxt->ss);
89 asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
90 asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
91 asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
92 asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
93 asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
95 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
96 rdmsrl(MSR_GS_BASE, ctxt->gs_base);
97 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
98 mtrr_save_fixed_ranges(NULL);
100 rdmsrl(MSR_EFER, ctxt->efer);
106 ctxt->cr0 = read_cr0();
107 ctxt->cr2 = read_cr2();
108 ctxt->cr3 = read_cr3();
109 ctxt->cr4 = __read_cr4_safe();
111 ctxt->cr8 = read_cr8();
113 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
117 /* Needed by apm.c */
118 void save_processor_state(void)
120 __save_processor_state(&saved_context);
121 x86_platform.save_sched_clock_state();
124 EXPORT_SYMBOL(save_processor_state);
127 static void do_fpu_end(void)
130 * Restore FPU regs if necessary.
135 static void fix_processor_context(void)
137 int cpu = smp_processor_id();
138 struct tss_struct *t = &per_cpu(cpu_tss, cpu);
140 struct desc_struct *desc = get_cpu_gdt_table(cpu);
143 set_tss_desc(cpu, t); /*
144 * This just modifies memory; should not be
145 * necessary. But... This is necessary, because
146 * 386 hardware has concept of busy TSS or some
151 memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
152 tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
153 write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
155 syscall_init(); /* This sets MSR_*STAR and related */
157 load_TR_desc(); /* This does ltr */
158 load_mm_ldt(current->active_mm); /* This does lldt */
162 * __restore_processor_state - restore the contents of CPU registers saved
163 * by __save_processor_state()
164 * @ctxt - structure to load the registers contents from
166 static void notrace __restore_processor_state(struct saved_context *ctxt)
168 if (ctxt->misc_enable_saved)
169 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
173 /* cr4 was introduced in the Pentium CPU */
176 __write_cr4(ctxt->cr4);
179 wrmsrl(MSR_EFER, ctxt->efer);
180 write_cr8(ctxt->cr8);
181 __write_cr4(ctxt->cr4);
183 write_cr3(ctxt->cr3);
184 write_cr2(ctxt->cr2);
185 write_cr0(ctxt->cr0);
188 * now restore the descriptor tables to their proper values
189 * ltr is done i fix_processor_context().
192 load_idt(&ctxt->idt);
195 load_idt((const struct desc_ptr *)&ctxt->idt_limit);
202 loadsegment(es, ctxt->es);
203 loadsegment(fs, ctxt->fs);
204 loadsegment(gs, ctxt->gs);
205 loadsegment(ss, ctxt->ss);
210 if (boot_cpu_has(X86_FEATURE_SEP))
214 asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
215 asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
216 asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
217 load_gs_index(ctxt->gs);
218 asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
220 wrmsrl(MSR_FS_BASE, ctxt->fs_base);
221 wrmsrl(MSR_GS_BASE, ctxt->gs_base);
222 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
226 * restore XCR0 for xsave capable cpu's.
229 xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
231 fix_processor_context();
234 x86_platform.restore_sched_clock_state();
236 perf_restore_debug_store();
239 /* Needed by apm.c */
240 void notrace restore_processor_state(void)
242 __restore_processor_state(&saved_context);
245 EXPORT_SYMBOL(restore_processor_state);
249 * When bsp_check() is called in hibernate and suspend, cpu hotplug
250 * is disabled already. So it's unnessary to handle race condition between
251 * cpumask query and cpu hotplug.
253 static int bsp_check(void)
255 if (cpumask_first(cpu_online_mask) != 0) {
256 pr_warn("CPU0 is offline.\n");
263 static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
269 case PM_SUSPEND_PREPARE:
270 case PM_HIBERNATION_PREPARE:
273 #ifdef CONFIG_DEBUG_HOTPLUG_CPU0
274 case PM_RESTORE_PREPARE:
276 * When system resumes from hibernation, online CPU0 because
277 * 1. it's required for resume and
278 * 2. the CPU was online before hibernation
281 _debug_hotplug_cpu(0, 1);
283 case PM_POST_RESTORE:
285 * When a resume really happens, this code won't be called.
287 * This code is called only when user space hibernation software
288 * prepares for snapshot device during boot time. So we just
289 * call _debug_hotplug_cpu() to restore to CPU0's state prior to
290 * preparing the snapshot device.
292 * This works for normal boot case in our CPU0 hotplug debug
293 * mode, i.e. CPU0 is offline and user mode hibernation
294 * software initializes during boot time.
296 * If CPU0 is online and user application accesses snapshot
297 * device after boot time, this will offline CPU0 and user may
298 * see different CPU0 state before and after accessing
299 * the snapshot device. But hopefully this is not a case when
300 * user debugging CPU0 hotplug. Even if users hit this case,
301 * they can easily online CPU0 back.
303 * To simplify this debug code, we only consider normal boot
304 * case. Otherwise we need to remember CPU0's state and restore
305 * to that state and resolve racy conditions etc.
307 _debug_hotplug_cpu(0, 0);
313 return notifier_from_errno(ret);
316 static int __init bsp_pm_check_init(void)
319 * Set this bsp_pm_callback as lower priority than
320 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
321 * earlier to disable cpu hotplug before bsp online check.
323 pm_notifier(bsp_pm_callback, -INT_MAX);
327 core_initcall(bsp_pm_check_init);