3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
48 #define mod_64(x, y) ((x) % (y))
56 #define APIC_BUS_CYCLE_NS 1
58 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
59 #define apic_debug(fmt, arg...)
61 #define APIC_LVT_NUM 6
62 /* 14 is the version for Xeon and Pentium 8.4.8*/
63 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64 #define LAPIC_MMIO_LENGTH (1 << 12)
65 /* followed define is not in apicdef.h */
66 #define APIC_SHORT_MASK 0xc0000
67 #define APIC_DEST_NOSHORT 0x0
68 #define APIC_DEST_MASK 0x800
69 #define MAX_APIC_VECTOR 256
70 #define APIC_VECTORS_PER_REG 32
72 #define APIC_BROADCAST 0xFF
73 #define X2APIC_BROADCAST 0xFFFFFFFFul
75 #define VEC_POS(v) ((v) & (32 - 1))
76 #define REG_POS(v) (((v) >> 5) << 4)
78 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
80 *((u32 *) (apic->regs + reg_off)) = val;
83 static inline int apic_test_vector(int vec, void *bitmap)
85 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
88 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
90 struct kvm_lapic *apic = vcpu->arch.apic;
92 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
93 apic_test_vector(vector, apic->regs + APIC_IRR);
96 static inline void apic_set_vector(int vec, void *bitmap)
98 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
101 static inline void apic_clear_vector(int vec, void *bitmap)
103 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
106 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
108 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
111 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
113 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
116 struct static_key_deferred apic_hw_disabled __read_mostly;
117 struct static_key_deferred apic_sw_disabled __read_mostly;
119 static inline int apic_enabled(struct kvm_lapic *apic)
121 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
131 static inline int kvm_apic_id(struct kvm_lapic *apic)
133 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
136 /* The logical map is definitely wrong if we have multiple
137 * modes at the same time. (Physical map is always right.)
139 static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map)
141 return !(map->mode & (map->mode - 1));
145 apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid)
149 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER != 4);
150 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT != 8);
151 BUILD_BUG_ON(KVM_APIC_MODE_X2APIC != 16);
152 lid_bits = map->mode;
154 *cid = dest_id >> lid_bits;
155 *lid = dest_id & ((1 << lid_bits) - 1);
158 static void recalculate_apic_map(struct kvm *kvm)
160 struct kvm_apic_map *new, *old = NULL;
161 struct kvm_vcpu *vcpu;
164 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
166 mutex_lock(&kvm->arch.apic_map_lock);
171 kvm_for_each_vcpu(i, vcpu, kvm) {
172 struct kvm_lapic *apic = vcpu->arch.apic;
176 if (!kvm_apic_present(vcpu))
179 aid = kvm_apic_id(apic);
180 ldr = kvm_apic_get_reg(apic, APIC_LDR);
182 if (aid < ARRAY_SIZE(new->phys_map))
183 new->phys_map[aid] = apic;
185 if (apic_x2apic_mode(apic)) {
186 new->mode |= KVM_APIC_MODE_X2APIC;
188 ldr = GET_APIC_LOGICAL_ID(ldr);
189 if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
190 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
192 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
195 if (!kvm_apic_logical_map_valid(new))
198 apic_logical_id(new, ldr, &cid, &lid);
200 if (lid && cid < ARRAY_SIZE(new->logical_map))
201 new->logical_map[cid][ffs(lid) - 1] = apic;
204 old = rcu_dereference_protected(kvm->arch.apic_map,
205 lockdep_is_held(&kvm->arch.apic_map_lock));
206 rcu_assign_pointer(kvm->arch.apic_map, new);
207 mutex_unlock(&kvm->arch.apic_map_lock);
212 kvm_vcpu_request_scan_ioapic(kvm);
215 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
217 bool enabled = val & APIC_SPIV_APIC_ENABLED;
219 apic_set_reg(apic, APIC_SPIV, val);
221 if (enabled != apic->sw_enabled) {
222 apic->sw_enabled = enabled;
224 static_key_slow_dec_deferred(&apic_sw_disabled);
225 recalculate_apic_map(apic->vcpu->kvm);
227 static_key_slow_inc(&apic_sw_disabled.key);
231 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
233 apic_set_reg(apic, APIC_ID, id << 24);
234 recalculate_apic_map(apic->vcpu->kvm);
237 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
239 apic_set_reg(apic, APIC_LDR, id);
240 recalculate_apic_map(apic->vcpu->kvm);
243 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
245 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
248 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
250 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
253 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
255 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
258 static inline int apic_lvtt_period(struct kvm_lapic *apic)
260 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
263 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
265 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
268 static inline int apic_lvt_nmi_mode(u32 lvt_val)
270 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
273 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
275 struct kvm_lapic *apic = vcpu->arch.apic;
276 struct kvm_cpuid_entry2 *feat;
277 u32 v = APIC_VERSION;
279 if (!kvm_vcpu_has_lapic(vcpu))
282 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
283 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
284 v |= APIC_LVR_DIRECTED_EOI;
285 apic_set_reg(apic, APIC_LVR, v);
288 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
289 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
290 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
291 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
292 LINT_MASK, LINT_MASK, /* LVT0-1 */
293 LVT_MASK /* LVTERR */
296 static int find_highest_vector(void *bitmap)
301 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
302 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
303 reg = bitmap + REG_POS(vec);
305 return fls(*reg) - 1 + vec;
311 static u8 count_vectors(void *bitmap)
317 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
318 reg = bitmap + REG_POS(vec);
319 count += hweight32(*reg);
325 void __kvm_apic_update_irr(u32 *pir, void *regs)
329 for (i = 0; i <= 7; i++) {
330 pir_val = xchg(&pir[i], 0);
332 *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
335 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
337 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
339 struct kvm_lapic *apic = vcpu->arch.apic;
341 __kvm_apic_update_irr(pir, apic->regs);
343 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
345 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
347 apic_set_vector(vec, apic->regs + APIC_IRR);
349 * irr_pending must be true if any interrupt is pending; set it after
350 * APIC_IRR to avoid race with apic_clear_irr
352 apic->irr_pending = true;
355 static inline int apic_search_irr(struct kvm_lapic *apic)
357 return find_highest_vector(apic->regs + APIC_IRR);
360 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
365 * Note that irr_pending is just a hint. It will be always
366 * true with virtual interrupt delivery enabled.
368 if (!apic->irr_pending)
371 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
372 result = apic_search_irr(apic);
373 ASSERT(result == -1 || result >= 16);
378 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
380 struct kvm_vcpu *vcpu;
384 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
385 /* try to update RVI */
386 apic_clear_vector(vec, apic->regs + APIC_IRR);
387 kvm_make_request(KVM_REQ_EVENT, vcpu);
389 apic->irr_pending = false;
390 apic_clear_vector(vec, apic->regs + APIC_IRR);
391 if (apic_search_irr(apic) != -1)
392 apic->irr_pending = true;
396 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
398 struct kvm_vcpu *vcpu;
400 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
406 * With APIC virtualization enabled, all caching is disabled
407 * because the processor can modify ISR under the hood. Instead
410 if (unlikely(kvm_x86_ops->hwapic_isr_update))
411 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
414 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
416 * ISR (in service register) bit is set when injecting an interrupt.
417 * The highest vector is injected. Thus the latest bit set matches
418 * the highest bit in ISR.
420 apic->highest_isr_cache = vec;
424 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
429 * Note that isr_count is always 1, and highest_isr_cache
430 * is always -1, with APIC virtualization enabled.
432 if (!apic->isr_count)
434 if (likely(apic->highest_isr_cache != -1))
435 return apic->highest_isr_cache;
437 result = find_highest_vector(apic->regs + APIC_ISR);
438 ASSERT(result == -1 || result >= 16);
443 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
445 struct kvm_vcpu *vcpu;
446 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
452 * We do get here for APIC virtualization enabled if the guest
453 * uses the Hyper-V APIC enlightenment. In this case we may need
454 * to trigger a new interrupt delivery by writing the SVI field;
455 * on the other hand isr_count and highest_isr_cache are unused
456 * and must be left alone.
458 if (unlikely(kvm_x86_ops->hwapic_isr_update))
459 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
460 apic_find_highest_isr(apic));
463 BUG_ON(apic->isr_count < 0);
464 apic->highest_isr_cache = -1;
468 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
472 /* This may race with setting of irr in __apic_accept_irq() and
473 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
474 * will cause vmexit immediately and the value will be recalculated
475 * on the next vmentry.
477 if (!kvm_vcpu_has_lapic(vcpu))
479 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
484 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
485 int vector, int level, int trig_mode,
486 unsigned long *dest_map);
488 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
489 unsigned long *dest_map)
491 struct kvm_lapic *apic = vcpu->arch.apic;
493 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
494 irq->level, irq->trig_mode, dest_map);
497 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
500 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
504 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
507 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
511 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
513 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
516 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
519 if (pv_eoi_get_user(vcpu, &val) < 0)
520 apic_debug("Can't read EOI MSR value: 0x%llx\n",
521 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
525 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
527 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
528 apic_debug("Can't set EOI MSR value: 0x%llx\n",
529 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
532 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
535 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
537 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
538 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
539 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
542 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
545 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
547 struct kvm_lapic *apic = vcpu->arch.apic;
550 for (i = 0; i < 8; i++)
551 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
554 static void apic_update_ppr(struct kvm_lapic *apic)
556 u32 tpr, isrv, ppr, old_ppr;
559 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
560 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
561 isr = apic_find_highest_isr(apic);
562 isrv = (isr != -1) ? isr : 0;
564 if ((tpr & 0xf0) >= (isrv & 0xf0))
569 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
570 apic, ppr, isr, isrv);
572 if (old_ppr != ppr) {
573 apic_set_reg(apic, APIC_PROCPRI, ppr);
575 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
579 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
581 apic_set_reg(apic, APIC_TASKPRI, tpr);
582 apic_update_ppr(apic);
585 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
587 if (apic_x2apic_mode(apic))
588 return mda == X2APIC_BROADCAST;
590 return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
593 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
595 if (kvm_apic_broadcast(apic, mda))
598 if (apic_x2apic_mode(apic))
599 return mda == kvm_apic_id(apic);
601 return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
604 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
608 if (kvm_apic_broadcast(apic, mda))
611 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
613 if (apic_x2apic_mode(apic))
614 return ((logical_id >> 16) == (mda >> 16))
615 && (logical_id & mda & 0xffff) != 0;
617 logical_id = GET_APIC_LOGICAL_ID(logical_id);
618 mda = GET_APIC_DEST_FIELD(mda);
620 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
622 return (logical_id & mda) != 0;
623 case APIC_DFR_CLUSTER:
624 return ((logical_id >> 4) == (mda >> 4))
625 && (logical_id & mda & 0xf) != 0;
627 apic_debug("Bad DFR vcpu %d: %08x\n",
628 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
633 /* KVM APIC implementation has two quirks
634 * - dest always begins at 0 while xAPIC MDA has offset 24,
635 * - IOxAPIC messages have to be delivered (directly) to x2APIC.
637 static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
638 struct kvm_lapic *target)
640 bool ipi = source != NULL;
641 bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
643 if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
644 return X2APIC_BROADCAST;
646 return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
649 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
650 int short_hand, unsigned int dest, int dest_mode)
652 struct kvm_lapic *target = vcpu->arch.apic;
653 u32 mda = kvm_apic_mda(dest, source, target);
655 apic_debug("target %p, source %p, dest 0x%x, "
656 "dest_mode 0x%x, short_hand 0x%x\n",
657 target, source, dest, dest_mode, short_hand);
660 switch (short_hand) {
661 case APIC_DEST_NOSHORT:
662 if (dest_mode == APIC_DEST_PHYSICAL)
663 return kvm_apic_match_physical_addr(target, mda);
665 return kvm_apic_match_logical_addr(target, mda);
667 return target == source;
668 case APIC_DEST_ALLINC:
670 case APIC_DEST_ALLBUT:
671 return target != source;
673 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
679 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
680 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
682 struct kvm_apic_map *map;
683 unsigned long bitmap = 1;
684 struct kvm_lapic **dst;
686 bool ret, x2apic_ipi;
690 if (irq->shorthand == APIC_DEST_SELF) {
691 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
698 x2apic_ipi = src && apic_x2apic_mode(src);
699 if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
704 map = rcu_dereference(kvm->arch.apic_map);
711 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
712 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
715 dst = &map->phys_map[irq->dest_id];
719 if (!kvm_apic_logical_map_valid(map)) {
724 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
726 if (cid >= ARRAY_SIZE(map->logical_map))
729 dst = map->logical_map[cid];
731 if (irq->delivery_mode == APIC_DM_LOWEST) {
733 for_each_set_bit(i, &bitmap, 16) {
738 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
742 bitmap = (l >= 0) ? 1 << l : 0;
746 for_each_set_bit(i, &bitmap, 16) {
751 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
759 * Add a pending IRQ into lapic.
760 * Return 1 if successfully added and 0 if discarded.
762 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
763 int vector, int level, int trig_mode,
764 unsigned long *dest_map)
767 struct kvm_vcpu *vcpu = apic->vcpu;
769 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
771 switch (delivery_mode) {
773 vcpu->arch.apic_arb_prio++;
775 /* FIXME add logic for vcpu on reset */
776 if (unlikely(!apic_enabled(apic)))
782 __set_bit(vcpu->vcpu_id, dest_map);
784 if (kvm_x86_ops->deliver_posted_interrupt)
785 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
787 apic_set_irr(vector, apic);
789 kvm_make_request(KVM_REQ_EVENT, vcpu);
796 vcpu->arch.pv.pv_unhalted = 1;
797 kvm_make_request(KVM_REQ_EVENT, vcpu);
802 apic_debug("Ignoring guest SMI\n");
807 kvm_inject_nmi(vcpu);
812 if (!trig_mode || level) {
814 /* assumes that there are only KVM_APIC_INIT/SIPI */
815 apic->pending_events = (1UL << KVM_APIC_INIT);
816 /* make sure pending_events is visible before sending
819 kvm_make_request(KVM_REQ_EVENT, vcpu);
822 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
827 case APIC_DM_STARTUP:
828 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
829 vcpu->vcpu_id, vector);
831 apic->sipi_vector = vector;
832 /* make sure sipi_vector is visible for the receiver */
834 set_bit(KVM_APIC_SIPI, &apic->pending_events);
835 kvm_make_request(KVM_REQ_EVENT, vcpu);
841 * Should only be called by kvm_apic_local_deliver() with LVT0,
842 * before NMI watchdog was enabled. Already handled by
843 * kvm_apic_accept_pic_intr().
848 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
855 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
857 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
860 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
862 if (kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
864 if (apic_test_vector(vector, apic->regs + APIC_TMR))
865 trigger_mode = IOAPIC_LEVEL_TRIG;
867 trigger_mode = IOAPIC_EDGE_TRIG;
868 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
872 static int apic_set_eoi(struct kvm_lapic *apic)
874 int vector = apic_find_highest_isr(apic);
876 trace_kvm_eoi(apic, vector);
879 * Not every write EOI will has corresponding ISR,
880 * one example is when Kernel check timer on setup_IO_APIC
885 apic_clear_isr(vector, apic);
886 apic_update_ppr(apic);
888 kvm_ioapic_send_eoi(apic, vector);
889 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
894 * this interface assumes a trap-like exit, which has already finished
895 * desired side effect including vISR and vPPR update.
897 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
899 struct kvm_lapic *apic = vcpu->arch.apic;
901 trace_kvm_eoi(apic, vector);
903 kvm_ioapic_send_eoi(apic, vector);
904 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
906 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
908 static void apic_send_ipi(struct kvm_lapic *apic)
910 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
911 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
912 struct kvm_lapic_irq irq;
914 irq.vector = icr_low & APIC_VECTOR_MASK;
915 irq.delivery_mode = icr_low & APIC_MODE_MASK;
916 irq.dest_mode = icr_low & APIC_DEST_MASK;
917 irq.level = icr_low & APIC_INT_ASSERT;
918 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
919 irq.shorthand = icr_low & APIC_SHORT_MASK;
920 if (apic_x2apic_mode(apic))
921 irq.dest_id = icr_high;
923 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
925 trace_kvm_apic_ipi(icr_low, irq.dest_id);
927 apic_debug("icr_high 0x%x, icr_low 0x%x, "
928 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
929 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
930 icr_high, icr_low, irq.shorthand, irq.dest_id,
931 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
934 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
937 static u32 apic_get_tmcct(struct kvm_lapic *apic)
943 ASSERT(apic != NULL);
945 /* if initial count is 0, current count should also be 0 */
946 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
947 apic->lapic_timer.period == 0)
950 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
951 if (ktime_to_ns(remaining) < 0)
952 remaining = ktime_set(0, 0);
954 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
955 tmcct = div64_u64(ns,
956 (APIC_BUS_CYCLE_NS * apic->divide_count));
961 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
963 struct kvm_vcpu *vcpu = apic->vcpu;
964 struct kvm_run *run = vcpu->run;
966 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
967 run->tpr_access.rip = kvm_rip_read(vcpu);
968 run->tpr_access.is_write = write;
971 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
973 if (apic->vcpu->arch.tpr_access_reporting)
974 __report_tpr_access(apic, write);
977 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
981 if (offset >= LAPIC_MMIO_LENGTH)
986 if (apic_x2apic_mode(apic))
987 val = kvm_apic_id(apic);
989 val = kvm_apic_id(apic) << 24;
992 apic_debug("Access APIC ARBPRI register which is for P6\n");
995 case APIC_TMCCT: /* Timer CCR */
996 if (apic_lvtt_tscdeadline(apic))
999 val = apic_get_tmcct(apic);
1002 apic_update_ppr(apic);
1003 val = kvm_apic_get_reg(apic, offset);
1006 report_tpr_access(apic, false);
1009 val = kvm_apic_get_reg(apic, offset);
1016 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1018 return container_of(dev, struct kvm_lapic, dev);
1021 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1024 unsigned char alignment = offset & 0xf;
1026 /* this bitmask has a bit cleared for each reserved register */
1027 static const u64 rmask = 0x43ff01ffffffe70cULL;
1029 if ((alignment + len) > 4) {
1030 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1035 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1036 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1041 result = __apic_read(apic, offset & ~0xf);
1043 trace_kvm_apic_read(offset, result);
1049 memcpy(data, (char *)&result + alignment, len);
1052 printk(KERN_ERR "Local APIC read with len = %x, "
1053 "should be 1,2, or 4 instead\n", len);
1059 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1061 return kvm_apic_hw_enabled(apic) &&
1062 addr >= apic->base_address &&
1063 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1066 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1067 gpa_t address, int len, void *data)
1069 struct kvm_lapic *apic = to_lapic(this);
1070 u32 offset = address - apic->base_address;
1072 if (!apic_mmio_in_range(apic, address))
1075 apic_reg_read(apic, offset, len, data);
1080 static void update_divide_count(struct kvm_lapic *apic)
1082 u32 tmp1, tmp2, tdcr;
1084 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1086 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1087 apic->divide_count = 0x1 << (tmp2 & 0x7);
1089 apic_debug("timer divide count is 0x%x\n",
1090 apic->divide_count);
1093 static void apic_update_lvtt(struct kvm_lapic *apic)
1095 u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) &
1096 apic->lapic_timer.timer_mode_mask;
1098 if (apic->lapic_timer.timer_mode != timer_mode) {
1099 apic->lapic_timer.timer_mode = timer_mode;
1100 hrtimer_cancel(&apic->lapic_timer.timer);
1104 static void apic_timer_expired(struct kvm_lapic *apic)
1106 struct kvm_vcpu *vcpu = apic->vcpu;
1107 struct swait_head *q = &vcpu->wq;
1108 struct kvm_timer *ktimer = &apic->lapic_timer;
1110 if (atomic_read(&apic->lapic_timer.pending))
1113 atomic_inc(&apic->lapic_timer.pending);
1114 kvm_set_pending_timer(vcpu);
1116 if (swaitqueue_active(q))
1117 swait_wake_interruptible(q);
1119 if (apic_lvtt_tscdeadline(apic))
1120 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1124 * On APICv, this test will cause a busy wait
1125 * during a higher-priority task.
1128 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1130 struct kvm_lapic *apic = vcpu->arch.apic;
1131 u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1133 if (kvm_apic_hw_enabled(apic)) {
1134 int vec = reg & APIC_VECTOR_MASK;
1135 void *bitmap = apic->regs + APIC_ISR;
1137 if (kvm_x86_ops->deliver_posted_interrupt)
1138 bitmap = apic->regs + APIC_IRR;
1140 if (apic_test_vector(vec, bitmap))
1146 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1148 struct kvm_lapic *apic = vcpu->arch.apic;
1149 u64 guest_tsc, tsc_deadline;
1151 if (!kvm_vcpu_has_lapic(vcpu))
1154 if (apic->lapic_timer.expired_tscdeadline == 0)
1157 if (!lapic_timer_int_injected(vcpu))
1160 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1161 apic->lapic_timer.expired_tscdeadline = 0;
1162 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1163 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1165 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1166 if (guest_tsc < tsc_deadline)
1167 __delay(tsc_deadline - guest_tsc);
1170 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data);
1172 static void __apic_timer_expired(struct hrtimer *data)
1175 enum hrtimer_restart r;
1176 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1178 r = apic_timer_fn(data);
1180 if (r == HRTIMER_RESTART) {
1182 ret = hrtimer_start_expires(data, HRTIMER_MODE_ABS);
1184 hrtimer_add_expires_ns(&ktimer->timer,
1187 } while (ret == -ETIME && i < 10);
1189 if (ret == -ETIME) {
1190 printk_once(KERN_ERR "%s: failed to reprogram timer\n",
1197 static void start_apic_timer(struct kvm_lapic *apic)
1202 atomic_set(&apic->lapic_timer.pending, 0);
1204 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1205 /* lapic timer in oneshot or periodic mode */
1206 now = apic->lapic_timer.timer.base->get_time();
1207 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1208 * APIC_BUS_CYCLE_NS * apic->divide_count;
1210 if (!apic->lapic_timer.period)
1213 * Do not allow the guest to program periodic timers with small
1214 * interval, since the hrtimers are not throttled by the host
1217 if (apic_lvtt_period(apic)) {
1218 s64 min_period = min_timer_period_us * 1000LL;
1220 if (apic->lapic_timer.period < min_period) {
1221 pr_info_ratelimited(
1222 "kvm: vcpu %i: requested %lld ns "
1223 "lapic timer period limited to %lld ns\n",
1224 apic->vcpu->vcpu_id,
1225 apic->lapic_timer.period, min_period);
1226 apic->lapic_timer.period = min_period;
1230 ret = hrtimer_start(&apic->lapic_timer.timer,
1231 ktime_add_ns(now, apic->lapic_timer.period),
1234 __apic_timer_expired(&apic->lapic_timer.timer);
1236 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1238 "timer initial count 0x%x, period %lldns, "
1239 "expire @ 0x%016" PRIx64 ".\n", __func__,
1240 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1241 kvm_apic_get_reg(apic, APIC_TMICT),
1242 apic->lapic_timer.period,
1243 ktime_to_ns(ktime_add_ns(now,
1244 apic->lapic_timer.period)));
1245 } else if (apic_lvtt_tscdeadline(apic)) {
1246 /* lapic timer in tsc deadline mode */
1247 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1250 struct kvm_vcpu *vcpu = apic->vcpu;
1251 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1252 unsigned long flags;
1254 if (unlikely(!tscdeadline || !this_tsc_khz))
1257 local_irq_save(flags);
1259 now = apic->lapic_timer.timer.base->get_time();
1260 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1261 if (likely(tscdeadline > guest_tsc)) {
1262 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1263 do_div(ns, this_tsc_khz);
1264 expire = ktime_add_ns(now, ns);
1265 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1266 ret = hrtimer_start(&apic->lapic_timer.timer,
1267 expire, HRTIMER_MODE_ABS);
1269 __apic_timer_expired(&apic->lapic_timer.timer);
1271 apic_timer_expired(apic);
1273 local_irq_restore(flags);
1277 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1279 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1281 if (apic_lvt_nmi_mode(lvt0_val)) {
1282 if (!nmi_wd_enabled) {
1283 apic_debug("Receive NMI setting on APIC_LVT0 "
1284 "for cpu %d\n", apic->vcpu->vcpu_id);
1285 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1287 } else if (nmi_wd_enabled)
1288 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1291 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1295 trace_kvm_apic_write(reg, val);
1298 case APIC_ID: /* Local APIC ID */
1299 if (!apic_x2apic_mode(apic))
1300 kvm_apic_set_id(apic, val >> 24);
1306 report_tpr_access(apic, true);
1307 apic_set_tpr(apic, val & 0xff);
1315 if (!apic_x2apic_mode(apic))
1316 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1322 if (!apic_x2apic_mode(apic)) {
1323 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1324 recalculate_apic_map(apic->vcpu->kvm);
1331 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1332 mask |= APIC_SPIV_DIRECTED_EOI;
1333 apic_set_spiv(apic, val & mask);
1334 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1338 for (i = 0; i < APIC_LVT_NUM; i++) {
1339 lvt_val = kvm_apic_get_reg(apic,
1340 APIC_LVTT + 0x10 * i);
1341 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1342 lvt_val | APIC_LVT_MASKED);
1344 apic_update_lvtt(apic);
1345 atomic_set(&apic->lapic_timer.pending, 0);
1351 /* No delay here, so we always clear the pending bit */
1352 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1353 apic_send_ipi(apic);
1357 if (!apic_x2apic_mode(apic))
1359 apic_set_reg(apic, APIC_ICR2, val);
1363 apic_manage_nmi_watchdog(apic, val);
1368 /* TODO: Check vector */
1369 if (!kvm_apic_sw_enabled(apic))
1370 val |= APIC_LVT_MASKED;
1372 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1373 apic_set_reg(apic, reg, val);
1378 if (!kvm_apic_sw_enabled(apic))
1379 val |= APIC_LVT_MASKED;
1380 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1381 apic_set_reg(apic, APIC_LVTT, val);
1382 apic_update_lvtt(apic);
1386 if (apic_lvtt_tscdeadline(apic))
1389 hrtimer_cancel(&apic->lapic_timer.timer);
1390 apic_set_reg(apic, APIC_TMICT, val);
1391 start_apic_timer(apic);
1396 apic_debug("KVM_WRITE:TDCR %x\n", val);
1397 apic_set_reg(apic, APIC_TDCR, val);
1398 update_divide_count(apic);
1402 if (apic_x2apic_mode(apic) && val != 0) {
1403 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1409 if (apic_x2apic_mode(apic)) {
1410 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1419 apic_debug("Local APIC Write to read-only register %x\n", reg);
1423 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1424 gpa_t address, int len, const void *data)
1426 struct kvm_lapic *apic = to_lapic(this);
1427 unsigned int offset = address - apic->base_address;
1430 if (!apic_mmio_in_range(apic, address))
1434 * APIC register must be aligned on 128-bits boundary.
1435 * 32/64/128 bits registers must be accessed thru 32 bits.
1438 if (len != 4 || (offset & 0xf)) {
1439 /* Don't shout loud, $infamous_os would cause only noise. */
1440 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1446 /* too common printing */
1447 if (offset != APIC_EOI)
1448 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1449 "0x%x\n", __func__, offset, len, val);
1451 apic_reg_write(apic, offset & 0xff0, val);
1456 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1458 if (kvm_vcpu_has_lapic(vcpu))
1459 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1461 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1463 /* emulate APIC access in a trap manner */
1464 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1468 /* hw has done the conditional check and inst decode */
1471 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1473 /* TODO: optimize to just emulate side effect w/o one more write */
1474 apic_reg_write(vcpu->arch.apic, offset, val);
1476 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1478 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1480 struct kvm_lapic *apic = vcpu->arch.apic;
1482 if (!vcpu->arch.apic)
1485 hrtimer_cancel(&apic->lapic_timer.timer);
1487 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1488 static_key_slow_dec_deferred(&apic_hw_disabled);
1490 if (!apic->sw_enabled)
1491 static_key_slow_dec_deferred(&apic_sw_disabled);
1494 free_page((unsigned long)apic->regs);
1500 *----------------------------------------------------------------------
1502 *----------------------------------------------------------------------
1505 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1507 struct kvm_lapic *apic = vcpu->arch.apic;
1509 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1510 apic_lvtt_period(apic))
1513 return apic->lapic_timer.tscdeadline;
1516 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1518 struct kvm_lapic *apic = vcpu->arch.apic;
1520 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1521 apic_lvtt_period(apic))
1524 hrtimer_cancel(&apic->lapic_timer.timer);
1525 apic->lapic_timer.tscdeadline = data;
1526 start_apic_timer(apic);
1529 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1531 struct kvm_lapic *apic = vcpu->arch.apic;
1533 if (!kvm_vcpu_has_lapic(vcpu))
1536 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1537 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1540 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1544 if (!kvm_vcpu_has_lapic(vcpu))
1547 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1549 return (tpr & 0xf0) >> 4;
1552 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1554 u64 old_value = vcpu->arch.apic_base;
1555 struct kvm_lapic *apic = vcpu->arch.apic;
1558 value |= MSR_IA32_APICBASE_BSP;
1559 vcpu->arch.apic_base = value;
1563 vcpu->arch.apic_base = value;
1565 /* update jump label if enable bit changes */
1566 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1567 if (value & MSR_IA32_APICBASE_ENABLE)
1568 static_key_slow_dec_deferred(&apic_hw_disabled);
1570 static_key_slow_inc(&apic_hw_disabled.key);
1571 recalculate_apic_map(vcpu->kvm);
1574 if ((old_value ^ value) & X2APIC_ENABLE) {
1575 if (value & X2APIC_ENABLE) {
1576 u32 id = kvm_apic_id(apic);
1577 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1578 kvm_apic_set_ldr(apic, ldr);
1579 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1581 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1584 apic->base_address = apic->vcpu->arch.apic_base &
1585 MSR_IA32_APICBASE_BASE;
1587 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1588 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1589 pr_warn_once("APIC base relocation is unsupported by KVM");
1591 /* with FSB delivery interrupt, we can restart APIC functionality */
1592 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1593 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1597 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1599 struct kvm_lapic *apic;
1602 apic_debug("%s\n", __func__);
1605 apic = vcpu->arch.apic;
1606 ASSERT(apic != NULL);
1608 /* Stop the timer in case it's a reset to an active apic */
1609 hrtimer_cancel(&apic->lapic_timer.timer);
1611 kvm_apic_set_id(apic, vcpu->vcpu_id);
1612 kvm_apic_set_version(apic->vcpu);
1614 for (i = 0; i < APIC_LVT_NUM; i++)
1615 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1616 apic_update_lvtt(apic);
1617 apic_set_reg(apic, APIC_LVT0,
1618 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1620 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1621 apic_set_spiv(apic, 0xff);
1622 apic_set_reg(apic, APIC_TASKPRI, 0);
1623 kvm_apic_set_ldr(apic, 0);
1624 apic_set_reg(apic, APIC_ESR, 0);
1625 apic_set_reg(apic, APIC_ICR, 0);
1626 apic_set_reg(apic, APIC_ICR2, 0);
1627 apic_set_reg(apic, APIC_TDCR, 0);
1628 apic_set_reg(apic, APIC_TMICT, 0);
1629 for (i = 0; i < 8; i++) {
1630 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1631 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1632 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1634 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1635 apic->isr_count = kvm_x86_ops->hwapic_isr_update ? 1 : 0;
1636 apic->highest_isr_cache = -1;
1637 update_divide_count(apic);
1638 atomic_set(&apic->lapic_timer.pending, 0);
1639 if (kvm_vcpu_is_bsp(vcpu))
1640 kvm_lapic_set_base(vcpu,
1641 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1642 vcpu->arch.pv_eoi.msr_val = 0;
1643 apic_update_ppr(apic);
1645 vcpu->arch.apic_arb_prio = 0;
1646 vcpu->arch.apic_attention = 0;
1648 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1649 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1650 vcpu, kvm_apic_id(apic),
1651 vcpu->arch.apic_base, apic->base_address);
1655 *----------------------------------------------------------------------
1657 *----------------------------------------------------------------------
1660 static bool lapic_is_periodic(struct kvm_lapic *apic)
1662 return apic_lvtt_period(apic);
1665 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1667 struct kvm_lapic *apic = vcpu->arch.apic;
1669 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1670 apic_lvt_enabled(apic, APIC_LVTT))
1671 return atomic_read(&apic->lapic_timer.pending);
1676 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1678 u32 reg = kvm_apic_get_reg(apic, lvt_type);
1679 int vector, mode, trig_mode;
1681 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1682 vector = reg & APIC_VECTOR_MASK;
1683 mode = reg & APIC_MODE_MASK;
1684 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1685 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1691 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1693 struct kvm_lapic *apic = vcpu->arch.apic;
1696 kvm_apic_local_deliver(apic, APIC_LVT0);
1699 static const struct kvm_io_device_ops apic_mmio_ops = {
1700 .read = apic_mmio_read,
1701 .write = apic_mmio_write,
1704 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1706 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1707 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1709 apic_timer_expired(apic);
1711 if (lapic_is_periodic(apic)) {
1712 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1713 return HRTIMER_RESTART;
1715 return HRTIMER_NORESTART;
1718 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1720 struct kvm_lapic *apic;
1722 ASSERT(vcpu != NULL);
1723 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1725 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1729 vcpu->arch.apic = apic;
1731 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1733 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1735 goto nomem_free_apic;
1739 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1741 apic->lapic_timer.timer.function = apic_timer_fn;
1742 apic->lapic_timer.timer.irqsafe = 1;
1745 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1746 * thinking that APIC satet has changed.
1748 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1749 kvm_lapic_set_base(vcpu,
1750 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1752 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1753 kvm_lapic_reset(vcpu);
1754 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1763 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1765 struct kvm_lapic *apic = vcpu->arch.apic;
1768 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1771 apic_update_ppr(apic);
1772 highest_irr = apic_find_highest_irr(apic);
1773 if ((highest_irr == -1) ||
1774 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1779 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1781 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1784 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1786 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1787 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1792 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1794 struct kvm_lapic *apic = vcpu->arch.apic;
1796 if (!kvm_vcpu_has_lapic(vcpu))
1799 if (atomic_read(&apic->lapic_timer.pending) > 0) {
1800 kvm_apic_local_deliver(apic, APIC_LVTT);
1801 if (apic_lvtt_tscdeadline(apic))
1802 apic->lapic_timer.tscdeadline = 0;
1803 atomic_set(&apic->lapic_timer.pending, 0);
1807 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1809 int vector = kvm_apic_has_interrupt(vcpu);
1810 struct kvm_lapic *apic = vcpu->arch.apic;
1816 * We get here even with APIC virtualization enabled, if doing
1817 * nested virtualization and L1 runs with the "acknowledge interrupt
1818 * on exit" mode. Then we cannot inject the interrupt via RVI,
1819 * because the process would deliver it through the IDT.
1822 apic_set_isr(vector, apic);
1823 apic_update_ppr(apic);
1824 apic_clear_irr(vector, apic);
1828 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1829 struct kvm_lapic_state *s)
1831 struct kvm_lapic *apic = vcpu->arch.apic;
1833 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1834 /* set SPIV separately to get count of SW disabled APICs right */
1835 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1836 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1837 /* call kvm_apic_set_id() to put apic into apic_map */
1838 kvm_apic_set_id(apic, kvm_apic_id(apic));
1839 kvm_apic_set_version(vcpu);
1841 apic_update_ppr(apic);
1842 hrtimer_cancel(&apic->lapic_timer.timer);
1843 apic_update_lvtt(apic);
1844 apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
1845 update_divide_count(apic);
1846 start_apic_timer(apic);
1847 apic->irr_pending = true;
1848 apic->isr_count = kvm_x86_ops->hwapic_isr_update ?
1849 1 : count_vectors(apic->regs + APIC_ISR);
1850 apic->highest_isr_cache = -1;
1851 if (kvm_x86_ops->hwapic_irr_update)
1852 kvm_x86_ops->hwapic_irr_update(vcpu,
1853 apic_find_highest_irr(apic));
1854 if (unlikely(kvm_x86_ops->hwapic_isr_update))
1855 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1856 apic_find_highest_isr(apic));
1857 kvm_make_request(KVM_REQ_EVENT, vcpu);
1858 kvm_rtc_eoi_tracking_restore_one(vcpu);
1861 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1863 struct hrtimer *timer;
1865 if (!kvm_vcpu_has_lapic(vcpu))
1868 timer = &vcpu->arch.apic->lapic_timer.timer;
1869 if (hrtimer_cancel(timer))
1870 if (hrtimer_start_expires(timer, HRTIMER_MODE_ABS) == -ETIME)
1871 __apic_timer_expired(timer);
1875 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1877 * Detect whether guest triggered PV EOI since the
1878 * last entry. If yes, set EOI on guests's behalf.
1879 * Clear PV EOI in guest memory in any case.
1881 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1882 struct kvm_lapic *apic)
1887 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1888 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1890 * KVM_APIC_PV_EOI_PENDING is unset:
1891 * -> host disabled PV EOI.
1892 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1893 * -> host enabled PV EOI, guest did not execute EOI yet.
1894 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1895 * -> host enabled PV EOI, guest executed EOI.
1897 BUG_ON(!pv_eoi_enabled(vcpu));
1898 pending = pv_eoi_get_pending(vcpu);
1900 * Clear pending bit in any case: it will be set again on vmentry.
1901 * While this might not be ideal from performance point of view,
1902 * this makes sure pv eoi is only enabled when we know it's safe.
1904 pv_eoi_clr_pending(vcpu);
1907 vector = apic_set_eoi(apic);
1908 trace_kvm_pv_eoi(apic, vector);
1911 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1915 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1916 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1918 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1921 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1924 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1928 * apic_sync_pv_eoi_to_guest - called before vmentry
1930 * Detect whether it's safe to enable PV EOI and
1933 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1934 struct kvm_lapic *apic)
1936 if (!pv_eoi_enabled(vcpu) ||
1937 /* IRR set or many bits in ISR: could be nested. */
1938 apic->irr_pending ||
1939 /* Cache not set: could be safe but we don't bother. */
1940 apic->highest_isr_cache == -1 ||
1941 /* Need EOI to update ioapic. */
1942 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1944 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1945 * so we need not do anything here.
1950 pv_eoi_set_pending(apic->vcpu);
1953 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1956 int max_irr, max_isr;
1957 struct kvm_lapic *apic = vcpu->arch.apic;
1959 apic_sync_pv_eoi_to_guest(vcpu, apic);
1961 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1964 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1965 max_irr = apic_find_highest_irr(apic);
1968 max_isr = apic_find_highest_isr(apic);
1971 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1973 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1977 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1980 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1981 &vcpu->arch.apic->vapic_cache,
1982 vapic_addr, sizeof(u32)))
1984 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1986 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1989 vcpu->arch.apic->vapic_addr = vapic_addr;
1993 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1995 struct kvm_lapic *apic = vcpu->arch.apic;
1996 u32 reg = (msr - APIC_BASE_MSR) << 4;
1998 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
2001 if (reg == APIC_ICR2)
2004 /* if this is ICR write vector before command */
2005 if (reg == APIC_ICR)
2006 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2007 return apic_reg_write(apic, reg, (u32)data);
2010 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2012 struct kvm_lapic *apic = vcpu->arch.apic;
2013 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2015 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
2018 if (reg == APIC_DFR || reg == APIC_ICR2) {
2019 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2024 if (apic_reg_read(apic, reg, 4, &low))
2026 if (reg == APIC_ICR)
2027 apic_reg_read(apic, APIC_ICR2, 4, &high);
2029 *data = (((u64)high) << 32) | low;
2034 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2036 struct kvm_lapic *apic = vcpu->arch.apic;
2038 if (!kvm_vcpu_has_lapic(vcpu))
2041 /* if this is ICR write vector before command */
2042 if (reg == APIC_ICR)
2043 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2044 return apic_reg_write(apic, reg, (u32)data);
2047 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2049 struct kvm_lapic *apic = vcpu->arch.apic;
2052 if (!kvm_vcpu_has_lapic(vcpu))
2055 if (apic_reg_read(apic, reg, 4, &low))
2057 if (reg == APIC_ICR)
2058 apic_reg_read(apic, APIC_ICR2, 4, &high);
2060 *data = (((u64)high) << 32) | low;
2065 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2067 u64 addr = data & ~KVM_MSR_ENABLED;
2068 if (!IS_ALIGNED(addr, 4))
2071 vcpu->arch.pv_eoi.msr_val = data;
2072 if (!pv_eoi_enabled(vcpu))
2074 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2078 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2080 struct kvm_lapic *apic = vcpu->arch.apic;
2084 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
2087 pe = xchg(&apic->pending_events, 0);
2089 if (test_bit(KVM_APIC_INIT, &pe)) {
2090 kvm_lapic_reset(vcpu);
2091 kvm_vcpu_reset(vcpu);
2092 if (kvm_vcpu_is_bsp(apic->vcpu))
2093 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2095 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2097 if (test_bit(KVM_APIC_SIPI, &pe) &&
2098 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2099 /* evaluate pending_events before reading the vector */
2101 sipi_vector = apic->sipi_vector;
2102 apic_debug("vcpu %d received sipi with vector # %x\n",
2103 vcpu->vcpu_id, sipi_vector);
2104 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2105 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2109 void kvm_lapic_init(void)
2111 /* do not patch jump label more than once per second */
2112 jump_label_rate_limit(&apic_hw_disabled, HZ);
2113 jump_label_rate_limit(&apic_sw_disabled, HZ);