1 #include <linux/bitops.h>
2 #include <linux/types.h>
3 #include <linux/slab.h>
5 #include <asm/perf_event.h>
8 #include "perf_event.h"
10 /* The size of a BTS record in bytes: */
11 #define BTS_RECORD_SIZE 24
13 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
14 #define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
15 #define PEBS_FIXUP_SIZE PAGE_SIZE
18 * pebs_record_32 for p4 and core not supported
20 struct pebs_record_32 {
28 union intel_x86_pebs_dse {
31 unsigned int ld_dse:4;
32 unsigned int ld_stlb_miss:1;
33 unsigned int ld_locked:1;
34 unsigned int ld_reserved:26;
37 unsigned int st_l1d_hit:1;
38 unsigned int st_reserved1:3;
39 unsigned int st_stlb_miss:1;
40 unsigned int st_locked:1;
41 unsigned int st_reserved2:26;
47 * Map PEBS Load Latency Data Source encodings to generic
48 * memory data source information
50 #define P(a, b) PERF_MEM_S(a, b)
51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
54 /* Version for Sandy Bridge and later */
55 static u64 pebs_data_source[] = {
56 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
57 OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */
58 OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
59 OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
60 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
61 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
62 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
63 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
64 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
65 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
66 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
67 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
68 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
69 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
70 OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */
71 OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
74 /* Patch up minor differences in the bits */
75 void __init intel_pmu_pebs_data_source_nhm(void)
77 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | P(SNOOP, HIT);
78 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | P(SNOOP, HITM);
79 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | P(SNOOP, HITM);
82 static u64 precise_store_data(u64 status)
84 union intel_x86_pebs_dse dse;
85 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
91 * 1 = stored missed 2nd level TLB
93 * so it either hit the walker or the OS
94 * otherwise hit 2nd level TLB
102 * bit 0: hit L1 data cache
103 * if not set, then all we know is that
112 * bit 5: Locked prefix
115 val |= P(LOCK, LOCKED);
120 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
122 union perf_mem_data_src dse;
124 dse.val = PERF_MEM_NA;
126 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
127 dse.mem_op = PERF_MEM_OP_STORE;
128 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
129 dse.mem_op = PERF_MEM_OP_LOAD;
132 * L1 info only valid for following events:
134 * MEM_UOPS_RETIRED.STLB_MISS_STORES
135 * MEM_UOPS_RETIRED.LOCK_STORES
136 * MEM_UOPS_RETIRED.SPLIT_STORES
137 * MEM_UOPS_RETIRED.ALL_STORES
139 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
141 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
143 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
148 static u64 load_latency_data(u64 status)
150 union intel_x86_pebs_dse dse;
152 int model = boot_cpu_data.x86_model;
153 int fam = boot_cpu_data.x86;
158 * use the mapping table for bit 0-3
160 val = pebs_data_source[dse.ld_dse];
163 * Nehalem models do not support TLB, Lock infos
165 if (fam == 0x6 && (model == 26 || model == 30
166 || model == 31 || model == 46)) {
167 val |= P(TLB, NA) | P(LOCK, NA);
172 * 0 = did not miss 2nd level TLB
173 * 1 = missed 2nd level TLB
175 if (dse.ld_stlb_miss)
176 val |= P(TLB, MISS) | P(TLB, L2);
178 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
181 * bit 5: locked prefix
184 val |= P(LOCK, LOCKED);
189 struct pebs_record_core {
193 u64 r8, r9, r10, r11;
194 u64 r12, r13, r14, r15;
197 struct pebs_record_nhm {
201 u64 r8, r9, r10, r11;
202 u64 r12, r13, r14, r15;
203 u64 status, dla, dse, lat;
207 * Same as pebs_record_nhm, with two additional fields.
209 struct pebs_record_hsw {
213 u64 r8, r9, r10, r11;
214 u64 r12, r13, r14, r15;
215 u64 status, dla, dse, lat;
216 u64 real_ip, tsx_tuning;
219 union hsw_tsx_tuning {
221 u32 cycles_last_block : 32,
224 instruction_abort : 1,
225 non_instruction_abort : 1,
234 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
236 /* Same as HSW, plus TSC */
238 struct pebs_record_skl {
242 u64 r8, r9, r10, r11;
243 u64 r12, r13, r14, r15;
244 u64 status, dla, dse, lat;
245 u64 real_ip, tsx_tuning;
249 void init_debug_store_on_cpu(int cpu)
251 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
256 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
257 (u32)((u64)(unsigned long)ds),
258 (u32)((u64)(unsigned long)ds >> 32));
261 void fini_debug_store_on_cpu(int cpu)
263 if (!per_cpu(cpu_hw_events, cpu).ds)
266 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
269 static DEFINE_PER_CPU(void *, insn_buffer);
271 static int alloc_pebs_buffer(int cpu)
273 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
274 int node = cpu_to_node(cpu);
276 void *buffer, *ibuffer;
281 buffer = kzalloc_node(x86_pmu.pebs_buffer_size, GFP_KERNEL, node);
282 if (unlikely(!buffer))
286 * HSW+ already provides us the eventing ip; no need to allocate this
289 if (x86_pmu.intel_cap.pebs_format < 2) {
290 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
295 per_cpu(insn_buffer, cpu) = ibuffer;
298 max = x86_pmu.pebs_buffer_size / x86_pmu.pebs_record_size;
300 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
301 ds->pebs_index = ds->pebs_buffer_base;
302 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
303 max * x86_pmu.pebs_record_size;
308 static void release_pebs_buffer(int cpu)
310 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
312 if (!ds || !x86_pmu.pebs)
315 kfree(per_cpu(insn_buffer, cpu));
316 per_cpu(insn_buffer, cpu) = NULL;
318 kfree((void *)(unsigned long)ds->pebs_buffer_base);
319 ds->pebs_buffer_base = 0;
322 static int alloc_bts_buffer(int cpu)
324 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
325 int node = cpu_to_node(cpu);
332 buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
333 if (unlikely(!buffer)) {
334 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
338 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
341 ds->bts_buffer_base = (u64)(unsigned long)buffer;
342 ds->bts_index = ds->bts_buffer_base;
343 ds->bts_absolute_maximum = ds->bts_buffer_base +
344 max * BTS_RECORD_SIZE;
345 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
346 thresh * BTS_RECORD_SIZE;
351 static void release_bts_buffer(int cpu)
353 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
355 if (!ds || !x86_pmu.bts)
358 kfree((void *)(unsigned long)ds->bts_buffer_base);
359 ds->bts_buffer_base = 0;
362 static int alloc_ds_buffer(int cpu)
364 int node = cpu_to_node(cpu);
365 struct debug_store *ds;
367 ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
371 per_cpu(cpu_hw_events, cpu).ds = ds;
376 static void release_ds_buffer(int cpu)
378 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
383 per_cpu(cpu_hw_events, cpu).ds = NULL;
387 void release_ds_buffers(void)
391 if (!x86_pmu.bts && !x86_pmu.pebs)
395 for_each_online_cpu(cpu)
396 fini_debug_store_on_cpu(cpu);
398 for_each_possible_cpu(cpu) {
399 release_pebs_buffer(cpu);
400 release_bts_buffer(cpu);
401 release_ds_buffer(cpu);
406 void reserve_ds_buffers(void)
408 int bts_err = 0, pebs_err = 0;
411 x86_pmu.bts_active = 0;
412 x86_pmu.pebs_active = 0;
414 if (!x86_pmu.bts && !x86_pmu.pebs)
425 for_each_possible_cpu(cpu) {
426 if (alloc_ds_buffer(cpu)) {
431 if (!bts_err && alloc_bts_buffer(cpu))
434 if (!pebs_err && alloc_pebs_buffer(cpu))
437 if (bts_err && pebs_err)
442 for_each_possible_cpu(cpu)
443 release_bts_buffer(cpu);
447 for_each_possible_cpu(cpu)
448 release_pebs_buffer(cpu);
451 if (bts_err && pebs_err) {
452 for_each_possible_cpu(cpu)
453 release_ds_buffer(cpu);
455 if (x86_pmu.bts && !bts_err)
456 x86_pmu.bts_active = 1;
458 if (x86_pmu.pebs && !pebs_err)
459 x86_pmu.pebs_active = 1;
461 for_each_online_cpu(cpu)
462 init_debug_store_on_cpu(cpu);
472 struct event_constraint bts_constraint =
473 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
475 void intel_pmu_enable_bts(u64 config)
477 unsigned long debugctlmsr;
479 debugctlmsr = get_debugctlmsr();
481 debugctlmsr |= DEBUGCTLMSR_TR;
482 debugctlmsr |= DEBUGCTLMSR_BTS;
483 if (config & ARCH_PERFMON_EVENTSEL_INT)
484 debugctlmsr |= DEBUGCTLMSR_BTINT;
486 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
487 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
489 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
490 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
492 update_debugctlmsr(debugctlmsr);
495 void intel_pmu_disable_bts(void)
497 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
498 unsigned long debugctlmsr;
503 debugctlmsr = get_debugctlmsr();
506 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
507 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
509 update_debugctlmsr(debugctlmsr);
512 int intel_pmu_drain_bts_buffer(void)
514 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
515 struct debug_store *ds = cpuc->ds;
521 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
522 struct bts_record *at, *base, *top;
523 struct perf_output_handle handle;
524 struct perf_event_header header;
525 struct perf_sample_data data;
526 unsigned long skip = 0;
532 if (!x86_pmu.bts_active)
535 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
536 top = (struct bts_record *)(unsigned long)ds->bts_index;
541 memset(®s, 0, sizeof(regs));
543 ds->bts_index = ds->bts_buffer_base;
545 perf_sample_data_init(&data, 0, event->hw.last_period);
548 * BTS leaks kernel addresses in branches across the cpl boundary,
549 * such as traps or system calls, so unless the user is asking for
550 * kernel tracing (and right now it's not possible), we'd need to
551 * filter them out. But first we need to count how many of those we
552 * have in the current batch. This is an extra O(n) pass, however,
553 * it's much faster than the other one especially considering that
554 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
555 * alloc_bts_buffer()).
557 for (at = base; at < top; at++) {
559 * Note that right now *this* BTS code only works if
560 * attr::exclude_kernel is set, but let's keep this extra
561 * check here in case that changes.
563 if (event->attr.exclude_kernel &&
564 (kernel_ip(at->from) || kernel_ip(at->to)))
569 * Prepare a generic sample, i.e. fill in the invariant fields.
570 * We will overwrite the from and to address before we output
573 perf_prepare_sample(&header, &data, event, ®s);
575 if (perf_output_begin(&handle, event, header.size *
576 (top - base - skip)))
579 for (at = base; at < top; at++) {
580 /* Filter out any records that contain kernel addresses. */
581 if (event->attr.exclude_kernel &&
582 (kernel_ip(at->from) || kernel_ip(at->to)))
588 perf_output_sample(&handle, &header, &data, event);
591 perf_output_end(&handle);
593 /* There's new data available. */
594 event->hw.interrupts++;
595 event->pending_kill = POLL_IN;
599 static inline void intel_pmu_drain_pebs_buffer(void)
603 x86_pmu.drain_pebs(®s);
606 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
609 intel_pmu_drain_pebs_buffer();
615 struct event_constraint intel_core2_pebs_event_constraints[] = {
616 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
617 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
618 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
619 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
620 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
621 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
622 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
626 struct event_constraint intel_atom_pebs_event_constraints[] = {
627 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
628 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
629 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
630 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
631 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
635 struct event_constraint intel_slm_pebs_event_constraints[] = {
636 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
637 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
638 /* Allow all events as PEBS with no flags */
639 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
643 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
644 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
645 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
646 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
647 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
648 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
649 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
650 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
651 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
652 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
653 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
654 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
655 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
656 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
660 struct event_constraint intel_westmere_pebs_event_constraints[] = {
661 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
662 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
663 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
664 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
665 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
666 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
667 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
668 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
669 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
670 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
671 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
672 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
673 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
677 struct event_constraint intel_snb_pebs_event_constraints[] = {
678 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
679 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
680 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
681 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
682 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
683 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
684 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
685 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
686 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
687 /* Allow all events as PEBS with no flags */
688 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
692 struct event_constraint intel_ivb_pebs_event_constraints[] = {
693 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
694 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
695 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
696 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
697 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
698 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
699 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
700 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
701 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
702 /* Allow all events as PEBS with no flags */
703 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
707 struct event_constraint intel_hsw_pebs_event_constraints[] = {
708 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
709 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
710 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
711 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
712 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
713 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
714 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
715 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
716 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
717 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
718 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
719 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
720 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
721 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
722 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
723 /* Allow all events as PEBS with no flags */
724 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
728 struct event_constraint intel_skl_pebs_event_constraints[] = {
729 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
730 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
731 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
732 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
733 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
734 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
735 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
736 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
737 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
738 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
739 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
740 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
741 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
742 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
743 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
744 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */
745 /* Allow all events as PEBS with no flags */
746 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
750 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
752 struct event_constraint *c;
754 if (!event->attr.precise_ip)
757 if (x86_pmu.pebs_constraints) {
758 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
759 if ((event->hw.config & c->cmask) == c->code) {
760 event->hw.flags |= c->flags;
766 return &emptyconstraint;
769 static inline bool pebs_is_enabled(struct cpu_hw_events *cpuc)
771 return (cpuc->pebs_enabled & ((1ULL << MAX_PEBS_EVENTS) - 1));
774 void intel_pmu_pebs_enable(struct perf_event *event)
776 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
777 struct hw_perf_event *hwc = &event->hw;
778 struct debug_store *ds = cpuc->ds;
782 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
784 first_pebs = !pebs_is_enabled(cpuc);
785 cpuc->pebs_enabled |= 1ULL << hwc->idx;
787 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
788 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
789 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
790 cpuc->pebs_enabled |= 1ULL << 63;
793 * When the event is constrained enough we can use a larger
794 * threshold and run the event with less frequent PMI.
796 if (hwc->flags & PERF_X86_EVENT_FREERUNNING) {
797 threshold = ds->pebs_absolute_maximum -
798 x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
801 perf_sched_cb_inc(event->ctx->pmu);
803 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
806 * If not all events can use larger buffer,
807 * roll back to threshold = 1
810 (ds->pebs_interrupt_threshold > threshold))
811 perf_sched_cb_dec(event->ctx->pmu);
814 /* Use auto-reload if possible to save a MSR write in the PMI */
815 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
816 ds->pebs_event_reset[hwc->idx] =
817 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
820 if (first_pebs || ds->pebs_interrupt_threshold > threshold)
821 ds->pebs_interrupt_threshold = threshold;
824 void intel_pmu_pebs_disable(struct perf_event *event)
826 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
827 struct hw_perf_event *hwc = &event->hw;
828 struct debug_store *ds = cpuc->ds;
829 bool large_pebs = ds->pebs_interrupt_threshold >
830 ds->pebs_buffer_base + x86_pmu.pebs_record_size;
833 intel_pmu_drain_pebs_buffer();
835 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
837 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
838 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
839 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
840 cpuc->pebs_enabled &= ~(1ULL << 63);
842 if (large_pebs && !pebs_is_enabled(cpuc))
843 perf_sched_cb_dec(event->ctx->pmu);
846 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
848 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
851 void intel_pmu_pebs_enable_all(void)
853 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
855 if (cpuc->pebs_enabled)
856 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
859 void intel_pmu_pebs_disable_all(void)
861 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
863 if (cpuc->pebs_enabled)
864 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
867 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
869 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
870 unsigned long from = cpuc->lbr_entries[0].from;
871 unsigned long old_to, to = cpuc->lbr_entries[0].to;
872 unsigned long ip = regs->ip;
878 * We don't need to fixup if the PEBS assist is fault like
880 if (!x86_pmu.intel_cap.pebs_trap)
884 * No LBR entry, no basic block, no rewinding
886 if (!cpuc->lbr_stack.nr || !from || !to)
890 * Basic blocks should never cross user/kernel boundaries
892 if (kernel_ip(ip) != kernel_ip(to))
896 * unsigned math, either ip is before the start (impossible) or
897 * the basic block is larger than 1 page (sanity)
899 if ((ip - to) > PEBS_FIXUP_SIZE)
903 * We sampled a branch insn, rewind using the LBR stack
906 set_linear_ip(regs, from);
911 if (!kernel_ip(ip)) {
913 u8 *buf = this_cpu_read(insn_buffer);
915 /* 'size' must fit our buffer, see above */
916 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
931 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
933 insn_init(&insn, kaddr, size, is_64bit);
934 insn_get_length(&insn);
936 * Make sure there was not a problem decoding the
937 * instruction and getting the length. This is
938 * doubly important because we have an infinite
939 * loop if insn.length=0.
945 kaddr += insn.length;
950 set_linear_ip(regs, old_to);
955 * Even though we decoded the basic block, the instruction stream
956 * never matched the given IP, either the TO or the IP got corrupted.
961 static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs)
963 if (pebs->tsx_tuning) {
964 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
965 return tsx.cycles_last_block;
970 static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs)
972 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
974 /* For RTM XABORTs also log the abort code from AX */
975 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
976 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
980 static void setup_pebs_sample_data(struct perf_event *event,
981 struct pt_regs *iregs, void *__pebs,
982 struct perf_sample_data *data,
983 struct pt_regs *regs)
985 #define PERF_X86_EVENT_PEBS_HSW_PREC \
986 (PERF_X86_EVENT_PEBS_ST_HSW | \
987 PERF_X86_EVENT_PEBS_LD_HSW | \
988 PERF_X86_EVENT_PEBS_NA_HSW)
990 * We cast to the biggest pebs_record but are careful not to
991 * unconditionally access the 'extra' entries.
993 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
994 struct pebs_record_skl *pebs = __pebs;
997 int fl = event->hw.flags;
1002 sample_type = event->attr.sample_type;
1003 dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
1005 fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
1006 fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1008 perf_sample_data_init(data, 0, event->hw.last_period);
1010 data->period = event->hw.last_period;
1013 * Use latency for weight (only avail with PEBS-LL)
1015 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
1016 data->weight = pebs->lat;
1019 * data.data_src encodes the data source
1022 u64 val = PERF_MEM_NA;
1024 val = load_latency_data(pebs->dse);
1025 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1026 val = precise_datala_hsw(event, pebs->dse);
1028 val = precise_store_data(pebs->dse);
1029 data->data_src.val = val;
1033 * We use the interrupt regs as a base because the PEBS record
1034 * does not contain a full regs set, specifically it seems to
1035 * lack segment descriptors, which get used by things like
1038 * In the simple case fix up only the IP and BP,SP regs, for
1039 * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
1040 * A possible PERF_SAMPLE_REGS will have to transfer all regs.
1043 regs->flags = pebs->flags;
1044 set_linear_ip(regs, pebs->ip);
1045 regs->bp = pebs->bp;
1046 regs->sp = pebs->sp;
1048 if (sample_type & PERF_SAMPLE_REGS_INTR) {
1049 regs->ax = pebs->ax;
1050 regs->bx = pebs->bx;
1051 regs->cx = pebs->cx;
1052 regs->dx = pebs->dx;
1053 regs->si = pebs->si;
1054 regs->di = pebs->di;
1055 regs->bp = pebs->bp;
1056 regs->sp = pebs->sp;
1058 regs->flags = pebs->flags;
1059 #ifndef CONFIG_X86_32
1060 regs->r8 = pebs->r8;
1061 regs->r9 = pebs->r9;
1062 regs->r10 = pebs->r10;
1063 regs->r11 = pebs->r11;
1064 regs->r12 = pebs->r12;
1065 regs->r13 = pebs->r13;
1066 regs->r14 = pebs->r14;
1067 regs->r15 = pebs->r15;
1071 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
1072 regs->ip = pebs->real_ip;
1073 regs->flags |= PERF_EFLAGS_EXACT;
1074 } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs))
1075 regs->flags |= PERF_EFLAGS_EXACT;
1077 regs->flags &= ~PERF_EFLAGS_EXACT;
1079 if ((sample_type & PERF_SAMPLE_ADDR) &&
1080 x86_pmu.intel_cap.pebs_format >= 1)
1081 data->addr = pebs->dla;
1083 if (x86_pmu.intel_cap.pebs_format >= 2) {
1084 /* Only set the TSX weight when no memory weight. */
1085 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1086 data->weight = intel_hsw_weight(pebs);
1088 if (sample_type & PERF_SAMPLE_TRANSACTION)
1089 data->txn = intel_hsw_transaction(pebs);
1093 * v3 supplies an accurate time stamp, so we use that
1094 * for the time stamp.
1096 * We can only do this for the default trace clock.
1098 if (x86_pmu.intel_cap.pebs_format >= 3 &&
1099 event->attr.use_clockid == 0)
1100 data->time = native_sched_clock_from_tsc(pebs->tsc);
1102 if (has_branch_stack(event))
1103 data->br_stack = &cpuc->lbr_stack;
1106 static inline void *
1107 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1109 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1114 * fmt0 does not have a status bitfield (does not use
1115 * perf_record_nhm format)
1117 if (x86_pmu.intel_cap.pebs_format < 1)
1123 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1124 struct pebs_record_nhm *p = at;
1126 if (test_bit(bit, (unsigned long *)&p->status)) {
1127 /* PEBS v3 has accurate status bits */
1128 if (x86_pmu.intel_cap.pebs_format >= 3)
1131 if (p->status == (1 << bit))
1134 /* clear non-PEBS bit and re-check */
1135 pebs_status = p->status & cpuc->pebs_enabled;
1136 pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1;
1137 if (pebs_status == (1 << bit))
1144 static void __intel_pmu_pebs_event(struct perf_event *event,
1145 struct pt_regs *iregs,
1146 void *base, void *top,
1149 struct perf_sample_data data;
1150 struct pt_regs regs;
1151 void *at = get_next_pebs_record_by_bit(base, top, bit);
1153 if (!intel_pmu_save_and_restart(event) &&
1154 !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
1158 setup_pebs_sample_data(event, iregs, at, &data, ®s);
1159 perf_event_output(event, &data, ®s);
1160 at += x86_pmu.pebs_record_size;
1161 at = get_next_pebs_record_by_bit(at, top, bit);
1165 setup_pebs_sample_data(event, iregs, at, &data, ®s);
1168 * All but the last records are processed.
1169 * The last one is left to be able to call the overflow handler.
1171 if (perf_event_overflow(event, &data, ®s)) {
1172 x86_pmu_stop(event, 0);
1178 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
1180 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1181 struct debug_store *ds = cpuc->ds;
1182 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1183 struct pebs_record_core *at, *top;
1186 if (!x86_pmu.pebs_active)
1189 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1190 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1193 * Whatever else happens, drain the thing
1195 ds->pebs_index = ds->pebs_buffer_base;
1197 if (!test_bit(0, cpuc->active_mask))
1200 WARN_ON_ONCE(!event);
1202 if (!event->attr.precise_ip)
1209 __intel_pmu_pebs_event(event, iregs, at, top, 0, n);
1212 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1214 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1215 struct debug_store *ds = cpuc->ds;
1216 struct perf_event *event;
1217 void *base, *at, *top;
1218 short counts[MAX_PEBS_EVENTS] = {};
1219 short error[MAX_PEBS_EVENTS] = {};
1222 if (!x86_pmu.pebs_active)
1225 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1226 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1228 ds->pebs_index = ds->pebs_buffer_base;
1230 if (unlikely(base >= top))
1233 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1234 struct pebs_record_nhm *p = at;
1237 /* PEBS v3 has accurate status bits */
1238 if (x86_pmu.intel_cap.pebs_format >= 3) {
1239 for_each_set_bit(bit, (unsigned long *)&p->status,
1246 pebs_status = p->status & cpuc->pebs_enabled;
1247 pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
1249 bit = find_first_bit((unsigned long *)&pebs_status,
1250 x86_pmu.max_pebs_events);
1251 if (WARN(bit >= x86_pmu.max_pebs_events,
1252 "PEBS record without PEBS event! status=%Lx pebs_enabled=%Lx active_mask=%Lx",
1253 (unsigned long long)p->status, (unsigned long long)cpuc->pebs_enabled,
1254 *(unsigned long long *)cpuc->active_mask))
1258 * The PEBS hardware does not deal well with the situation
1259 * when events happen near to each other and multiple bits
1260 * are set. But it should happen rarely.
1262 * If these events include one PEBS and multiple non-PEBS
1263 * events, it doesn't impact PEBS record. The record will
1264 * be handled normally. (slow path)
1266 * If these events include two or more PEBS events, the
1267 * records for the events can be collapsed into a single
1268 * one, and it's not possible to reconstruct all events
1269 * that caused the PEBS record. It's called collision.
1270 * If collision happened, the record will be dropped.
1272 if (p->status != (1ULL << bit)) {
1273 for_each_set_bit(i, (unsigned long *)&pebs_status,
1274 x86_pmu.max_pebs_events)
1282 for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
1283 if ((counts[bit] == 0) && (error[bit] == 0))
1286 event = cpuc->events[bit];
1287 WARN_ON_ONCE(!event);
1288 WARN_ON_ONCE(!event->attr.precise_ip);
1290 /* log dropped samples number */
1292 perf_log_lost_samples(event, error[bit]);
1295 __intel_pmu_pebs_event(event, iregs, base,
1296 top, bit, counts[bit]);
1302 * BTS, PEBS probe and setup
1305 void __init intel_ds_init(void)
1308 * No support for 32bit formats
1310 if (!boot_cpu_has(X86_FEATURE_DTES64))
1313 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
1314 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1315 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
1317 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
1318 int format = x86_pmu.intel_cap.pebs_format;
1322 printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1323 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1325 * Using >PAGE_SIZE buffers makes the WRMSR to
1326 * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
1327 * mysteriously hang on Core2.
1329 * As a workaround, we don't do this.
1331 x86_pmu.pebs_buffer_size = PAGE_SIZE;
1332 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1336 printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1337 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1338 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1342 pr_cont("PEBS fmt2%c, ", pebs_type);
1343 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1344 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1348 pr_cont("PEBS fmt3%c, ", pebs_type);
1349 x86_pmu.pebs_record_size =
1350 sizeof(struct pebs_record_skl);
1351 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1352 x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
1356 printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1362 void perf_restore_debug_store(void)
1364 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1366 if (!x86_pmu.bts && !x86_pmu.pebs)
1369 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);