1 #include <linux/export.h>
2 #include <linux/bitops.h>
7 #include <linux/sched.h>
8 #include <linux/random.h>
9 #include <asm/processor.h>
13 #include <asm/pci-direct.h>
14 #include <asm/delay.h>
17 # include <asm/mmconfig.h>
18 # include <asm/cacheflush.h>
24 * nodes_per_socket: Stores the number of nodes per socket.
25 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
26 * Node Identifiers[10:8]
28 static u32 nodes_per_socket = 1;
30 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
35 WARN_ONCE((boot_cpu_data.x86 != 0xf),
36 "%s should only be used on K8!\n", __func__);
41 err = rdmsr_safe_regs(gprs);
43 *p = gprs[0] | ((u64)gprs[2] << 32);
48 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
52 WARN_ONCE((boot_cpu_data.x86 != 0xf),
53 "%s should only be used on K8!\n", __func__);
60 return wrmsr_safe_regs(gprs);
64 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
65 * misexecution of code under Linux. Owners of such processors should
66 * contact AMD for precise details and a CPU swap.
68 * See http://www.multimania.com/poulot/k6bug.html
69 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
70 * (Publication # 21266 Issue Date: August 1998)
72 * The following test is erm.. interesting. AMD neglected to up
73 * the chip setting when fixing the bug but they also tweaked some
74 * performance at the same time..
77 extern __visible void vide(void);
78 __asm__(".globl vide\n\t.align 4\nvide: ret");
80 static void init_amd_k5(struct cpuinfo_x86 *c)
84 * General Systems BIOSen alias the cpu frequency registers
85 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
86 * drivers subsequently pokes it, and changes the CPU speed.
87 * Workaround : Remove the unneeded alias.
89 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
90 #define CBAR_ENB (0x80000000)
91 #define CBAR_KEY (0X000000CB)
92 if (c->x86_model == 9 || c->x86_model == 10) {
93 if (inl(CBAR) & CBAR_ENB)
94 outl(0 | CBAR_KEY, CBAR);
99 static void init_amd_k6(struct cpuinfo_x86 *c)
103 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
105 if (c->x86_model < 6) {
106 /* Based on AMD doc 20734R - June 2000 */
107 if (c->x86_model == 0) {
108 clear_cpu_cap(c, X86_FEATURE_APIC);
109 set_cpu_cap(c, X86_FEATURE_PGE);
114 if (c->x86_model == 6 && c->x86_mask == 1) {
115 const int K6_BUG_LOOP = 1000000;
117 void (*f_vide)(void);
120 printk(KERN_INFO "AMD K6 stepping B detected - ");
123 * It looks like AMD fixed the 2.6.2 bug and improved indirect
124 * calls at the same time.
135 if (d > 20*K6_BUG_LOOP)
137 "system stability may be impaired when more than 32 MB are used.\n");
139 printk(KERN_CONT "probably OK (after B9730xxxx).\n");
142 /* K6 with old style WHCR */
143 if (c->x86_model < 8 ||
144 (c->x86_model == 8 && c->x86_mask < 8)) {
145 /* We can only write allocate on the low 508Mb */
149 rdmsr(MSR_K6_WHCR, l, h);
150 if ((l&0x0000FFFF) == 0) {
152 l = (1<<0)|((mbytes/4)<<1);
153 local_irq_save(flags);
155 wrmsr(MSR_K6_WHCR, l, h);
156 local_irq_restore(flags);
157 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
163 if ((c->x86_model == 8 && c->x86_mask > 7) ||
164 c->x86_model == 9 || c->x86_model == 13) {
165 /* The more serious chips .. */
170 rdmsr(MSR_K6_WHCR, l, h);
171 if ((l&0xFFFF0000) == 0) {
173 l = ((mbytes>>2)<<22)|(1<<16);
174 local_irq_save(flags);
176 wrmsr(MSR_K6_WHCR, l, h);
177 local_irq_restore(flags);
178 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
185 if (c->x86_model == 10) {
186 /* AMD Geode LX is model 10 */
187 /* placeholder for any needed mods */
193 static void init_amd_k7(struct cpuinfo_x86 *c)
199 * Bit 15 of Athlon specific MSR 15, needs to be 0
200 * to enable SSE on Palomino/Morgan/Barton CPU's.
201 * If the BIOS didn't enable it already, enable it here.
203 if (c->x86_model >= 6 && c->x86_model <= 10) {
204 if (!cpu_has(c, X86_FEATURE_XMM)) {
205 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
206 msr_clear_bit(MSR_K7_HWCR, 15);
207 set_cpu_cap(c, X86_FEATURE_XMM);
212 * It's been determined by AMD that Athlons since model 8 stepping 1
213 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
214 * As per AMD technical note 27212 0.2
216 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
217 rdmsr(MSR_K7_CLK_CTL, l, h);
218 if ((l & 0xfff00000) != 0x20000000) {
220 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
221 l, ((l & 0x000fffff)|0x20000000));
222 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
226 set_cpu_cap(c, X86_FEATURE_K7);
228 /* calling is from identify_secondary_cpu() ? */
233 * Certain Athlons might work (for various values of 'work') in SMP
234 * but they are not certified as MP capable.
236 /* Athlon 660/661 is valid. */
237 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
241 /* Duron 670 is valid */
242 if ((c->x86_model == 7) && (c->x86_mask == 0))
246 * Athlon 662, Duron 671, and Athlon >model 7 have capability
247 * bit. It's worth noting that the A5 stepping (662) of some
248 * Athlon XP's have the MP bit set.
249 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
252 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
253 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
255 if (cpu_has(c, X86_FEATURE_MP))
258 /* If we get here, not a certified SMP capable AMD system. */
261 * Don't taint if we are running SMP kernel on a single non-MP
264 WARN_ONCE(1, "WARNING: This combination of AMD"
265 " processors is not suitable for SMP.\n");
266 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
272 * To workaround broken NUMA config. Read the comment in
273 * srat_detect_node().
275 static int nearby_node(int apicid)
279 for (i = apicid - 1; i >= 0; i--) {
280 node = __apicid_to_node[i];
281 if (node != NUMA_NO_NODE && node_online(node))
284 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
285 node = __apicid_to_node[i];
286 if (node != NUMA_NO_NODE && node_online(node))
289 return first_node(node_online_map); /* Shouldn't happen */
294 * Fixup core topology information for
295 * (1) AMD multi-node processors
296 * Assumption: Number of cores in each internal node is the same.
297 * (2) AMD processors supporting compute units
300 static void amd_get_topology(struct cpuinfo_x86 *c)
302 u32 cores_per_cu = 1;
304 int cpu = smp_processor_id();
306 /* get information required for multi-node processors */
307 if (cpu_has_topoext) {
308 u32 eax, ebx, ecx, edx;
310 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
311 nodes_per_socket = ((ecx >> 8) & 7) + 1;
314 /* get compute unit information */
315 smp_num_siblings = ((ebx >> 8) & 3) + 1;
316 c->compute_unit_id = ebx & 0xff;
317 cores_per_cu += ((ebx >> 8) & 3);
318 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
321 rdmsrl(MSR_FAM10H_NODE_ID, value);
322 nodes_per_socket = ((value >> 3) & 7) + 1;
327 /* fixup multi-node processor information */
328 if (nodes_per_socket > 1) {
332 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
333 cores_per_node = c->x86_max_cores / nodes_per_socket;
334 cus_per_node = cores_per_node / cores_per_cu;
336 /* store NodeID, use llc_shared_map to store sibling info */
337 per_cpu(cpu_llc_id, cpu) = node_id;
339 /* core id has to be in the [0 .. cores_per_node - 1] range */
340 c->cpu_core_id %= cores_per_node;
341 c->compute_unit_id %= cus_per_node;
347 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
348 * Assumes number of cores is a power of two.
350 static void amd_detect_cmp(struct cpuinfo_x86 *c)
354 int cpu = smp_processor_id();
356 bits = c->x86_coreid_bits;
357 /* Low order bits define the core id (index of core in socket) */
358 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
359 /* Convert the initial APIC ID into the socket ID */
360 c->phys_proc_id = c->initial_apicid >> bits;
361 /* use socket ID also for last level cache */
362 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
366 * Fix percpu cpu_llc_id here as LLC topology is different
367 * for Fam17h systems.
369 if (c->x86 != 0x17 || !cpuid_edx(0x80000006))
372 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
376 u16 amd_get_nb_id(int cpu)
380 id = per_cpu(cpu_llc_id, cpu);
384 EXPORT_SYMBOL_GPL(amd_get_nb_id);
386 u32 amd_get_nodes_per_socket(void)
388 return nodes_per_socket;
390 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
392 static void srat_detect_node(struct cpuinfo_x86 *c)
395 int cpu = smp_processor_id();
397 unsigned apicid = c->apicid;
399 node = numa_cpu_node(cpu);
400 if (node == NUMA_NO_NODE)
401 node = per_cpu(cpu_llc_id, cpu);
404 * On multi-fabric platform (e.g. Numascale NumaChip) a
405 * platform-specific handler needs to be called to fixup some
408 if (x86_cpuinit.fixup_cpu_id)
409 x86_cpuinit.fixup_cpu_id(c, node);
411 if (!node_online(node)) {
413 * Two possibilities here:
415 * - The CPU is missing memory and no node was created. In
416 * that case try picking one from a nearby CPU.
418 * - The APIC IDs differ from the HyperTransport node IDs
419 * which the K8 northbridge parsing fills in. Assume
420 * they are all increased by a constant offset, but in
421 * the same order as the HT nodeids. If that doesn't
422 * result in a usable node fall back to the path for the
425 * This workaround operates directly on the mapping between
426 * APIC ID and NUMA node, assuming certain relationship
427 * between APIC ID, HT node ID and NUMA topology. As going
428 * through CPU mapping may alter the outcome, directly
429 * access __apicid_to_node[].
431 int ht_nodeid = c->initial_apicid;
433 if (ht_nodeid >= 0 &&
434 __apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
435 node = __apicid_to_node[ht_nodeid];
436 /* Pick a nearby node */
437 if (!node_online(node))
438 node = nearby_node(apicid);
440 numa_set_node(cpu, node);
444 static void early_init_amd_mc(struct cpuinfo_x86 *c)
449 /* Multi core CPU? */
450 if (c->extended_cpuid_level < 0x80000008)
453 ecx = cpuid_ecx(0x80000008);
455 c->x86_max_cores = (ecx & 0xff) + 1;
457 /* CPU telling us the core id bits shift? */
458 bits = (ecx >> 12) & 0xF;
460 /* Otherwise recompute */
462 while ((1 << bits) < c->x86_max_cores)
466 c->x86_coreid_bits = bits;
470 static void bsp_init_amd(struct cpuinfo_x86 *c)
475 unsigned long long tseg;
478 * Split up direct mapping around the TSEG SMM area.
479 * Don't do it for gbpages because there seems very little
480 * benefit in doing so.
482 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
483 unsigned long pfn = tseg >> PAGE_SHIFT;
485 printk(KERN_DEBUG "tseg: %010llx\n", tseg);
486 if (pfn_range_is_mapped(pfn, pfn + 1))
487 set_memory_4k((unsigned long)__va(tseg), 1);
492 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
495 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
498 rdmsrl(MSR_K7_HWCR, val);
499 if (!(val & BIT(24)))
500 printk(KERN_WARNING FW_BUG "TSC doesn't count "
501 "with P0 frequency!\n");
505 if (c->x86 == 0x15) {
506 unsigned long upperbit;
509 cpuid = cpuid_edx(0x80000005);
510 assoc = cpuid >> 16 & 0xff;
511 upperbit = ((cpuid >> 24) << 10) / assoc;
513 va_align.mask = (upperbit - 1) & PAGE_MASK;
514 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
516 /* A random value per boot for bit slice [12:upper_bit) */
517 va_align.bits = get_random_int() & va_align.mask;
520 if (cpu_has(c, X86_FEATURE_MWAITX))
524 static void early_init_amd(struct cpuinfo_x86 *c)
526 early_init_amd_mc(c);
529 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
530 * with P/T states and does not stop in deep C-states
532 if (c->x86_power & (1 << 8)) {
533 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
534 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
535 if (!check_tsc_unstable())
536 set_sched_clock_stable();
540 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
542 /* Set MTRR capability flag if appropriate */
544 if (c->x86_model == 13 || c->x86_model == 9 ||
545 (c->x86_model == 8 && c->x86_mask >= 8))
546 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
548 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
550 * ApicID can always be treated as an 8-bit value for AMD APIC versions
551 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
552 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
555 if (cpu_has_apic && c->x86 > 0x16) {
556 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
557 } else if (cpu_has_apic && c->x86 >= 0xf) {
558 /* check CPU config space for extended APIC ID */
560 val = read_pci_config(0, 24, 0, 0x68);
561 if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18)))
562 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
567 * This is only needed to tell the kernel whether to use VMCALL
568 * and VMMCALL. VMMCALL is never executed except under virt, so
569 * we can set it unconditionally.
571 set_cpu_cap(c, X86_FEATURE_VMMCALL);
573 /* F16h erratum 793, CVE-2013-6885 */
574 if (c->x86 == 0x16 && c->x86_model <= 0xf)
575 msr_set_bit(MSR_AMD64_LS_CFG, 15);
578 static const int amd_erratum_383[];
579 static const int amd_erratum_400[];
580 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
582 static void init_amd_k8(struct cpuinfo_x86 *c)
587 /* On C+ stepping K8 rep microcode works well for copy/memset */
588 level = cpuid_eax(1);
589 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
590 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
593 * Some BIOSes incorrectly force this feature, but only K8 revision D
594 * (model = 0x14) and later actually support it.
595 * (AMD Erratum #110, docId: 25759).
597 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
598 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
599 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
600 value &= ~BIT_64(32);
601 wrmsrl_amd_safe(0xc001100d, value);
605 if (!c->x86_model_id[0])
606 strcpy(c->x86_model_id, "Hammer");
610 * Disable TLB flush filter by setting HWCR.FFDIS on K8
611 * bit 6 of msr C001_0015
613 * Errata 63 for SH-B3 steppings
614 * Errata 122 for all steppings (F+ have it disabled by default)
616 msr_set_bit(MSR_K7_HWCR, 6);
620 static void init_amd_gh(struct cpuinfo_x86 *c)
623 /* do this for boot cpu */
624 if (c == &boot_cpu_data)
625 check_enable_amd_mmconf_dmi();
627 fam10h_check_enable_mmcfg();
631 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
632 * is always needed when GART is enabled, even in a kernel which has no
633 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
634 * If it doesn't, we do it here as suggested by the BKDG.
636 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
638 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
641 * On family 10h BIOS may not have properly enabled WC+ support, causing
642 * it to be converted to CD memtype. This may result in performance
643 * degradation for certain nested-paging guests. Prevent this conversion
644 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
646 * NOTE: we want to use the _safe accessors so as not to #GP kvm
647 * guests on older kvm hosts.
649 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
651 if (cpu_has_amd_erratum(c, amd_erratum_383))
652 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
655 #define MSR_AMD64_DE_CFG 0xC0011029
657 static void init_amd_ln(struct cpuinfo_x86 *c)
660 * Apply erratum 665 fix unconditionally so machines without a BIOS
663 msr_set_bit(MSR_AMD64_DE_CFG, 31);
666 static void init_amd_bd(struct cpuinfo_x86 *c)
670 /* re-enable TopologyExtensions if switched off by BIOS */
671 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
672 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
674 if (msr_set_bit(0xc0011005, 54) > 0) {
675 rdmsrl(0xc0011005, value);
676 if (value & BIT_64(54)) {
677 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
678 pr_info(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
684 * The way access filter has a performance penalty on some workloads.
685 * Disable it on the affected CPUs.
687 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
688 if (!rdmsrl_safe(0xc0011021, &value) && !(value & 0x1E)) {
690 wrmsrl_safe(0xc0011021, value);
695 static void init_amd(struct cpuinfo_x86 *c)
702 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
703 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
705 clear_cpu_cap(c, 0*32+31);
708 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
710 /* get apicid instead of initial apic id from cpuid */
711 c->apicid = hard_smp_processor_id();
713 /* K6s reports MCEs but don't actually have all the MSRs */
715 clear_cpu_cap(c, X86_FEATURE_MCE);
718 case 4: init_amd_k5(c); break;
719 case 5: init_amd_k6(c); break;
720 case 6: init_amd_k7(c); break;
721 case 0xf: init_amd_k8(c); break;
722 case 0x10: init_amd_gh(c); break;
723 case 0x12: init_amd_ln(c); break;
724 case 0x15: init_amd_bd(c); break;
727 /* Enable workaround for FXSAVE leak */
729 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
731 cpu_detect_cache_sizes(c);
733 /* Multi core CPU? */
734 if (c->extended_cpuid_level >= 0x80000008) {
743 init_amd_cacheinfo(c);
746 set_cpu_cap(c, X86_FEATURE_K8);
749 /* MFENCE stops RDTSC speculation */
750 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
754 * Family 0x12 and above processors have APIC timer
755 * running in deep C states.
758 set_cpu_cap(c, X86_FEATURE_ARAT);
760 if (cpu_has_amd_erratum(c, amd_erratum_400))
761 set_cpu_bug(c, X86_BUG_AMD_APIC_C1E);
763 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
765 /* 3DNow or LM implies PREFETCHW */
766 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
767 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
768 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
770 /* AMD CPUs don't reset SS attributes on SYSRET */
771 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
775 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
777 /* AMD errata T13 (order #21922) */
780 if (c->x86_model == 3 && c->x86_mask == 0)
782 /* Tbird rev A1/A2 */
783 if (c->x86_model == 4 &&
784 (c->x86_mask == 0 || c->x86_mask == 1))
791 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
793 u32 ebx, eax, ecx, edx;
799 if (c->extended_cpuid_level < 0x80000006)
802 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
804 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
805 tlb_lli_4k[ENTRIES] = ebx & mask;
808 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
809 * characteristics from the CPUID function 0x80000005 instead.
812 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
816 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
817 if (!((eax >> 16) & mask))
818 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
820 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
822 /* a 4M entry uses two 2M entries */
823 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
825 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
828 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
829 tlb_lli_2m[ENTRIES] = 1024;
831 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
832 tlb_lli_2m[ENTRIES] = eax & 0xff;
835 tlb_lli_2m[ENTRIES] = eax & mask;
837 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
840 static const struct cpu_dev amd_cpu_dev = {
842 .c_ident = { "AuthenticAMD" },
845 { .family = 4, .model_names =
856 .legacy_cache_size = amd_size_cache,
858 .c_early_init = early_init_amd,
859 .c_detect_tlb = cpu_detect_tlb_amd,
860 .c_bsp_init = bsp_init_amd,
862 .c_x86_vendor = X86_VENDOR_AMD,
865 cpu_dev_register(amd_cpu_dev);
868 * AMD errata checking
870 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
871 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
872 * have an OSVW id assigned, which it takes as first argument. Both take a
873 * variable number of family-specific model-stepping ranges created by
878 * const int amd_erratum_319[] =
879 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
880 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
881 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
884 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
885 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
886 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
887 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
888 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
889 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
890 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
892 static const int amd_erratum_400[] =
893 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
894 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
896 static const int amd_erratum_383[] =
897 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
900 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
902 int osvw_id = *erratum++;
906 if (osvw_id >= 0 && osvw_id < 65536 &&
907 cpu_has(cpu, X86_FEATURE_OSVW)) {
910 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
911 if (osvw_id < osvw_len) {
914 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
916 return osvw_bits & (1ULL << (osvw_id & 0x3f));
920 /* OSVW unavailable or ID unknown, match family-model-stepping range */
921 ms = (cpu->x86_model << 4) | cpu->x86_mask;
922 while ((range = *erratum++))
923 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
924 (ms >= AMD_MODEL_RANGE_START(range)) &&
925 (ms <= AMD_MODEL_RANGE_END(range)))
931 void set_dr_addr_mask(unsigned long mask, int dr)
938 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
943 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);