2 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Enable support of hierarchical irqdomains
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/interrupt.h>
14 #include <linux/init.h>
15 #include <linux/compiler.h>
16 #include <linux/slab.h>
17 #include <asm/irqdomain.h>
18 #include <asm/hw_irq.h>
20 #include <asm/i8259.h>
22 #include <asm/irq_remapping.h>
24 struct apic_chip_data {
27 cpumask_var_t old_domain;
28 u8 move_in_progress : 1;
31 struct irq_domain *x86_vector_domain;
32 static DEFINE_RAW_SPINLOCK(vector_lock);
33 static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask;
34 static struct irq_chip lapic_controller;
35 #ifdef CONFIG_X86_IO_APIC
36 static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY];
39 void lock_vector_lock(void)
41 /* Used to the online set of cpus does not change
42 * during assign_irq_vector.
44 raw_spin_lock(&vector_lock);
47 void unlock_vector_lock(void)
49 raw_spin_unlock(&vector_lock);
52 static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data)
57 while (irq_data->parent_data)
58 irq_data = irq_data->parent_data;
60 return irq_data->chip_data;
63 struct irq_cfg *irqd_cfg(struct irq_data *irq_data)
65 struct apic_chip_data *data = apic_chip_data(irq_data);
67 return data ? &data->cfg : NULL;
70 struct irq_cfg *irq_cfg(unsigned int irq)
72 return irqd_cfg(irq_get_irq_data(irq));
75 static struct apic_chip_data *alloc_apic_chip_data(int node)
77 struct apic_chip_data *data;
79 data = kzalloc_node(sizeof(*data), GFP_KERNEL, node);
82 if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node))
84 if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node))
88 free_cpumask_var(data->domain);
94 static void free_apic_chip_data(struct apic_chip_data *data)
97 free_cpumask_var(data->domain);
98 free_cpumask_var(data->old_domain);
103 static int __assign_irq_vector(int irq, struct apic_chip_data *d,
104 const struct cpumask *mask)
107 * NOTE! The local APIC isn't very good at handling
108 * multiple interrupts at the same interrupt level.
109 * As the interrupt level is determined by taking the
110 * vector number and shifting that right by 4, we
111 * want to spread these out a bit so that they don't
112 * all fall in the same interrupt level.
114 * Also, we've got to be careful not to trash gate
115 * 0x80, because int 0x80 is hm, kind of importantish. ;)
117 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
118 static int current_offset = VECTOR_OFFSET_START % 16;
122 * If there is still a move in progress or the previous move has not
123 * been cleaned up completely, tell the caller to come back later.
125 if (d->move_in_progress ||
126 cpumask_intersects(d->old_domain, cpu_online_mask))
129 /* Only try and allocate irqs on cpus that are present */
130 cpumask_clear(d->old_domain);
131 cpumask_clear(searched_cpumask);
132 cpu = cpumask_first_and(mask, cpu_online_mask);
133 while (cpu < nr_cpu_ids) {
136 /* Get the possible target cpus for @mask/@cpu from the apic */
137 apic->vector_allocation_domain(cpu, vector_cpumask, mask);
140 * Clear the offline cpus from @vector_cpumask for searching
141 * and verify whether the result overlaps with @mask. If true,
142 * then the call to apic->cpu_mask_to_apicid_and() will
143 * succeed as well. If not, no point in trying to find a
144 * vector in this mask.
146 cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask);
147 if (!cpumask_intersects(vector_searchmask, mask))
150 if (cpumask_subset(vector_cpumask, d->domain)) {
151 if (cpumask_equal(vector_cpumask, d->domain))
154 * Mark the cpus which are not longer in the mask for
157 cpumask_andnot(d->old_domain, d->domain, vector_cpumask);
158 vector = d->cfg.vector;
162 vector = current_vector;
163 offset = current_offset;
166 if (vector >= first_system_vector) {
167 offset = (offset + 1) % 16;
168 vector = FIRST_EXTERNAL_VECTOR + offset;
171 /* If the search wrapped around, try the next cpu */
172 if (unlikely(current_vector == vector))
175 if (test_bit(vector, used_vectors))
178 for_each_cpu(new_cpu, vector_searchmask) {
179 if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector]))
183 current_vector = vector;
184 current_offset = offset;
185 /* Schedule the old vector for cleanup on all cpus */
187 cpumask_copy(d->old_domain, d->domain);
188 for_each_cpu(new_cpu, vector_searchmask)
189 per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq);
194 * We exclude the current @vector_cpumask from the requested
195 * @mask and try again with the next online cpu in the
196 * result. We cannot modify @mask, so we use @vector_cpumask
197 * as a temporary buffer here as it will be reassigned when
198 * calling apic->vector_allocation_domain() above.
200 cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask);
201 cpumask_andnot(vector_cpumask, mask, searched_cpumask);
202 cpu = cpumask_first_and(vector_cpumask, cpu_online_mask);
209 * Exclude offline cpus from the cleanup mask and set the
210 * move_in_progress flag when the result is not empty.
212 cpumask_and(d->old_domain, d->old_domain, cpu_online_mask);
213 d->move_in_progress = !cpumask_empty(d->old_domain);
214 d->cfg.old_vector = d->move_in_progress ? d->cfg.vector : 0;
215 d->cfg.vector = vector;
216 cpumask_copy(d->domain, vector_cpumask);
219 * Cache destination APIC IDs into cfg->dest_apicid. This cannot fail
220 * as we already established, that mask & d->domain & cpu_online_mask
223 BUG_ON(apic->cpu_mask_to_apicid_and(mask, d->domain,
224 &d->cfg.dest_apicid));
228 static int assign_irq_vector(int irq, struct apic_chip_data *data,
229 const struct cpumask *mask)
234 raw_spin_lock_irqsave(&vector_lock, flags);
235 err = __assign_irq_vector(irq, data, mask);
236 raw_spin_unlock_irqrestore(&vector_lock, flags);
240 static int assign_irq_vector_policy(int irq, int node,
241 struct apic_chip_data *data,
242 struct irq_alloc_info *info)
244 if (info && info->mask)
245 return assign_irq_vector(irq, data, info->mask);
246 if (node != NUMA_NO_NODE &&
247 assign_irq_vector(irq, data, cpumask_of_node(node)) == 0)
249 return assign_irq_vector(irq, data, apic->target_cpus());
252 static void clear_irq_vector(int irq, struct apic_chip_data *data)
254 struct irq_desc *desc;
257 if (!data->cfg.vector)
260 vector = data->cfg.vector;
261 for_each_cpu_and(cpu, data->domain, cpu_online_mask)
262 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
264 data->cfg.vector = 0;
265 cpumask_clear(data->domain);
268 * If move is in progress or the old_domain mask is not empty,
269 * i.e. the cleanup IPI has not been processed yet, we need to remove
270 * the old references to desc from all cpus vector tables.
272 if (!data->move_in_progress && cpumask_empty(data->old_domain))
275 desc = irq_to_desc(irq);
276 for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) {
277 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
279 if (per_cpu(vector_irq, cpu)[vector] != desc)
281 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
285 data->move_in_progress = 0;
288 void init_irq_alloc_info(struct irq_alloc_info *info,
289 const struct cpumask *mask)
291 memset(info, 0, sizeof(*info));
295 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
300 memset(dst, 0, sizeof(*dst));
303 static void x86_vector_free_irqs(struct irq_domain *domain,
304 unsigned int virq, unsigned int nr_irqs)
306 struct apic_chip_data *apic_data;
307 struct irq_data *irq_data;
311 for (i = 0; i < nr_irqs; i++) {
312 irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i);
313 if (irq_data && irq_data->chip_data) {
314 raw_spin_lock_irqsave(&vector_lock, flags);
315 clear_irq_vector(virq + i, irq_data->chip_data);
316 apic_data = irq_data->chip_data;
317 irq_domain_reset_irq_data(irq_data);
318 raw_spin_unlock_irqrestore(&vector_lock, flags);
319 free_apic_chip_data(apic_data);
320 #ifdef CONFIG_X86_IO_APIC
321 if (virq + i < nr_legacy_irqs())
322 legacy_irq_data[virq + i] = NULL;
328 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
329 unsigned int nr_irqs, void *arg)
331 struct irq_alloc_info *info = arg;
332 struct apic_chip_data *data;
333 struct irq_data *irq_data;
339 /* Currently vector allocator can't guarantee contiguous allocations */
340 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
343 for (i = 0; i < nr_irqs; i++) {
344 irq_data = irq_domain_get_irq_data(domain, virq + i);
346 node = irq_data_get_node(irq_data);
347 #ifdef CONFIG_X86_IO_APIC
348 if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i])
349 data = legacy_irq_data[virq + i];
352 data = alloc_apic_chip_data(node);
358 irq_data->chip = &lapic_controller;
359 irq_data->chip_data = data;
360 irq_data->hwirq = virq + i;
361 err = assign_irq_vector_policy(virq + i, node, data, info);
369 x86_vector_free_irqs(domain, virq, i + 1);
373 static const struct irq_domain_ops x86_vector_domain_ops = {
374 .alloc = x86_vector_alloc_irqs,
375 .free = x86_vector_free_irqs,
378 int __init arch_probe_nr_irqs(void)
382 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
383 nr_irqs = NR_VECTORS * nr_cpu_ids;
385 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
386 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
388 * for MSI and HT dyn irq
390 if (gsi_top <= NR_IRQS_LEGACY)
391 nr += 8 * nr_cpu_ids;
399 * We don't know if PIC is present at this point so we need to do
400 * probe() to get the right number of legacy IRQs.
402 return legacy_pic->probe();
405 #ifdef CONFIG_X86_IO_APIC
406 static void init_legacy_irqs(void)
408 int i, node = cpu_to_node(0);
409 struct apic_chip_data *data;
412 * For legacy IRQ's, start with assigning irq0 to irq15 to
413 * ISA_IRQ_VECTOR(i) for all cpu's.
415 for (i = 0; i < nr_legacy_irqs(); i++) {
416 data = legacy_irq_data[i] = alloc_apic_chip_data(node);
419 data->cfg.vector = ISA_IRQ_VECTOR(i);
420 cpumask_setall(data->domain);
421 irq_set_chip_data(i, data);
425 static void init_legacy_irqs(void) { }
428 int __init arch_early_irq_init(void)
432 x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops,
434 BUG_ON(x86_vector_domain == NULL);
435 irq_set_default_host(x86_vector_domain);
437 arch_init_msi_domain(x86_vector_domain);
438 arch_init_htirq_domain(x86_vector_domain);
440 BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL));
441 BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL));
442 BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL));
444 return arch_early_ioapic_init();
447 /* Initialize vector_irq on a new cpu */
448 static void __setup_vector_irq(int cpu)
450 struct apic_chip_data *data;
451 struct irq_desc *desc;
454 /* Mark the inuse vectors */
455 for_each_irq_desc(irq, desc) {
456 struct irq_data *idata = irq_desc_get_irq_data(desc);
458 data = apic_chip_data(idata);
459 if (!data || !cpumask_test_cpu(cpu, data->domain))
461 vector = data->cfg.vector;
462 per_cpu(vector_irq, cpu)[vector] = desc;
464 /* Mark the free vectors */
465 for (vector = 0; vector < NR_VECTORS; ++vector) {
466 desc = per_cpu(vector_irq, cpu)[vector];
467 if (IS_ERR_OR_NULL(desc))
470 data = apic_chip_data(irq_desc_get_irq_data(desc));
471 if (!cpumask_test_cpu(cpu, data->domain))
472 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
477 * Setup the vector to irq mappings. Must be called with vector_lock held.
479 void setup_vector_irq(int cpu)
483 lockdep_assert_held(&vector_lock);
485 * On most of the platforms, legacy PIC delivers the interrupts on the
486 * boot cpu. But there are certain platforms where PIC interrupts are
487 * delivered to multiple cpu's. If the legacy IRQ is handled by the
488 * legacy PIC, for the new cpu that is coming online, setup the static
489 * legacy vector to irq mapping:
491 for (irq = 0; irq < nr_legacy_irqs(); irq++)
492 per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq);
494 __setup_vector_irq(cpu);
497 static int apic_retrigger_irq(struct irq_data *irq_data)
499 struct apic_chip_data *data = apic_chip_data(irq_data);
503 raw_spin_lock_irqsave(&vector_lock, flags);
504 cpu = cpumask_first_and(data->domain, cpu_online_mask);
505 apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector);
506 raw_spin_unlock_irqrestore(&vector_lock, flags);
511 void apic_ack_edge(struct irq_data *data)
513 irq_complete_move(irqd_cfg(data));
518 static int apic_set_affinity(struct irq_data *irq_data,
519 const struct cpumask *dest, bool force)
521 struct apic_chip_data *data = irq_data->chip_data;
522 int err, irq = irq_data->irq;
524 if (!config_enabled(CONFIG_SMP))
527 if (!cpumask_intersects(dest, cpu_online_mask))
530 err = assign_irq_vector(irq, data, dest);
531 return err ? err : IRQ_SET_MASK_OK;
534 static struct irq_chip lapic_controller = {
535 .irq_ack = apic_ack_edge,
536 .irq_set_affinity = apic_set_affinity,
537 .irq_retrigger = apic_retrigger_irq,
541 static void __send_cleanup_vector(struct apic_chip_data *data)
543 raw_spin_lock(&vector_lock);
544 cpumask_and(data->old_domain, data->old_domain, cpu_online_mask);
545 data->move_in_progress = 0;
546 if (!cpumask_empty(data->old_domain))
547 apic->send_IPI_mask(data->old_domain, IRQ_MOVE_CLEANUP_VECTOR);
548 raw_spin_unlock(&vector_lock);
551 void send_cleanup_vector(struct irq_cfg *cfg)
553 struct apic_chip_data *data;
555 data = container_of(cfg, struct apic_chip_data, cfg);
556 if (data->move_in_progress)
557 __send_cleanup_vector(data);
560 asmlinkage __visible void smp_irq_move_cleanup_interrupt(void)
566 /* Prevent vectors vanishing under us */
567 raw_spin_lock(&vector_lock);
569 me = smp_processor_id();
570 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
571 struct apic_chip_data *data;
572 struct irq_desc *desc;
576 desc = __this_cpu_read(vector_irq[vector]);
577 if (IS_ERR_OR_NULL(desc))
580 if (!raw_spin_trylock(&desc->lock)) {
581 raw_spin_unlock(&vector_lock);
583 raw_spin_lock(&vector_lock);
587 data = apic_chip_data(irq_desc_get_irq_data(desc));
592 * Nothing to cleanup if irq migration is in progress
593 * or this cpu is not set in the cleanup mask.
595 if (data->move_in_progress ||
596 !cpumask_test_cpu(me, data->old_domain))
600 * We have two cases to handle here:
601 * 1) vector is unchanged but the target mask got reduced
602 * 2) vector and the target mask has changed
604 * #1 is obvious, but in #2 we have two vectors with the same
605 * irq descriptor: the old and the new vector. So we need to
606 * make sure that we only cleanup the old vector. The new
607 * vector has the current @vector number in the config and
608 * this cpu is part of the target mask. We better leave that
611 if (vector == data->cfg.vector &&
612 cpumask_test_cpu(me, data->domain))
615 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
617 * Check if the vector that needs to be cleanedup is
618 * registered at the cpu's IRR. If so, then this is not
619 * the best time to clean it up. Lets clean it up in the
620 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
623 if (irr & (1 << (vector % 32))) {
624 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
627 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
628 cpumask_clear_cpu(me, data->old_domain);
630 raw_spin_unlock(&desc->lock);
633 raw_spin_unlock(&vector_lock);
638 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
641 struct apic_chip_data *data;
643 data = container_of(cfg, struct apic_chip_data, cfg);
644 if (likely(!data->move_in_progress))
647 me = smp_processor_id();
648 if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain))
649 __send_cleanup_vector(data);
652 void irq_complete_move(struct irq_cfg *cfg)
654 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
658 * Called from fixup_irqs() with @desc->lock held and interrupts disabled.
660 void irq_force_complete_move(struct irq_desc *desc)
662 struct irq_data *irqdata;
663 struct apic_chip_data *data;
668 * The function is called for all descriptors regardless of which
669 * irqdomain they belong to. For example if an IRQ is provided by
670 * an irq_chip as part of a GPIO driver, the chip data for that
671 * descriptor is specific to the irq_chip in question.
673 * Check first that the chip_data is what we expect
674 * (apic_chip_data) before touching it any further.
676 irqdata = irq_domain_get_irq_data(x86_vector_domain,
677 irq_desc_get_irq(desc));
681 data = apic_chip_data(irqdata);
682 cfg = data ? &data->cfg : NULL;
688 * This is tricky. If the cleanup of @data->old_domain has not been
689 * done yet, then the following setaffinity call will fail with
690 * -EBUSY. This can leave the interrupt in a stale state.
692 * All CPUs are stuck in stop machine with interrupts disabled so
693 * calling __irq_complete_move() would be completely pointless.
695 raw_spin_lock(&vector_lock);
697 * Clean out all offline cpus (including the outgoing one) from the
700 cpumask_and(data->old_domain, data->old_domain, cpu_online_mask);
703 * If move_in_progress is cleared and the old_domain mask is empty,
704 * then there is nothing to cleanup. fixup_irqs() will take care of
705 * the stale vectors on the outgoing cpu.
707 if (!data->move_in_progress && cpumask_empty(data->old_domain)) {
708 raw_spin_unlock(&vector_lock);
713 * 1) The interrupt is in move_in_progress state. That means that we
714 * have not seen an interrupt since the io_apic was reprogrammed to
717 * 2) The interrupt has fired on the new vector, but the cleanup IPIs
718 * have not been processed yet.
720 if (data->move_in_progress) {
722 * In theory there is a race:
724 * set_ioapic(new_vector) <-- Interrupt is raised before update
725 * is effective, i.e. it's raised on
728 * So if the target cpu cannot handle that interrupt before
729 * the old vector is cleaned up, we get a spurious interrupt
730 * and in the worst case the ioapic irq line becomes stale.
732 * But in case of cpu hotplug this should be a non issue
733 * because if the affinity update happens right before all
734 * cpus rendevouz in stop machine, there is no way that the
735 * interrupt can be blocked on the target cpu because all cpus
736 * loops first with interrupts enabled in stop machine, so the
737 * old vector is not yet cleaned up when the interrupt fires.
739 * So the only way to run into this issue is if the delivery
740 * of the interrupt on the apic/system bus would be delayed
741 * beyond the point where the target cpu disables interrupts
742 * in stop machine. I doubt that it can happen, but at least
743 * there is a theroretical chance. Virtualization might be
744 * able to expose this, but AFAICT the IOAPIC emulation is not
745 * as stupid as the real hardware.
747 * Anyway, there is nothing we can do about that at this point
748 * w/o refactoring the whole fixup_irq() business completely.
749 * We print at least the irq number and the old vector number,
750 * so we have the necessary information when a problem in that
753 pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n",
754 irqdata->irq, cfg->old_vector);
757 * If old_domain is not empty, then other cpus still have the irq
758 * descriptor set in their vector array. Clean it up.
760 for_each_cpu(cpu, data->old_domain)
761 per_cpu(vector_irq, cpu)[cfg->old_vector] = VECTOR_UNUSED;
763 /* Cleanup the left overs of the (half finished) move */
764 cpumask_clear(data->old_domain);
765 data->move_in_progress = 0;
766 raw_spin_unlock(&vector_lock);
770 static void __init print_APIC_field(int base)
776 for (i = 0; i < 8; i++)
777 pr_cont("%08x", apic_read(base + i*0x10));
782 static void __init print_local_APIC(void *dummy)
784 unsigned int i, v, ver, maxlvt;
787 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
788 smp_processor_id(), hard_smp_processor_id());
789 v = apic_read(APIC_ID);
790 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
791 v = apic_read(APIC_LVR);
792 pr_info("... APIC VERSION: %08x\n", v);
793 ver = GET_APIC_VERSION(v);
794 maxlvt = lapic_get_maxlvt();
796 v = apic_read(APIC_TASKPRI);
797 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
800 if (APIC_INTEGRATED(ver)) {
801 if (!APIC_XAPIC(ver)) {
802 v = apic_read(APIC_ARBPRI);
803 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
804 v, v & APIC_ARBPRI_MASK);
806 v = apic_read(APIC_PROCPRI);
807 pr_debug("... APIC PROCPRI: %08x\n", v);
811 * Remote read supported only in the 82489DX and local APIC for
812 * Pentium processors.
814 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
815 v = apic_read(APIC_RRR);
816 pr_debug("... APIC RRR: %08x\n", v);
819 v = apic_read(APIC_LDR);
820 pr_debug("... APIC LDR: %08x\n", v);
821 if (!x2apic_enabled()) {
822 v = apic_read(APIC_DFR);
823 pr_debug("... APIC DFR: %08x\n", v);
825 v = apic_read(APIC_SPIV);
826 pr_debug("... APIC SPIV: %08x\n", v);
828 pr_debug("... APIC ISR field:\n");
829 print_APIC_field(APIC_ISR);
830 pr_debug("... APIC TMR field:\n");
831 print_APIC_field(APIC_TMR);
832 pr_debug("... APIC IRR field:\n");
833 print_APIC_field(APIC_IRR);
836 if (APIC_INTEGRATED(ver)) {
837 /* Due to the Pentium erratum 3AP. */
839 apic_write(APIC_ESR, 0);
841 v = apic_read(APIC_ESR);
842 pr_debug("... APIC ESR: %08x\n", v);
845 icr = apic_icr_read();
846 pr_debug("... APIC ICR: %08x\n", (u32)icr);
847 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
849 v = apic_read(APIC_LVTT);
850 pr_debug("... APIC LVTT: %08x\n", v);
854 v = apic_read(APIC_LVTPC);
855 pr_debug("... APIC LVTPC: %08x\n", v);
857 v = apic_read(APIC_LVT0);
858 pr_debug("... APIC LVT0: %08x\n", v);
859 v = apic_read(APIC_LVT1);
860 pr_debug("... APIC LVT1: %08x\n", v);
864 v = apic_read(APIC_LVTERR);
865 pr_debug("... APIC LVTERR: %08x\n", v);
868 v = apic_read(APIC_TMICT);
869 pr_debug("... APIC TMICT: %08x\n", v);
870 v = apic_read(APIC_TMCCT);
871 pr_debug("... APIC TMCCT: %08x\n", v);
872 v = apic_read(APIC_TDCR);
873 pr_debug("... APIC TDCR: %08x\n", v);
875 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
876 v = apic_read(APIC_EFEAT);
877 maxlvt = (v >> 16) & 0xff;
878 pr_debug("... APIC EFEAT: %08x\n", v);
879 v = apic_read(APIC_ECTRL);
880 pr_debug("... APIC ECTRL: %08x\n", v);
881 for (i = 0; i < maxlvt; i++) {
882 v = apic_read(APIC_EILVTn(i));
883 pr_debug("... APIC EILVT%d: %08x\n", i, v);
889 static void __init print_local_APICs(int maxcpu)
897 for_each_online_cpu(cpu) {
900 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
905 static void __init print_PIC(void)
910 if (!nr_legacy_irqs())
913 pr_debug("\nprinting PIC contents\n");
915 raw_spin_lock_irqsave(&i8259A_lock, flags);
917 v = inb(0xa1) << 8 | inb(0x21);
918 pr_debug("... PIC IMR: %04x\n", v);
920 v = inb(0xa0) << 8 | inb(0x20);
921 pr_debug("... PIC IRR: %04x\n", v);
925 v = inb(0xa0) << 8 | inb(0x20);
929 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
931 pr_debug("... PIC ISR: %04x\n", v);
933 v = inb(0x4d1) << 8 | inb(0x4d0);
934 pr_debug("... PIC ELCR: %04x\n", v);
937 static int show_lapic __initdata = 1;
938 static __init int setup_show_lapic(char *arg)
942 if (strcmp(arg, "all") == 0) {
943 show_lapic = CONFIG_NR_CPUS;
945 get_option(&arg, &num);
952 __setup("show_lapic=", setup_show_lapic);
954 static int __init print_ICs(void)
956 if (apic_verbosity == APIC_QUIET)
961 /* don't print out if apic is not there */
962 if (!cpu_has_apic && !apic_from_smp_config())
965 print_local_APICs(show_lapic);
971 late_initcall(print_ICs);