2 * T4240 Silicon/SoC Device Tree Source (pre include)
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37 /include/ "e6500_power_isa.dtsi"
40 compatible = "fsl,T4240";
43 interrupt-parent = <&mpic>;
68 cpu0: PowerPC,e6500@0 {
72 next-level-cache = <&L2_1>;
73 fsl,portid-mapping = <0x80000000>;
75 cpu1: PowerPC,e6500@2 {
79 next-level-cache = <&L2_1>;
80 fsl,portid-mapping = <0x80000000>;
82 cpu2: PowerPC,e6500@4 {
86 next-level-cache = <&L2_1>;
87 fsl,portid-mapping = <0x80000000>;
89 cpu3: PowerPC,e6500@6 {
93 next-level-cache = <&L2_1>;
94 fsl,portid-mapping = <0x80000000>;
96 cpu4: PowerPC,e6500@8 {
100 next-level-cache = <&L2_2>;
101 fsl,portid-mapping = <0x40000000>;
103 cpu5: PowerPC,e6500@10 {
107 next-level-cache = <&L2_2>;
108 fsl,portid-mapping = <0x40000000>;
110 cpu6: PowerPC,e6500@12 {
114 next-level-cache = <&L2_2>;
115 fsl,portid-mapping = <0x40000000>;
117 cpu7: PowerPC,e6500@14 {
121 next-level-cache = <&L2_2>;
122 fsl,portid-mapping = <0x40000000>;
124 cpu8: PowerPC,e6500@16 {
128 next-level-cache = <&L2_3>;
129 fsl,portid-mapping = <0x20000000>;
131 cpu9: PowerPC,e6500@18 {
135 next-level-cache = <&L2_3>;
136 fsl,portid-mapping = <0x20000000>;
138 cpu10: PowerPC,e6500@20 {
142 next-level-cache = <&L2_3>;
143 fsl,portid-mapping = <0x20000000>;
145 cpu11: PowerPC,e6500@22 {
149 next-level-cache = <&L2_3>;
150 fsl,portid-mapping = <0x20000000>;