2 * P5020/5010 Silicon/SoC Device Tree Source (post include)
4 * Copyright 2011 - 2014 Freescale Semiconductor Inc.
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36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
42 interrupts = <25 2 0 0>;
47 /* controller at 0x200000 */
49 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
53 bus-range = <0x0 0xff>;
54 clock-frequency = <33333333>;
55 interrupts = <16 2 1 15>;
56 fsl,iommu-parent = <&pamu0>;
57 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
60 #interrupt-cells = <1>;
64 interrupts = <16 2 1 15>;
65 interrupt-map-mask = <0xf800 0 0 7>;
68 0000 0 0 1 &mpic 40 1 0 0
69 0000 0 0 2 &mpic 1 1 0 0
70 0000 0 0 3 &mpic 2 1 0 0
71 0000 0 0 4 &mpic 3 1 0 0
76 /* controller at 0x201000 */
78 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
83 clock-frequency = <33333333>;
84 interrupts = <16 2 1 14>;
85 fsl,iommu-parent = <&pamu0>;
86 fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
89 #interrupt-cells = <1>;
93 interrupts = <16 2 1 14>;
94 interrupt-map-mask = <0xf800 0 0 7>;
97 0000 0 0 1 &mpic 41 1 0 0
98 0000 0 0 2 &mpic 5 1 0 0
99 0000 0 0 3 &mpic 6 1 0 0
100 0000 0 0 4 &mpic 7 1 0 0
105 /* controller at 0x202000 */
107 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
110 #address-cells = <3>;
111 bus-range = <0x0 0xff>;
112 clock-frequency = <33333333>;
113 interrupts = <16 2 1 13>;
114 fsl,iommu-parent = <&pamu0>;
115 fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
118 #interrupt-cells = <1>;
120 #address-cells = <3>;
122 interrupts = <16 2 1 13>;
123 interrupt-map-mask = <0xf800 0 0 7>;
126 0000 0 0 1 &mpic 42 1 0 0
127 0000 0 0 2 &mpic 9 1 0 0
128 0000 0 0 3 &mpic 10 1 0 0
129 0000 0 0 4 &mpic 11 1 0 0
134 /* controller at 0x203000 */
136 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
139 #address-cells = <3>;
140 bus-range = <0x0 0xff>;
141 clock-frequency = <33333333>;
142 interrupts = <16 2 1 12>;
143 fsl,iommu-parent = <&pamu0>;
144 fsl,liodn-reg = <&guts 0x50c>; /* PEX4LIODNR */
147 #interrupt-cells = <1>;
149 #address-cells = <3>;
151 interrupts = <16 2 1 12>;
152 interrupt-map-mask = <0xf800 0 0 7>;
155 0000 0 0 1 &mpic 43 1 0 0
156 0000 0 0 2 &mpic 0 1 0 0
157 0000 0 0 3 &mpic 4 1 0 0
158 0000 0 0 4 &mpic 8 1 0 0
164 compatible = "fsl,srio";
165 interrupts = <16 2 1 11>;
166 #address-cells = <2>;
168 fsl,iommu-parent = <&pamu0>;
172 #address-cells = <2>;
175 fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
179 #address-cells = <2>;
182 fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
187 #address-cells = <1>;
189 compatible = "fsl,dcsr", "simple-bus";
192 compatible = "fsl,p5020-dcsr-epu", "fsl,dcsr-epu";
193 interrupts = <52 2 0 0
199 compatible = "fsl,dcsr-npc";
200 reg = <0x1000 0x1000 0x1000000 0x8000>;
203 compatible = "fsl,dcsr-nxc";
204 reg = <0x2000 0x1000>;
207 compatible = "fsl,dcsr-corenet";
208 reg = <0x8000 0x1000 0xB0000 0x1000>;
211 compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
212 reg = <0x9000 0x1000>;
215 compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
216 reg = <0x11000 0x1000>;
219 compatible = "fsl,dcsr-ddr";
220 dev-handle = <&ddr1>;
221 reg = <0x12000 0x1000>;
224 compatible = "fsl,dcsr-ddr";
225 dev-handle = <&ddr2>;
226 reg = <0x13000 0x1000>;
229 compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
230 reg = <0x18000 0x1000>;
233 compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
234 reg = <0x22000 0x1000>;
236 dcsr-cpu-sb-proxy@40000 {
237 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
238 cpu-handle = <&cpu0>;
239 reg = <0x40000 0x1000>;
241 dcsr-cpu-sb-proxy@41000 {
242 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
243 cpu-handle = <&cpu1>;
244 reg = <0x41000 0x1000>;
248 /include/ "qoriq-bman1-portals.dtsi"
251 #address-cells = <1>;
254 compatible = "simple-bus";
257 compatible = "fsl,soc-sram-error";
258 interrupts = <16 2 1 29>;
262 compatible = "fsl,corenet-law";
267 ddr1: memory-controller@8000 {
268 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
269 reg = <0x8000 0x1000>;
270 interrupts = <16 2 1 23>;
273 ddr2: memory-controller@9000 {
274 compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
275 reg = <0x9000 0x1000>;
276 interrupts = <16 2 1 22>;
279 cpc: l3-cache-controller@10000 {
280 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
281 reg = <0x10000 0x1000
283 interrupts = <16 2 1 27
288 compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
289 reg = <0x18000 0x1000>;
290 interrupts = <16 2 1 31>;
291 fsl,ccf-num-csdids = <32>;
292 fsl,ccf-num-snoopids = <32>;
296 compatible = "fsl,pamu-v1.0", "fsl,pamu";
297 reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */
298 ranges = <0 0x20000 0x4000>;
299 #address-cells = <1>;
304 fsl,portid-mapping = <0x3c000000>;
308 fsl,primary-cache-geometry = <32 1>;
309 fsl,secondary-cache-geometry = <128 2>;
313 reg = <0x1000 0x1000>;
314 fsl,primary-cache-geometry = <32 1>;
315 fsl,secondary-cache-geometry = <128 2>;
319 reg = <0x2000 0x1000>;
320 fsl,primary-cache-geometry = <32 1>;
321 fsl,secondary-cache-geometry = <128 2>;
325 reg = <0x3000 0x1000>;
326 fsl,primary-cache-geometry = <32 1>;
327 fsl,secondary-cache-geometry = <128 2>;
331 /include/ "qoriq-mpic.dtsi"
333 guts: global-utilities@e0000 {
334 compatible = "fsl,qoriq-device-config-1.0";
335 reg = <0xe0000 0xe00>;
338 fsl,liodn-bits = <12>;
341 pins: global-utilities@e0e00 {
342 compatible = "fsl,qoriq-pin-control-1.0";
343 reg = <0xe0e00 0x200>;
347 /include/ "qoriq-clockgen1.dtsi"
348 global-utilities@e1000 {
349 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
352 rcpm: global-utilities@e2000 {
353 compatible = "fsl,qoriq-rcpm-1.0";
354 reg = <0xe2000 0x1000>;
359 compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
360 reg = <0xe8000 0x1000>;
363 serdes: serdes@ea000 {
364 compatible = "fsl,p5020-serdes";
365 reg = <0xea000 0x1000>;
368 /include/ "qoriq-dma-0.dtsi"
370 fsl,iommu-parent = <&pamu0>;
371 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
374 /include/ "qoriq-dma-1.dtsi"
376 fsl,iommu-parent = <&pamu0>;
377 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
380 /include/ "qoriq-espi-0.dtsi"
382 fsl,espi-num-chipselects = <4>;
385 /include/ "qoriq-esdhc-0.dtsi"
387 fsl,iommu-parent = <&pamu1>;
388 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
392 /include/ "qoriq-i2c-0.dtsi"
393 /include/ "qoriq-i2c-1.dtsi"
394 /include/ "qoriq-duart-0.dtsi"
395 /include/ "qoriq-duart-1.dtsi"
396 /include/ "qoriq-gpio-0.dtsi"
397 /include/ "qoriq-usb2-mph-0.dtsi"
399 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
400 fsl,iommu-parent = <&pamu1>;
401 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
406 /include/ "qoriq-usb2-dr-0.dtsi"
408 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
409 fsl,iommu-parent = <&pamu1>;
410 fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
415 /include/ "qoriq-sata2-0.dtsi"
417 fsl,iommu-parent = <&pamu1>;
418 fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
421 /include/ "qoriq-sata2-1.dtsi"
423 fsl,iommu-parent = <&pamu1>;
424 fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
426 /include/ "qoriq-sec4.2-0.dtsi"
428 fsl,iommu-parent = <&pamu1>;
431 /include/ "qoriq-bman1.dtsi"
433 /include/ "qoriq-raid1.0-0.dtsi"
435 fsl,iommu-parent = <&pamu1>;