2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
42 #include <asm/branch.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
48 #include <asm/cpu-info.h>
49 #include <asm/processor.h>
50 #include <asm/fpu_emulator.h>
52 #include <asm/mips-r2-to-r6-emul.h>
56 /* Function which emulates a floating point instruction. */
58 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
61 static int fpux_emu(struct pt_regs *,
62 struct mips_fpu_struct *, mips_instruction, void *__user *);
64 /* Control registers */
66 #define FPCREG_RID 0 /* $0 = revision id */
67 #define FPCREG_FCCR 25 /* $25 = fccr */
68 #define FPCREG_FEXR 26 /* $26 = fexr */
69 #define FPCREG_FENR 28 /* $28 = fenr */
70 #define FPCREG_CSR 31 /* $31 = csr */
72 /* convert condition code register number to csr bit */
73 const unsigned int fpucondbit[8] = {
84 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
85 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
86 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
87 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
88 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
91 * This functions translates a 32-bit microMIPS instruction
92 * into a 32-bit MIPS32 instruction. Returns 0 on success
93 * and SIGILL otherwise.
95 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
97 union mips_instruction insn = *insn_ptr;
98 union mips_instruction mips32_insn = insn;
101 switch (insn.mm_i_format.opcode) {
103 mips32_insn.mm_i_format.opcode = ldc1_op;
104 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
105 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
108 mips32_insn.mm_i_format.opcode = lwc1_op;
109 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
110 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
113 mips32_insn.mm_i_format.opcode = sdc1_op;
114 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
115 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
118 mips32_insn.mm_i_format.opcode = swc1_op;
119 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
120 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
123 /* NOTE: offset is << by 1 if in microMIPS mode. */
124 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
125 (insn.mm_i_format.rt == mm_bc1t_op)) {
126 mips32_insn.fb_format.opcode = cop1_op;
127 mips32_insn.fb_format.bc = bc_op;
128 mips32_insn.fb_format.flag =
129 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
134 switch (insn.mm_fp0_format.func) {
143 op = insn.mm_fp0_format.func;
144 if (op == mm_32f_01_op)
146 else if (op == mm_32f_11_op)
148 else if (op == mm_32f_02_op)
150 else if (op == mm_32f_12_op)
152 else if (op == mm_32f_41_op)
154 else if (op == mm_32f_51_op)
156 else if (op == mm_32f_42_op)
160 mips32_insn.fp6_format.opcode = cop1x_op;
161 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
162 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
163 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
164 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
165 mips32_insn.fp6_format.func = func;
168 func = -1; /* Invalid */
169 op = insn.mm_fp5_format.op & 0x7;
170 if (op == mm_ldxc1_op)
172 else if (op == mm_sdxc1_op)
174 else if (op == mm_lwxc1_op)
176 else if (op == mm_swxc1_op)
180 mips32_insn.r_format.opcode = cop1x_op;
181 mips32_insn.r_format.rs =
182 insn.mm_fp5_format.base;
183 mips32_insn.r_format.rt =
184 insn.mm_fp5_format.index;
185 mips32_insn.r_format.rd = 0;
186 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
187 mips32_insn.r_format.func = func;
192 op = -1; /* Invalid */
193 if (insn.mm_fp2_format.op == mm_fmovt_op)
195 else if (insn.mm_fp2_format.op == mm_fmovf_op)
198 mips32_insn.fp0_format.opcode = cop1_op;
199 mips32_insn.fp0_format.fmt =
200 sdps_format[insn.mm_fp2_format.fmt];
201 mips32_insn.fp0_format.ft =
202 (insn.mm_fp2_format.cc<<2) + op;
203 mips32_insn.fp0_format.fs =
204 insn.mm_fp2_format.fs;
205 mips32_insn.fp0_format.fd =
206 insn.mm_fp2_format.fd;
207 mips32_insn.fp0_format.func = fmovc_op;
212 func = -1; /* Invalid */
213 if (insn.mm_fp0_format.op == mm_fadd_op)
215 else if (insn.mm_fp0_format.op == mm_fsub_op)
217 else if (insn.mm_fp0_format.op == mm_fmul_op)
219 else if (insn.mm_fp0_format.op == mm_fdiv_op)
222 mips32_insn.fp0_format.opcode = cop1_op;
223 mips32_insn.fp0_format.fmt =
224 sdps_format[insn.mm_fp0_format.fmt];
225 mips32_insn.fp0_format.ft =
226 insn.mm_fp0_format.ft;
227 mips32_insn.fp0_format.fs =
228 insn.mm_fp0_format.fs;
229 mips32_insn.fp0_format.fd =
230 insn.mm_fp0_format.fd;
231 mips32_insn.fp0_format.func = func;
236 func = -1; /* Invalid */
237 if (insn.mm_fp0_format.op == mm_fmovn_op)
239 else if (insn.mm_fp0_format.op == mm_fmovz_op)
242 mips32_insn.fp0_format.opcode = cop1_op;
243 mips32_insn.fp0_format.fmt =
244 sdps_format[insn.mm_fp0_format.fmt];
245 mips32_insn.fp0_format.ft =
246 insn.mm_fp0_format.ft;
247 mips32_insn.fp0_format.fs =
248 insn.mm_fp0_format.fs;
249 mips32_insn.fp0_format.fd =
250 insn.mm_fp0_format.fd;
251 mips32_insn.fp0_format.func = func;
255 case mm_32f_73_op: /* POOL32FXF */
256 switch (insn.mm_fp1_format.op) {
261 if ((insn.mm_fp1_format.op & 0x7f) ==
266 mips32_insn.r_format.opcode = spec_op;
267 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
268 mips32_insn.r_format.rt =
269 (insn.mm_fp4_format.cc << 2) + op;
270 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
271 mips32_insn.r_format.re = 0;
272 mips32_insn.r_format.func = movc_op;
278 if ((insn.mm_fp1_format.op & 0x7f) ==
281 fmt = swl_format[insn.mm_fp3_format.fmt];
284 fmt = dwl_format[insn.mm_fp3_format.fmt];
286 mips32_insn.fp0_format.opcode = cop1_op;
287 mips32_insn.fp0_format.fmt = fmt;
288 mips32_insn.fp0_format.ft = 0;
289 mips32_insn.fp0_format.fs =
290 insn.mm_fp3_format.fs;
291 mips32_insn.fp0_format.fd =
292 insn.mm_fp3_format.rt;
293 mips32_insn.fp0_format.func = func;
301 if ((insn.mm_fp1_format.op & 0x7f) ==
304 else if ((insn.mm_fp1_format.op & 0x7f) ==
309 mips32_insn.fp0_format.opcode = cop1_op;
310 mips32_insn.fp0_format.fmt =
311 sdps_format[insn.mm_fp3_format.fmt];
312 mips32_insn.fp0_format.ft = 0;
313 mips32_insn.fp0_format.fs =
314 insn.mm_fp3_format.fs;
315 mips32_insn.fp0_format.fd =
316 insn.mm_fp3_format.rt;
317 mips32_insn.fp0_format.func = func;
329 if (insn.mm_fp1_format.op == mm_ffloorl_op)
331 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
333 else if (insn.mm_fp1_format.op == mm_fceill_op)
335 else if (insn.mm_fp1_format.op == mm_fceilw_op)
337 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
339 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
341 else if (insn.mm_fp1_format.op == mm_froundl_op)
343 else if (insn.mm_fp1_format.op == mm_froundw_op)
345 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
349 mips32_insn.fp0_format.opcode = cop1_op;
350 mips32_insn.fp0_format.fmt =
351 sd_format[insn.mm_fp1_format.fmt];
352 mips32_insn.fp0_format.ft = 0;
353 mips32_insn.fp0_format.fs =
354 insn.mm_fp1_format.fs;
355 mips32_insn.fp0_format.fd =
356 insn.mm_fp1_format.rt;
357 mips32_insn.fp0_format.func = func;
362 if (insn.mm_fp1_format.op == mm_frsqrt_op)
364 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
368 mips32_insn.fp0_format.opcode = cop1_op;
369 mips32_insn.fp0_format.fmt =
370 sdps_format[insn.mm_fp1_format.fmt];
371 mips32_insn.fp0_format.ft = 0;
372 mips32_insn.fp0_format.fs =
373 insn.mm_fp1_format.fs;
374 mips32_insn.fp0_format.fd =
375 insn.mm_fp1_format.rt;
376 mips32_insn.fp0_format.func = func;
384 if (insn.mm_fp1_format.op == mm_mfc1_op)
386 else if (insn.mm_fp1_format.op == mm_mtc1_op)
388 else if (insn.mm_fp1_format.op == mm_cfc1_op)
390 else if (insn.mm_fp1_format.op == mm_ctc1_op)
392 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
396 mips32_insn.fp1_format.opcode = cop1_op;
397 mips32_insn.fp1_format.op = op;
398 mips32_insn.fp1_format.rt =
399 insn.mm_fp1_format.rt;
400 mips32_insn.fp1_format.fs =
401 insn.mm_fp1_format.fs;
402 mips32_insn.fp1_format.fd = 0;
403 mips32_insn.fp1_format.func = 0;
409 case mm_32f_74_op: /* c.cond.fmt */
410 mips32_insn.fp0_format.opcode = cop1_op;
411 mips32_insn.fp0_format.fmt =
412 sdps_format[insn.mm_fp4_format.fmt];
413 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
414 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
415 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
416 mips32_insn.fp0_format.func =
417 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
427 *insn_ptr = mips32_insn;
432 * Redundant with logic already in kernel/branch.c,
433 * embedded in compute_return_epc. At some point,
434 * a single subroutine should be used across both
437 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
438 unsigned long *contpc)
440 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
442 unsigned int bit = 0;
444 switch (insn.i_format.opcode) {
446 switch (insn.r_format.func) {
448 if (insn.r_format.rd != 0) {
449 regs->regs[insn.r_format.rd] =
450 regs->cp0_epc + dec_insn.pc_inc +
451 dec_insn.next_pc_inc;
455 /* For R6, JR already emulated in jalr_op */
456 if (NO_R6EMU && insn.r_format.func == jr_op)
458 *contpc = regs->regs[insn.r_format.rs];
463 switch (insn.i_format.rt) {
466 if (NO_R6EMU && (insn.i_format.rs ||
467 insn.i_format.rt == bltzall_op))
470 regs->regs[31] = regs->cp0_epc +
472 dec_insn.next_pc_inc;
478 if ((long)regs->regs[insn.i_format.rs] < 0)
479 *contpc = regs->cp0_epc +
481 (insn.i_format.simmediate << 2);
483 *contpc = regs->cp0_epc +
485 dec_insn.next_pc_inc;
489 if (NO_R6EMU && (insn.i_format.rs ||
490 insn.i_format.rt == bgezall_op))
493 regs->regs[31] = regs->cp0_epc +
495 dec_insn.next_pc_inc;
501 if ((long)regs->regs[insn.i_format.rs] >= 0)
502 *contpc = regs->cp0_epc +
504 (insn.i_format.simmediate << 2);
506 *contpc = regs->cp0_epc +
508 dec_insn.next_pc_inc;
515 regs->regs[31] = regs->cp0_epc +
517 dec_insn.next_pc_inc;
520 *contpc = regs->cp0_epc + dec_insn.pc_inc;
523 *contpc |= (insn.j_format.target << 2);
524 /* Set microMIPS mode bit: XOR for jalx. */
531 if (regs->regs[insn.i_format.rs] ==
532 regs->regs[insn.i_format.rt])
533 *contpc = regs->cp0_epc +
535 (insn.i_format.simmediate << 2);
537 *contpc = regs->cp0_epc +
539 dec_insn.next_pc_inc;
545 if (regs->regs[insn.i_format.rs] !=
546 regs->regs[insn.i_format.rt])
547 *contpc = regs->cp0_epc +
549 (insn.i_format.simmediate << 2);
551 *contpc = regs->cp0_epc +
553 dec_insn.next_pc_inc;
556 if (!insn.i_format.rt && NO_R6EMU)
561 * Compact branches for R6 for the
562 * blez and blezl opcodes.
563 * BLEZ | rs = 0 | rt != 0 == BLEZALC
564 * BLEZ | rs = rt != 0 == BGEZALC
565 * BLEZ | rs != 0 | rt != 0 == BGEUC
566 * BLEZL | rs = 0 | rt != 0 == BLEZC
567 * BLEZL | rs = rt != 0 == BGEZC
568 * BLEZL | rs != 0 | rt != 0 == BGEC
570 * For real BLEZ{,L}, rt is always 0.
572 if (cpu_has_mips_r6 && insn.i_format.rt) {
573 if ((insn.i_format.opcode == blez_op) &&
574 ((!insn.i_format.rs && insn.i_format.rt) ||
575 (insn.i_format.rs == insn.i_format.rt)))
576 regs->regs[31] = regs->cp0_epc +
578 *contpc = regs->cp0_epc + dec_insn.pc_inc +
579 dec_insn.next_pc_inc;
583 if ((long)regs->regs[insn.i_format.rs] <= 0)
584 *contpc = regs->cp0_epc +
586 (insn.i_format.simmediate << 2);
588 *contpc = regs->cp0_epc +
590 dec_insn.next_pc_inc;
593 if (!insn.i_format.rt && NO_R6EMU)
597 * Compact branches for R6 for the
598 * bgtz and bgtzl opcodes.
599 * BGTZ | rs = 0 | rt != 0 == BGTZALC
600 * BGTZ | rs = rt != 0 == BLTZALC
601 * BGTZ | rs != 0 | rt != 0 == BLTUC
602 * BGTZL | rs = 0 | rt != 0 == BGTZC
603 * BGTZL | rs = rt != 0 == BLTZC
604 * BGTZL | rs != 0 | rt != 0 == BLTC
606 * *ZALC varint for BGTZ &&& rt != 0
607 * For real GTZ{,L}, rt is always 0.
609 if (cpu_has_mips_r6 && insn.i_format.rt) {
610 if ((insn.i_format.opcode == blez_op) &&
611 ((!insn.i_format.rs && insn.i_format.rt) ||
612 (insn.i_format.rs == insn.i_format.rt)))
613 regs->regs[31] = regs->cp0_epc +
615 *contpc = regs->cp0_epc + dec_insn.pc_inc +
616 dec_insn.next_pc_inc;
621 if ((long)regs->regs[insn.i_format.rs] > 0)
622 *contpc = regs->cp0_epc +
624 (insn.i_format.simmediate << 2);
626 *contpc = regs->cp0_epc +
628 dec_insn.next_pc_inc;
632 if (!cpu_has_mips_r6)
634 if (insn.i_format.rt && !insn.i_format.rs)
635 regs->regs[31] = regs->cp0_epc + 4;
636 *contpc = regs->cp0_epc + dec_insn.pc_inc +
637 dec_insn.next_pc_inc;
640 #ifdef CONFIG_CPU_CAVIUM_OCTEON
641 case lwc2_op: /* This is bbit0 on Octeon */
642 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
643 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
645 *contpc = regs->cp0_epc + 8;
647 case ldc2_op: /* This is bbit032 on Octeon */
648 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
649 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
651 *contpc = regs->cp0_epc + 8;
653 case swc2_op: /* This is bbit1 on Octeon */
654 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
655 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
657 *contpc = regs->cp0_epc + 8;
659 case sdc2_op: /* This is bbit132 on Octeon */
660 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
661 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
663 *contpc = regs->cp0_epc + 8;
668 * Only valid for MIPS R6 but we can still end up
669 * here from a broken userland so just tell emulator
670 * this is not a branch and let it break later on.
672 if (!cpu_has_mips_r6)
674 *contpc = regs->cp0_epc + dec_insn.pc_inc +
675 dec_insn.next_pc_inc;
679 if (!cpu_has_mips_r6)
681 regs->regs[31] = regs->cp0_epc + 4;
682 *contpc = regs->cp0_epc + dec_insn.pc_inc +
683 dec_insn.next_pc_inc;
687 if (!cpu_has_mips_r6)
689 *contpc = regs->cp0_epc + dec_insn.pc_inc +
690 dec_insn.next_pc_inc;
694 if (!cpu_has_mips_r6)
696 if (!insn.i_format.rs)
697 regs->regs[31] = regs->cp0_epc + 4;
698 *contpc = regs->cp0_epc + dec_insn.pc_inc +
699 dec_insn.next_pc_inc;
705 /* Need to check for R6 bc1nez and bc1eqz branches */
706 if (cpu_has_mips_r6 &&
707 ((insn.i_format.rs == bc1eqz_op) ||
708 (insn.i_format.rs == bc1nez_op))) {
710 switch (insn.i_format.rs) {
712 if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
716 if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
721 *contpc = regs->cp0_epc +
723 (insn.i_format.simmediate << 2);
725 *contpc = regs->cp0_epc +
727 dec_insn.next_pc_inc;
731 /* R2/R6 compatible cop1 instruction. Fall through */
734 if (insn.i_format.rs == bc_op) {
737 fcr31 = read_32bit_cp1_register(CP1_STATUS);
739 fcr31 = current->thread.fpu.fcr31;
742 bit = (insn.i_format.rt >> 2);
745 switch (insn.i_format.rt & 3) {
748 if (~fcr31 & (1 << bit))
749 *contpc = regs->cp0_epc +
751 (insn.i_format.simmediate << 2);
753 *contpc = regs->cp0_epc +
755 dec_insn.next_pc_inc;
759 if (fcr31 & (1 << bit))
760 *contpc = regs->cp0_epc +
762 (insn.i_format.simmediate << 2);
764 *contpc = regs->cp0_epc +
766 dec_insn.next_pc_inc;
776 * In the Linux kernel, we support selection of FPR format on the
777 * basis of the Status.FR bit. If an FPU is not present, the FR bit
778 * is hardwired to zero, which would imply a 32-bit FPU even for
779 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
780 * FPU emu is slow and bulky and optimizing this function offers fairly
781 * sizeable benefits so we try to be clever and make this function return
782 * a constant whenever possible, that is on 64-bit kernels without O32
783 * compatibility enabled and on 32-bit without 64-bit FPU support.
785 static inline int cop1_64bit(struct pt_regs *xcp)
787 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
789 else if (config_enabled(CONFIG_32BIT) &&
790 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
793 return !test_thread_flag(TIF_32BIT_FPREGS);
796 static inline bool hybrid_fprs(void)
798 return test_thread_flag(TIF_HYBRID_FPREGS);
801 #define SIFROMREG(si, x) \
803 if (cop1_64bit(xcp) && !hybrid_fprs()) \
804 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
806 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
809 #define SITOREG(si, x) \
811 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
813 set_fpr32(&ctx->fpr[x], 0, si); \
814 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
815 set_fpr32(&ctx->fpr[x], i, 0); \
817 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
821 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
823 #define SITOHREG(si, x) \
826 set_fpr32(&ctx->fpr[x], 1, si); \
827 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
828 set_fpr32(&ctx->fpr[x], i, 0); \
831 #define DIFROMREG(di, x) \
832 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
834 #define DITOREG(di, x) \
837 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
838 set_fpr64(&ctx->fpr[fpr], 0, di); \
839 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
840 set_fpr64(&ctx->fpr[fpr], i, 0); \
843 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
844 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
845 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
846 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
849 * Emulate a CFC1 instruction.
851 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
854 u32 fcr31 = ctx->fcr31;
857 switch (MIPSInst_RD(ir)) {
860 pr_debug("%p gpr[%d]<-csr=%08x\n",
861 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
867 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
869 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
870 pr_debug("%p gpr[%d]<-enr=%08x\n",
871 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
877 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
878 pr_debug("%p gpr[%d]<-exr=%08x\n",
879 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
885 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
887 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
888 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
889 pr_debug("%p gpr[%d]<-ccr=%08x\n",
890 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
894 value = boot_cpu_data.fpu_id;
902 xcp->regs[MIPSInst_RT(ir)] = value;
906 * Emulate a CTC1 instruction.
908 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
911 u32 fcr31 = ctx->fcr31;
915 if (MIPSInst_RT(ir) == 0)
918 value = xcp->regs[MIPSInst_RT(ir)];
920 switch (MIPSInst_RD(ir)) {
922 pr_debug("%p gpr[%d]->csr=%08x\n",
923 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
925 /* Preserve read-only bits. */
926 mask = boot_cpu_data.fpu_msk31;
927 fcr31 = (value & ~mask) | (fcr31 & mask);
933 pr_debug("%p gpr[%d]->enr=%08x\n",
934 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
935 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
936 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
938 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
944 pr_debug("%p gpr[%d]->exr=%08x\n",
945 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
946 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
947 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
953 pr_debug("%p gpr[%d]->ccr=%08x\n",
954 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
955 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
956 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
958 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
970 * Emulate the single floating point instruction pointed at by EPC.
971 * Two instructions if the instruction is in a branch delay slot.
974 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
975 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
977 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
978 unsigned int cond, cbit;
988 * These are giving gcc a gentle hint about what to expect in
989 * dec_inst in order to do better optimization.
991 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
994 /* XXX NEC Vr54xx bug workaround */
995 if (delay_slot(xcp)) {
996 if (dec_insn.micro_mips_mode) {
997 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
998 clear_delay_slot(xcp);
1000 if (!isBranchInstr(xcp, dec_insn, &contpc))
1001 clear_delay_slot(xcp);
1005 if (delay_slot(xcp)) {
1007 * The instruction to be emulated is in a branch delay slot
1008 * which means that we have to emulate the branch instruction
1009 * BEFORE we do the cop1 instruction.
1011 * This branch could be a COP1 branch, but in that case we
1012 * would have had a trap for that instruction, and would not
1013 * come through this route.
1015 * Linux MIPS branch emulator operates on context, updating the
1018 ir = dec_insn.next_insn; /* process delay slot instr */
1019 pc_inc = dec_insn.next_pc_inc;
1021 ir = dec_insn.insn; /* process current instr */
1022 pc_inc = dec_insn.pc_inc;
1026 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1027 * instructions, we want to convert microMIPS FPU instructions
1028 * into MIPS32 instructions so that we could reuse all of the
1029 * FPU emulation code.
1031 * NOTE: We cannot do this for branch instructions since they
1032 * are not a subset. Example: Cannot emulate a 16-bit
1033 * aligned target address with a MIPS32 instruction.
1035 if (dec_insn.micro_mips_mode) {
1037 * If next instruction is a 16-bit instruction, then it
1038 * it cannot be a FPU instruction. This could happen
1039 * since we can be called for non-FPU instructions.
1041 if ((pc_inc == 2) ||
1042 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1048 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1049 MIPS_FPU_EMU_INC_STATS(emulated);
1050 switch (MIPSInst_OPCODE(ir)) {
1052 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1054 MIPS_FPU_EMU_INC_STATS(loads);
1056 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1057 MIPS_FPU_EMU_INC_STATS(errors);
1061 if (__get_user(dval, dva)) {
1062 MIPS_FPU_EMU_INC_STATS(errors);
1066 DITOREG(dval, MIPSInst_RT(ir));
1070 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1072 MIPS_FPU_EMU_INC_STATS(stores);
1073 DIFROMREG(dval, MIPSInst_RT(ir));
1074 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1075 MIPS_FPU_EMU_INC_STATS(errors);
1079 if (__put_user(dval, dva)) {
1080 MIPS_FPU_EMU_INC_STATS(errors);
1087 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1089 MIPS_FPU_EMU_INC_STATS(loads);
1090 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1091 MIPS_FPU_EMU_INC_STATS(errors);
1095 if (__get_user(wval, wva)) {
1096 MIPS_FPU_EMU_INC_STATS(errors);
1100 SITOREG(wval, MIPSInst_RT(ir));
1104 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1106 MIPS_FPU_EMU_INC_STATS(stores);
1107 SIFROMREG(wval, MIPSInst_RT(ir));
1108 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1109 MIPS_FPU_EMU_INC_STATS(errors);
1113 if (__put_user(wval, wva)) {
1114 MIPS_FPU_EMU_INC_STATS(errors);
1121 switch (MIPSInst_RS(ir)) {
1123 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1126 /* copregister fs -> gpr[rt] */
1127 if (MIPSInst_RT(ir) != 0) {
1128 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1134 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1137 /* copregister fs <- rt */
1138 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1142 if (!cpu_has_mips_r2_r6)
1145 /* copregister rd -> gpr[rt] */
1146 if (MIPSInst_RT(ir) != 0) {
1147 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1153 if (!cpu_has_mips_r2_r6)
1156 /* copregister rd <- gpr[rt] */
1157 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1161 /* copregister rd -> gpr[rt] */
1162 if (MIPSInst_RT(ir) != 0) {
1163 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1169 /* copregister rd <- rt */
1170 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1174 /* cop control register rd -> gpr[rt] */
1175 cop1_cfc(xcp, ctx, ir);
1179 /* copregister rd <- rt */
1180 cop1_ctc(xcp, ctx, ir);
1181 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1188 if (!cpu_has_mips_r6 || delay_slot(xcp))
1192 switch (MIPSInst_RS(ir)) {
1194 if (get_fpr32(¤t->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1)
1198 if (!(get_fpr32(¤t->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1))
1205 if (delay_slot(xcp))
1208 if (cpu_has_mips_4_5_r)
1209 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1211 cbit = FPU_CSR_COND;
1212 cond = ctx->fcr31 & cbit;
1215 switch (MIPSInst_RT(ir) & 3) {
1217 if (cpu_has_mips_2_3_4_5_r)
1224 if (cpu_has_mips_2_3_4_5_r)
1231 set_delay_slot(xcp);
1234 * Branch taken: emulate dslot instruction
1239 * Remember EPC at the branch to point back
1240 * at so that any delay-slot instruction
1241 * signal is not silently ignored.
1243 bcpc = xcp->cp0_epc;
1244 xcp->cp0_epc += dec_insn.pc_inc;
1246 contpc = MIPSInst_SIMM(ir);
1247 ir = dec_insn.next_insn;
1248 if (dec_insn.micro_mips_mode) {
1249 contpc = (xcp->cp0_epc + (contpc << 1));
1251 /* If 16-bit instruction, not FPU. */
1252 if ((dec_insn.next_pc_inc == 2) ||
1253 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1256 * Since this instruction will
1257 * be put on the stack with
1258 * 32-bit words, get around
1259 * this problem by putting a
1260 * NOP16 as the second one.
1262 if (dec_insn.next_pc_inc == 2)
1263 ir = (ir & (~0xffff)) | MM_NOP16;
1266 * Single step the non-CP1
1267 * instruction in the dslot.
1269 sig = mips_dsemul(xcp, ir,
1272 xcp->cp0_epc = bcpc;
1274 * SIGILL forces out of
1275 * the emulation loop.
1277 return sig ? sig : SIGILL;
1280 contpc = (xcp->cp0_epc + (contpc << 2));
1282 switch (MIPSInst_OPCODE(ir)) {
1289 if (cpu_has_mips_2_3_4_5_r)
1298 if (cpu_has_mips_4_5_64_r2_r6)
1299 /* its one of ours */
1305 switch (MIPSInst_FUNC(ir)) {
1307 if (cpu_has_mips_4_5_r)
1315 xcp->cp0_epc = bcpc;
1320 * Single step the non-cp1
1321 * instruction in the dslot
1323 sig = mips_dsemul(xcp, ir, contpc);
1325 xcp->cp0_epc = bcpc;
1326 /* SIGILL forces out of the emulation loop. */
1327 return sig ? sig : SIGILL;
1328 } else if (likely) { /* branch not taken */
1330 * branch likely nullifies
1331 * dslot if not taken
1333 xcp->cp0_epc += dec_insn.pc_inc;
1334 contpc += dec_insn.pc_inc;
1336 * else continue & execute
1337 * dslot as normal insn
1343 if (!(MIPSInst_RS(ir) & 0x10))
1346 /* a real fpu computation instruction */
1347 if ((sig = fpu_emu(xcp, ctx, ir)))
1353 if (!cpu_has_mips_4_5_64_r2_r6)
1356 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1362 if (!cpu_has_mips_4_5_r)
1365 if (MIPSInst_FUNC(ir) != movc_op)
1367 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1368 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1369 xcp->regs[MIPSInst_RD(ir)] =
1370 xcp->regs[MIPSInst_RS(ir)];
1378 xcp->cp0_epc = contpc;
1379 clear_delay_slot(xcp);
1385 * Conversion table from MIPS compare ops 48-63
1386 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1388 static const unsigned char cmptab[8] = {
1389 0, /* cmp_0 (sig) cmp_sf */
1390 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1391 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1392 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1393 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1394 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1395 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1396 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1399 static const unsigned char negative_cmptab[8] = {
1401 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1402 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1403 IEEE754_CLT | IEEE754_CGT,
1409 * Additional MIPS4 instructions
1412 #define DEF3OP(name, p, f1, f2, f3) \
1413 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1414 union ieee754##p s, union ieee754##p t) \
1416 struct _ieee754_csr ieee754_csr_save; \
1418 ieee754_csr_save = ieee754_csr; \
1420 ieee754_csr_save.cx |= ieee754_csr.cx; \
1421 ieee754_csr_save.sx |= ieee754_csr.sx; \
1423 ieee754_csr.cx |= ieee754_csr_save.cx; \
1424 ieee754_csr.sx |= ieee754_csr_save.sx; \
1428 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1430 return ieee754dp_div(ieee754dp_one(0), d);
1433 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1435 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1438 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1440 return ieee754sp_div(ieee754sp_one(0), s);
1443 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1445 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1448 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1449 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1450 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1451 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1452 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1453 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1454 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1455 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1457 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1458 mips_instruction ir, void *__user *fault_addr)
1460 unsigned rcsr = 0; /* resulting csr */
1462 MIPS_FPU_EMU_INC_STATS(cp1xops);
1464 switch (MIPSInst_FMA_FFMT(ir)) {
1465 case s_fmt:{ /* 0 */
1467 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1468 union ieee754sp fd, fr, fs, ft;
1472 switch (MIPSInst_FUNC(ir)) {
1474 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1475 xcp->regs[MIPSInst_FT(ir)]);
1477 MIPS_FPU_EMU_INC_STATS(loads);
1478 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1479 MIPS_FPU_EMU_INC_STATS(errors);
1483 if (__get_user(val, va)) {
1484 MIPS_FPU_EMU_INC_STATS(errors);
1488 SITOREG(val, MIPSInst_FD(ir));
1492 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1493 xcp->regs[MIPSInst_FT(ir)]);
1495 MIPS_FPU_EMU_INC_STATS(stores);
1497 SIFROMREG(val, MIPSInst_FS(ir));
1498 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1499 MIPS_FPU_EMU_INC_STATS(errors);
1503 if (put_user(val, va)) {
1504 MIPS_FPU_EMU_INC_STATS(errors);
1511 handler = fpemu_sp_madd;
1514 handler = fpemu_sp_msub;
1517 handler = fpemu_sp_nmadd;
1520 handler = fpemu_sp_nmsub;
1524 SPFROMREG(fr, MIPSInst_FR(ir));
1525 SPFROMREG(fs, MIPSInst_FS(ir));
1526 SPFROMREG(ft, MIPSInst_FT(ir));
1527 fd = (*handler) (fr, fs, ft);
1528 SPTOREG(fd, MIPSInst_FD(ir));
1531 if (ieee754_cxtest(IEEE754_INEXACT)) {
1532 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1533 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1535 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1536 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1537 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1539 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1540 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1541 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1543 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1544 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1545 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1548 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1549 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1550 /*printk ("SIGFPE: FPU csr = %08x\n",
1563 case d_fmt:{ /* 1 */
1564 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1565 union ieee754dp fd, fr, fs, ft;
1569 switch (MIPSInst_FUNC(ir)) {
1571 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1572 xcp->regs[MIPSInst_FT(ir)]);
1574 MIPS_FPU_EMU_INC_STATS(loads);
1575 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1576 MIPS_FPU_EMU_INC_STATS(errors);
1580 if (__get_user(val, va)) {
1581 MIPS_FPU_EMU_INC_STATS(errors);
1585 DITOREG(val, MIPSInst_FD(ir));
1589 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1590 xcp->regs[MIPSInst_FT(ir)]);
1592 MIPS_FPU_EMU_INC_STATS(stores);
1593 DIFROMREG(val, MIPSInst_FS(ir));
1594 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1595 MIPS_FPU_EMU_INC_STATS(errors);
1599 if (__put_user(val, va)) {
1600 MIPS_FPU_EMU_INC_STATS(errors);
1607 handler = fpemu_dp_madd;
1610 handler = fpemu_dp_msub;
1613 handler = fpemu_dp_nmadd;
1616 handler = fpemu_dp_nmsub;
1620 DPFROMREG(fr, MIPSInst_FR(ir));
1621 DPFROMREG(fs, MIPSInst_FS(ir));
1622 DPFROMREG(ft, MIPSInst_FT(ir));
1623 fd = (*handler) (fr, fs, ft);
1624 DPTOREG(fd, MIPSInst_FD(ir));
1634 if (MIPSInst_FUNC(ir) != pfetch_op)
1637 /* ignore prefx operation */
1650 * Emulate a single COP1 arithmetic instruction.
1652 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1653 mips_instruction ir)
1655 int rfmt; /* resulting format */
1656 unsigned rcsr = 0; /* resulting csr */
1665 } rv; /* resulting value */
1668 MIPS_FPU_EMU_INC_STATS(cp1ops);
1669 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1670 case s_fmt: { /* 0 */
1672 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1673 union ieee754sp(*u) (union ieee754sp);
1675 union ieee754sp fs, ft;
1677 switch (MIPSInst_FUNC(ir)) {
1680 handler.b = ieee754sp_add;
1683 handler.b = ieee754sp_sub;
1686 handler.b = ieee754sp_mul;
1689 handler.b = ieee754sp_div;
1694 if (!cpu_has_mips_2_3_4_5_r)
1697 handler.u = ieee754sp_sqrt;
1701 * Note that on some MIPS IV implementations such as the
1702 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1703 * achieve full IEEE-754 accuracy - however this emulator does.
1706 if (!cpu_has_mips_4_5_64_r2_r6)
1709 handler.u = fpemu_sp_rsqrt;
1713 if (!cpu_has_mips_4_5_64_r2_r6)
1716 handler.u = fpemu_sp_recip;
1720 if (!cpu_has_mips_4_5_r)
1723 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1724 if (((ctx->fcr31 & cond) != 0) !=
1725 ((MIPSInst_FT(ir) & 1) != 0))
1727 SPFROMREG(rv.s, MIPSInst_FS(ir));
1731 if (!cpu_has_mips_4_5_r)
1734 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1736 SPFROMREG(rv.s, MIPSInst_FS(ir));
1740 if (!cpu_has_mips_4_5_r)
1743 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1745 SPFROMREG(rv.s, MIPSInst_FS(ir));
1749 if (!cpu_has_mips_r6)
1752 SPFROMREG(rv.s, MIPSInst_FT(ir));
1756 SPFROMREG(rv.s, MIPSInst_FS(ir));
1760 if (!cpu_has_mips_r6)
1763 SPFROMREG(rv.s, MIPSInst_FT(ir));
1765 SPFROMREG(rv.s, MIPSInst_FS(ir));
1771 union ieee754sp ft, fs, fd;
1773 if (!cpu_has_mips_r6)
1776 SPFROMREG(ft, MIPSInst_FT(ir));
1777 SPFROMREG(fs, MIPSInst_FS(ir));
1778 SPFROMREG(fd, MIPSInst_FD(ir));
1779 rv.s = ieee754sp_maddf(fd, fs, ft);
1784 union ieee754sp ft, fs, fd;
1786 if (!cpu_has_mips_r6)
1789 SPFROMREG(ft, MIPSInst_FT(ir));
1790 SPFROMREG(fs, MIPSInst_FS(ir));
1791 SPFROMREG(fd, MIPSInst_FD(ir));
1792 rv.s = ieee754sp_msubf(fd, fs, ft);
1799 if (!cpu_has_mips_r6)
1802 SPFROMREG(fs, MIPSInst_FS(ir));
1803 rv.l = ieee754sp_tlong(fs);
1804 rv.s = ieee754sp_flong(rv.l);
1811 if (!cpu_has_mips_r6)
1814 SPFROMREG(fs, MIPSInst_FS(ir));
1815 rv.w = ieee754sp_2008class(fs);
1821 union ieee754sp fs, ft;
1823 if (!cpu_has_mips_r6)
1826 SPFROMREG(ft, MIPSInst_FT(ir));
1827 SPFROMREG(fs, MIPSInst_FS(ir));
1828 rv.s = ieee754sp_fmin(fs, ft);
1833 union ieee754sp fs, ft;
1835 if (!cpu_has_mips_r6)
1838 SPFROMREG(ft, MIPSInst_FT(ir));
1839 SPFROMREG(fs, MIPSInst_FS(ir));
1840 rv.s = ieee754sp_fmina(fs, ft);
1845 union ieee754sp fs, ft;
1847 if (!cpu_has_mips_r6)
1850 SPFROMREG(ft, MIPSInst_FT(ir));
1851 SPFROMREG(fs, MIPSInst_FS(ir));
1852 rv.s = ieee754sp_fmax(fs, ft);
1857 union ieee754sp fs, ft;
1859 if (!cpu_has_mips_r6)
1862 SPFROMREG(ft, MIPSInst_FT(ir));
1863 SPFROMREG(fs, MIPSInst_FS(ir));
1864 rv.s = ieee754sp_fmaxa(fs, ft);
1869 handler.u = ieee754sp_abs;
1873 handler.u = ieee754sp_neg;
1878 SPFROMREG(rv.s, MIPSInst_FS(ir));
1881 /* binary op on handler */
1883 SPFROMREG(fs, MIPSInst_FS(ir));
1884 SPFROMREG(ft, MIPSInst_FT(ir));
1886 rv.s = (*handler.b) (fs, ft);
1889 SPFROMREG(fs, MIPSInst_FS(ir));
1890 rv.s = (*handler.u) (fs);
1893 if (ieee754_cxtest(IEEE754_INEXACT)) {
1894 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1895 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1897 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1898 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1899 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1901 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1902 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1903 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1905 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1906 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1907 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1909 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1910 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1911 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1915 /* unary conv ops */
1917 return SIGILL; /* not defined */
1920 SPFROMREG(fs, MIPSInst_FS(ir));
1921 rv.d = ieee754dp_fsp(fs);
1926 SPFROMREG(fs, MIPSInst_FS(ir));
1927 rv.w = ieee754sp_tint(fs);
1935 if (!cpu_has_mips_2_3_4_5_r)
1938 oldrm = ieee754_csr.rm;
1939 SPFROMREG(fs, MIPSInst_FS(ir));
1940 ieee754_csr.rm = MIPSInst_FUNC(ir);
1941 rv.w = ieee754sp_tint(fs);
1942 ieee754_csr.rm = oldrm;
1947 if (!cpu_has_mips_3_4_5_64_r2_r6)
1950 SPFROMREG(fs, MIPSInst_FS(ir));
1951 rv.l = ieee754sp_tlong(fs);
1959 if (!cpu_has_mips_3_4_5_64_r2_r6)
1962 oldrm = ieee754_csr.rm;
1963 SPFROMREG(fs, MIPSInst_FS(ir));
1964 ieee754_csr.rm = MIPSInst_FUNC(ir);
1965 rv.l = ieee754sp_tlong(fs);
1966 ieee754_csr.rm = oldrm;
1971 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
1972 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1973 union ieee754sp fs, ft;
1975 SPFROMREG(fs, MIPSInst_FS(ir));
1976 SPFROMREG(ft, MIPSInst_FT(ir));
1977 rv.w = ieee754sp_cmp(fs, ft,
1978 cmptab[cmpop & 0x7], cmpop & 0x8);
1980 if ((cmpop & 0x8) && ieee754_cxtest
1981 (IEEE754_INVALID_OPERATION))
1982 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1994 union ieee754dp fs, ft;
1996 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1997 union ieee754dp(*u) (union ieee754dp);
2000 switch (MIPSInst_FUNC(ir)) {
2003 handler.b = ieee754dp_add;
2006 handler.b = ieee754dp_sub;
2009 handler.b = ieee754dp_mul;
2012 handler.b = ieee754dp_div;
2017 if (!cpu_has_mips_2_3_4_5_r)
2020 handler.u = ieee754dp_sqrt;
2023 * Note that on some MIPS IV implementations such as the
2024 * R5000 and R8000 the FSQRT and FRECIP instructions do not
2025 * achieve full IEEE-754 accuracy - however this emulator does.
2028 if (!cpu_has_mips_4_5_64_r2_r6)
2031 handler.u = fpemu_dp_rsqrt;
2034 if (!cpu_has_mips_4_5_64_r2_r6)
2037 handler.u = fpemu_dp_recip;
2040 if (!cpu_has_mips_4_5_r)
2043 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2044 if (((ctx->fcr31 & cond) != 0) !=
2045 ((MIPSInst_FT(ir) & 1) != 0))
2047 DPFROMREG(rv.d, MIPSInst_FS(ir));
2050 if (!cpu_has_mips_4_5_r)
2053 if (xcp->regs[MIPSInst_FT(ir)] != 0)
2055 DPFROMREG(rv.d, MIPSInst_FS(ir));
2058 if (!cpu_has_mips_4_5_r)
2061 if (xcp->regs[MIPSInst_FT(ir)] == 0)
2063 DPFROMREG(rv.d, MIPSInst_FS(ir));
2067 if (!cpu_has_mips_r6)
2070 DPFROMREG(rv.d, MIPSInst_FT(ir));
2074 DPFROMREG(rv.d, MIPSInst_FS(ir));
2078 if (!cpu_has_mips_r6)
2081 DPFROMREG(rv.d, MIPSInst_FT(ir));
2083 DPFROMREG(rv.d, MIPSInst_FS(ir));
2089 union ieee754dp ft, fs, fd;
2091 if (!cpu_has_mips_r6)
2094 DPFROMREG(ft, MIPSInst_FT(ir));
2095 DPFROMREG(fs, MIPSInst_FS(ir));
2096 DPFROMREG(fd, MIPSInst_FD(ir));
2097 rv.d = ieee754dp_maddf(fd, fs, ft);
2102 union ieee754dp ft, fs, fd;
2104 if (!cpu_has_mips_r6)
2107 DPFROMREG(ft, MIPSInst_FT(ir));
2108 DPFROMREG(fs, MIPSInst_FS(ir));
2109 DPFROMREG(fd, MIPSInst_FD(ir));
2110 rv.d = ieee754dp_msubf(fd, fs, ft);
2117 if (!cpu_has_mips_r6)
2120 DPFROMREG(fs, MIPSInst_FS(ir));
2121 rv.l = ieee754dp_tlong(fs);
2122 rv.d = ieee754dp_flong(rv.l);
2129 if (!cpu_has_mips_r6)
2132 DPFROMREG(fs, MIPSInst_FS(ir));
2133 rv.w = ieee754dp_2008class(fs);
2139 union ieee754dp fs, ft;
2141 if (!cpu_has_mips_r6)
2144 DPFROMREG(ft, MIPSInst_FT(ir));
2145 DPFROMREG(fs, MIPSInst_FS(ir));
2146 rv.d = ieee754dp_fmin(fs, ft);
2151 union ieee754dp fs, ft;
2153 if (!cpu_has_mips_r6)
2156 DPFROMREG(ft, MIPSInst_FT(ir));
2157 DPFROMREG(fs, MIPSInst_FS(ir));
2158 rv.d = ieee754dp_fmina(fs, ft);
2163 union ieee754dp fs, ft;
2165 if (!cpu_has_mips_r6)
2168 DPFROMREG(ft, MIPSInst_FT(ir));
2169 DPFROMREG(fs, MIPSInst_FS(ir));
2170 rv.d = ieee754dp_fmax(fs, ft);
2175 union ieee754dp fs, ft;
2177 if (!cpu_has_mips_r6)
2180 DPFROMREG(ft, MIPSInst_FT(ir));
2181 DPFROMREG(fs, MIPSInst_FS(ir));
2182 rv.d = ieee754dp_fmaxa(fs, ft);
2187 handler.u = ieee754dp_abs;
2191 handler.u = ieee754dp_neg;
2196 DPFROMREG(rv.d, MIPSInst_FS(ir));
2199 /* binary op on handler */
2201 DPFROMREG(fs, MIPSInst_FS(ir));
2202 DPFROMREG(ft, MIPSInst_FT(ir));
2204 rv.d = (*handler.b) (fs, ft);
2207 DPFROMREG(fs, MIPSInst_FS(ir));
2208 rv.d = (*handler.u) (fs);
2215 DPFROMREG(fs, MIPSInst_FS(ir));
2216 rv.s = ieee754sp_fdp(fs);
2221 return SIGILL; /* not defined */
2224 DPFROMREG(fs, MIPSInst_FS(ir));
2225 rv.w = ieee754dp_tint(fs); /* wrong */
2233 if (!cpu_has_mips_2_3_4_5_r)
2236 oldrm = ieee754_csr.rm;
2237 DPFROMREG(fs, MIPSInst_FS(ir));
2238 ieee754_csr.rm = MIPSInst_FUNC(ir);
2239 rv.w = ieee754dp_tint(fs);
2240 ieee754_csr.rm = oldrm;
2245 if (!cpu_has_mips_3_4_5_64_r2_r6)
2248 DPFROMREG(fs, MIPSInst_FS(ir));
2249 rv.l = ieee754dp_tlong(fs);
2257 if (!cpu_has_mips_3_4_5_64_r2_r6)
2260 oldrm = ieee754_csr.rm;
2261 DPFROMREG(fs, MIPSInst_FS(ir));
2262 ieee754_csr.rm = MIPSInst_FUNC(ir);
2263 rv.l = ieee754dp_tlong(fs);
2264 ieee754_csr.rm = oldrm;
2269 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2270 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2271 union ieee754dp fs, ft;
2273 DPFROMREG(fs, MIPSInst_FS(ir));
2274 DPFROMREG(ft, MIPSInst_FT(ir));
2275 rv.w = ieee754dp_cmp(fs, ft,
2276 cmptab[cmpop & 0x7], cmpop & 0x8);
2281 (IEEE754_INVALID_OPERATION))
2282 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2298 switch (MIPSInst_FUNC(ir)) {
2300 /* convert word to single precision real */
2301 SPFROMREG(fs, MIPSInst_FS(ir));
2302 rv.s = ieee754sp_fint(fs.bits);
2306 /* convert word to double precision real */
2307 SPFROMREG(fs, MIPSInst_FS(ir));
2308 rv.d = ieee754dp_fint(fs.bits);
2312 /* Emulating the new CMP.condn.fmt R6 instruction */
2313 #define CMPOP_MASK 0x7
2314 #define SIGN_BIT (0x1 << 3)
2315 #define PREDICATE_BIT (0x1 << 4)
2317 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2318 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2319 union ieee754sp fs, ft;
2321 /* This is an R6 only instruction */
2322 if (!cpu_has_mips_r6 ||
2323 (MIPSInst_FUNC(ir) & 0x20))
2326 /* fmt is w_fmt for single precision so fix it */
2328 /* default to false */
2332 SPFROMREG(fs, MIPSInst_FS(ir));
2333 SPFROMREG(ft, MIPSInst_FT(ir));
2335 /* positive predicates */
2336 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2337 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2339 rv.w = -1; /* true, all 1s */
2341 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2342 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2346 /* negative predicates */
2351 if (ieee754sp_cmp(fs, ft,
2352 negative_cmptab[cmpop],
2354 rv.w = -1; /* true, all 1s */
2356 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2357 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2362 /* Reserved R6 ops */
2363 pr_err("Reserved MIPS R6 CMP.condn.S operation\n");
2374 if (!cpu_has_mips_3_4_5_64_r2_r6)
2377 DIFROMREG(bits, MIPSInst_FS(ir));
2379 switch (MIPSInst_FUNC(ir)) {
2381 /* convert long to single precision real */
2382 rv.s = ieee754sp_flong(bits);
2386 /* convert long to double precision real */
2387 rv.d = ieee754dp_flong(bits);
2391 /* Emulating the new CMP.condn.fmt R6 instruction */
2392 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2393 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2394 union ieee754dp fs, ft;
2396 if (!cpu_has_mips_r6 ||
2397 (MIPSInst_FUNC(ir) & 0x20))
2400 /* fmt is l_fmt for double precision so fix it */
2402 /* default to false */
2406 DPFROMREG(fs, MIPSInst_FS(ir));
2407 DPFROMREG(ft, MIPSInst_FT(ir));
2409 /* positive predicates */
2410 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2411 if (ieee754dp_cmp(fs, ft,
2412 cmptab[cmpop], sig))
2413 rv.l = -1LL; /* true, all 1s */
2415 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2416 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2420 /* negative predicates */
2425 if (ieee754dp_cmp(fs, ft,
2426 negative_cmptab[cmpop],
2428 rv.l = -1LL; /* true, all 1s */
2430 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2431 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2436 /* Reserved R6 ops */
2437 pr_err("Reserved MIPS R6 CMP.condn.D operation\n");
2449 * Update the fpu CSR register for this operation.
2450 * If an exception is required, generate a tidy SIGFPE exception,
2451 * without updating the result register.
2452 * Note: cause exception bits do not accumulate, they are rewritten
2453 * for each op; only the flag/sticky bits accumulate.
2455 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2456 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2457 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2462 * Now we can safely write the result back to the register file.
2467 if (cpu_has_mips_4_5_r)
2468 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2470 cbit = FPU_CSR_COND;
2474 ctx->fcr31 &= ~cbit;
2478 DPTOREG(rv.d, MIPSInst_FD(ir));
2481 SPTOREG(rv.s, MIPSInst_FD(ir));
2484 SITOREG(rv.w, MIPSInst_FD(ir));
2487 if (!cpu_has_mips_3_4_5_64_r2_r6)
2490 DITOREG(rv.l, MIPSInst_FD(ir));
2499 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2500 int has_fpu, void *__user *fault_addr)
2502 unsigned long oldepc, prevepc;
2503 struct mm_decoded_insn dec_insn;
2508 oldepc = xcp->cp0_epc;
2510 prevepc = xcp->cp0_epc;
2512 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2514 * Get next 2 microMIPS instructions and convert them
2515 * into 32-bit instructions.
2517 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2518 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2519 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2520 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2521 MIPS_FPU_EMU_INC_STATS(errors);
2526 /* Get first instruction. */
2527 if (mm_insn_16bit(*instr_ptr)) {
2528 /* Duplicate the half-word. */
2529 dec_insn.insn = (*instr_ptr << 16) |
2531 /* 16-bit instruction. */
2532 dec_insn.pc_inc = 2;
2535 dec_insn.insn = (*instr_ptr << 16) |
2537 /* 32-bit instruction. */
2538 dec_insn.pc_inc = 4;
2541 /* Get second instruction. */
2542 if (mm_insn_16bit(*instr_ptr)) {
2543 /* Duplicate the half-word. */
2544 dec_insn.next_insn = (*instr_ptr << 16) |
2546 /* 16-bit instruction. */
2547 dec_insn.next_pc_inc = 2;
2549 dec_insn.next_insn = (*instr_ptr << 16) |
2551 /* 32-bit instruction. */
2552 dec_insn.next_pc_inc = 4;
2554 dec_insn.micro_mips_mode = 1;
2556 if ((get_user(dec_insn.insn,
2557 (mips_instruction __user *) xcp->cp0_epc)) ||
2558 (get_user(dec_insn.next_insn,
2559 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2560 MIPS_FPU_EMU_INC_STATS(errors);
2563 dec_insn.pc_inc = 4;
2564 dec_insn.next_pc_inc = 4;
2565 dec_insn.micro_mips_mode = 0;
2568 if ((dec_insn.insn == 0) ||
2569 ((dec_insn.pc_inc == 2) &&
2570 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2571 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2574 * The 'ieee754_csr' is an alias of ctx->fcr31.
2575 * No need to copy ctx->fcr31 to ieee754_csr.
2577 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2586 } while (xcp->cp0_epc > prevepc);
2588 /* SIGILL indicates a non-fpu instruction */
2589 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2590 /* but if EPC has advanced, then ignore it */