2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd.
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/compiler.h>
18 #include <linux/context_tracking.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/kexec.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
25 #include <linux/sched.h>
26 #include <linux/smp.h>
27 #include <linux/spinlock.h>
28 #include <linux/kallsyms.h>
29 #include <linux/bootmem.h>
30 #include <linux/interrupt.h>
31 #include <linux/ptrace.h>
32 #include <linux/kgdb.h>
33 #include <linux/kdebug.h>
34 #include <linux/kprobes.h>
35 #include <linux/notifier.h>
36 #include <linux/kdb.h>
37 #include <linux/irq.h>
38 #include <linux/perf_event.h>
40 #include <asm/bootinfo.h>
41 #include <asm/branch.h>
42 #include <asm/break.h>
45 #include <asm/cpu-type.h>
48 #include <asm/fpu_emulator.h>
50 #include <asm/mips-r2-to-r6-emul.h>
51 #include <asm/mipsregs.h>
52 #include <asm/mipsmtregs.h>
53 #include <asm/module.h>
55 #include <asm/pgtable.h>
56 #include <asm/ptrace.h>
57 #include <asm/sections.h>
58 #include <asm/tlbdebug.h>
59 #include <asm/traps.h>
60 #include <asm/uaccess.h>
61 #include <asm/watch.h>
62 #include <asm/mmu_context.h>
63 #include <asm/types.h>
64 #include <asm/stacktrace.h>
67 extern void check_wait(void);
68 extern asmlinkage void rollback_handle_int(void);
69 extern asmlinkage void handle_int(void);
70 extern u32 handle_tlbl[];
71 extern u32 handle_tlbs[];
72 extern u32 handle_tlbm[];
73 extern asmlinkage void handle_adel(void);
74 extern asmlinkage void handle_ades(void);
75 extern asmlinkage void handle_ibe(void);
76 extern asmlinkage void handle_dbe(void);
77 extern asmlinkage void handle_sys(void);
78 extern asmlinkage void handle_bp(void);
79 extern asmlinkage void handle_ri(void);
80 extern asmlinkage void handle_ri_rdhwr_vivt(void);
81 extern asmlinkage void handle_ri_rdhwr(void);
82 extern asmlinkage void handle_cpu(void);
83 extern asmlinkage void handle_ov(void);
84 extern asmlinkage void handle_tr(void);
85 extern asmlinkage void handle_msa_fpe(void);
86 extern asmlinkage void handle_fpe(void);
87 extern asmlinkage void handle_ftlb(void);
88 extern asmlinkage void handle_msa(void);
89 extern asmlinkage void handle_mdmx(void);
90 extern asmlinkage void handle_watch(void);
91 extern asmlinkage void handle_mt(void);
92 extern asmlinkage void handle_dsp(void);
93 extern asmlinkage void handle_mcheck(void);
94 extern asmlinkage void handle_reserved(void);
95 extern void tlb_do_page_fault_0(void);
97 void (*board_be_init)(void);
98 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
99 void (*board_nmi_handler_setup)(void);
100 void (*board_ejtag_handler_setup)(void);
101 void (*board_bind_eic_interrupt)(int irq, int regset);
102 void (*board_ebase_setup)(void);
103 void(*board_cache_error_setup)(void);
105 static void show_raw_backtrace(unsigned long reg29)
107 unsigned long *sp = (unsigned long *)(reg29 & ~3);
110 printk("Call Trace:");
111 #ifdef CONFIG_KALLSYMS
114 while (!kstack_end(sp)) {
115 unsigned long __user *p =
116 (unsigned long __user *)(unsigned long)sp++;
117 if (__get_user(addr, p)) {
118 printk(" (Bad stack address)");
121 if (__kernel_text_address(addr))
127 #ifdef CONFIG_KALLSYMS
129 static int __init set_raw_show_trace(char *str)
134 __setup("raw_show_trace", set_raw_show_trace);
137 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
139 unsigned long sp = regs->regs[29];
140 unsigned long ra = regs->regs[31];
141 unsigned long pc = regs->cp0_epc;
146 if (raw_show_trace || !__kernel_text_address(pc)) {
147 show_raw_backtrace(sp);
150 printk("Call Trace:\n");
153 pc = unwind_stack(task, &sp, pc, &ra);
159 * This routine abuses get_user()/put_user() to reference pointers
160 * with at least a bit of error checking ...
162 static void show_stacktrace(struct task_struct *task,
163 const struct pt_regs *regs)
165 const int field = 2 * sizeof(unsigned long);
168 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
172 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
173 if (i && ((i % (64 / field)) == 0))
180 if (__get_user(stackdata, sp++)) {
181 printk(" (Bad stack address)");
185 printk(" %0*lx", field, stackdata);
189 show_backtrace(task, regs);
192 void show_stack(struct task_struct *task, unsigned long *sp)
195 mm_segment_t old_fs = get_fs();
197 regs.regs[29] = (unsigned long)sp;
201 if (task && task != current) {
202 regs.regs[29] = task->thread.reg29;
204 regs.cp0_epc = task->thread.reg31;
205 #ifdef CONFIG_KGDB_KDB
206 } else if (atomic_read(&kgdb_active) != -1 &&
208 memcpy(®s, kdb_current_regs, sizeof(regs));
209 #endif /* CONFIG_KGDB_KDB */
211 prepare_frametrace(®s);
215 * show_stack() deals exclusively with kernel mode, so be sure to access
216 * the stack in the kernel (not user) address space.
219 show_stacktrace(task, ®s);
223 static void show_code(unsigned int __user *pc)
226 unsigned short __user *pc16 = NULL;
230 if ((unsigned long)pc & 1)
231 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
232 for(i = -3 ; i < 6 ; i++) {
234 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
235 printk(" (Bad address in epc)\n");
238 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
242 static void __show_regs(const struct pt_regs *regs)
244 const int field = 2 * sizeof(unsigned long);
245 unsigned int cause = regs->cp0_cause;
248 show_regs_print_info(KERN_DEFAULT);
251 * Saved main processor registers
253 for (i = 0; i < 32; ) {
257 printk(" %0*lx", field, 0UL);
258 else if (i == 26 || i == 27)
259 printk(" %*s", field, "");
261 printk(" %0*lx", field, regs->regs[i]);
268 #ifdef CONFIG_CPU_HAS_SMARTMIPS
269 printk("Acx : %0*lx\n", field, regs->acx);
271 printk("Hi : %0*lx\n", field, regs->hi);
272 printk("Lo : %0*lx\n", field, regs->lo);
275 * Saved cp0 registers
277 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
278 (void *) regs->cp0_epc);
279 printk("ra : %0*lx %pS\n", field, regs->regs[31],
280 (void *) regs->regs[31]);
282 printk("Status: %08x ", (uint32_t) regs->cp0_status);
285 if (regs->cp0_status & ST0_KUO)
287 if (regs->cp0_status & ST0_IEO)
289 if (regs->cp0_status & ST0_KUP)
291 if (regs->cp0_status & ST0_IEP)
293 if (regs->cp0_status & ST0_KUC)
295 if (regs->cp0_status & ST0_IEC)
297 } else if (cpu_has_4kex) {
298 if (regs->cp0_status & ST0_KX)
300 if (regs->cp0_status & ST0_SX)
302 if (regs->cp0_status & ST0_UX)
304 switch (regs->cp0_status & ST0_KSU) {
309 printk("SUPERVISOR ");
318 if (regs->cp0_status & ST0_ERL)
320 if (regs->cp0_status & ST0_EXL)
322 if (regs->cp0_status & ST0_IE)
327 printk("Cause : %08x\n", cause);
329 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
330 if (1 <= cause && cause <= 5)
331 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
333 printk("PrId : %08x (%s)\n", read_c0_prid(),
338 * FIXME: really the generic show_regs should take a const pointer argument.
340 void show_regs(struct pt_regs *regs)
342 __show_regs((struct pt_regs *)regs);
345 void show_registers(struct pt_regs *regs)
347 const int field = 2 * sizeof(unsigned long);
348 mm_segment_t old_fs = get_fs();
352 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
353 current->comm, current->pid, current_thread_info(), current,
354 field, current_thread_info()->tp_value);
355 if (cpu_has_userlocal) {
358 tls = read_c0_userlocal();
359 if (tls != current_thread_info()->tp_value)
360 printk("*HwTLS: %0*lx\n", field, tls);
363 if (!user_mode(regs))
364 /* Necessary for getting the correct stack content */
366 show_stacktrace(current, regs);
367 show_code((unsigned int __user *) regs->cp0_epc);
372 static int regs_to_trapnr(struct pt_regs *regs)
374 return (regs->cp0_cause >> 2) & 0x1f;
377 static DEFINE_RAW_SPINLOCK(die_lock);
379 void __noreturn die(const char *str, struct pt_regs *regs)
381 static int die_counter;
386 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs),
387 SIGSEGV) == NOTIFY_STOP)
391 raw_spin_lock_irq(&die_lock);
394 printk("%s[#%d]:\n", str, ++die_counter);
395 show_registers(regs);
396 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
397 raw_spin_unlock_irq(&die_lock);
402 panic("Fatal exception in interrupt");
405 printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
407 panic("Fatal exception");
410 if (regs && kexec_should_crash(current))
416 extern struct exception_table_entry __start___dbe_table[];
417 extern struct exception_table_entry __stop___dbe_table[];
420 " .section __dbe_table, \"a\"\n"
423 /* Given an address, look for it in the exception tables. */
424 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
426 const struct exception_table_entry *e;
428 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
430 e = search_module_dbetables(addr);
434 asmlinkage void do_be(struct pt_regs *regs)
436 const int field = 2 * sizeof(unsigned long);
437 const struct exception_table_entry *fixup = NULL;
438 int data = regs->cp0_cause & 4;
439 int action = MIPS_BE_FATAL;
440 enum ctx_state prev_state;
442 prev_state = exception_enter();
443 /* XXX For now. Fixme, this searches the wrong table ... */
444 if (data && !user_mode(regs))
445 fixup = search_dbe_tables(exception_epc(regs));
448 action = MIPS_BE_FIXUP;
450 if (board_be_handler)
451 action = board_be_handler(regs, fixup != NULL);
454 case MIPS_BE_DISCARD:
458 regs->cp0_epc = fixup->nextinsn;
467 * Assume it would be too dangerous to continue ...
469 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
470 data ? "Data" : "Instruction",
471 field, regs->cp0_epc, field, regs->regs[31]);
472 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs),
473 SIGBUS) == NOTIFY_STOP)
476 die_if_kernel("Oops", regs);
477 force_sig(SIGBUS, current);
480 exception_exit(prev_state);
484 * ll/sc, rdhwr, sync emulation
487 #define OPCODE 0xfc000000
488 #define BASE 0x03e00000
489 #define RT 0x001f0000
490 #define OFFSET 0x0000ffff
491 #define LL 0xc0000000
492 #define SC 0xe0000000
493 #define SPEC0 0x00000000
494 #define SPEC3 0x7c000000
495 #define RD 0x0000f800
496 #define FUNC 0x0000003f
497 #define SYNC 0x0000000f
498 #define RDHWR 0x0000003b
500 /* microMIPS definitions */
501 #define MM_POOL32A_FUNC 0xfc00ffff
502 #define MM_RDHWR 0x00006b3c
503 #define MM_RS 0x001f0000
504 #define MM_RT 0x03e00000
507 * The ll_bit is cleared by r*_switch.S
511 struct task_struct *ll_task;
513 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
515 unsigned long value, __user *vaddr;
519 * analyse the ll instruction that just caused a ri exception
520 * and put the referenced address to addr.
523 /* sign extend offset */
524 offset = opcode & OFFSET;
528 vaddr = (unsigned long __user *)
529 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
531 if ((unsigned long)vaddr & 3)
533 if (get_user(value, vaddr))
538 if (ll_task == NULL || ll_task == current) {
547 regs->regs[(opcode & RT) >> 16] = value;
552 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
554 unsigned long __user *vaddr;
559 * analyse the sc instruction that just caused a ri exception
560 * and put the referenced address to addr.
563 /* sign extend offset */
564 offset = opcode & OFFSET;
568 vaddr = (unsigned long __user *)
569 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
570 reg = (opcode & RT) >> 16;
572 if ((unsigned long)vaddr & 3)
577 if (ll_bit == 0 || ll_task != current) {
585 if (put_user(regs->regs[reg], vaddr))
594 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
595 * opcodes are supposed to result in coprocessor unusable exceptions if
596 * executed on ll/sc-less processors. That's the theory. In practice a
597 * few processors such as NEC's VR4100 throw reserved instruction exceptions
598 * instead, so we're doing the emulation thing in both exception handlers.
600 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
602 if ((opcode & OPCODE) == LL) {
603 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
605 return simulate_ll(regs, opcode);
607 if ((opcode & OPCODE) == SC) {
608 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
610 return simulate_sc(regs, opcode);
613 return -1; /* Must be something else ... */
617 * Simulate trapping 'rdhwr' instructions to provide user accessible
618 * registers not implemented in hardware.
620 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
622 struct thread_info *ti = task_thread_info(current);
624 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
627 case 0: /* CPU number */
628 regs->regs[rt] = smp_processor_id();
630 case 1: /* SYNCI length */
631 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
632 current_cpu_data.icache.linesz);
634 case 2: /* Read count register */
635 regs->regs[rt] = read_c0_count();
637 case 3: /* Count register resolution */
638 switch (current_cpu_type()) {
648 regs->regs[rt] = ti->tp_value;
655 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
657 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
658 int rd = (opcode & RD) >> 11;
659 int rt = (opcode & RT) >> 16;
661 simulate_rdhwr(regs, rd, rt);
669 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode)
671 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
672 int rd = (opcode & MM_RS) >> 16;
673 int rt = (opcode & MM_RT) >> 21;
674 simulate_rdhwr(regs, rd, rt);
682 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
684 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
685 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
690 return -1; /* Must be something else ... */
693 asmlinkage void do_ov(struct pt_regs *regs)
695 enum ctx_state prev_state;
698 prev_state = exception_enter();
699 die_if_kernel("Integer overflow", regs);
701 info.si_code = FPE_INTOVF;
702 info.si_signo = SIGFPE;
704 info.si_addr = (void __user *) regs->cp0_epc;
705 force_sig_info(SIGFPE, &info, current);
706 exception_exit(prev_state);
709 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
711 struct siginfo si = { 0 };
718 si.si_addr = fault_addr;
721 * Inexact can happen together with Overflow or Underflow.
722 * Respect the mask to deliver the correct exception.
724 fcr31 &= (fcr31 & FPU_CSR_ALL_E) <<
725 (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E));
726 if (fcr31 & FPU_CSR_INV_X)
727 si.si_code = FPE_FLTINV;
728 else if (fcr31 & FPU_CSR_DIV_X)
729 si.si_code = FPE_FLTDIV;
730 else if (fcr31 & FPU_CSR_OVF_X)
731 si.si_code = FPE_FLTOVF;
732 else if (fcr31 & FPU_CSR_UDF_X)
733 si.si_code = FPE_FLTUND;
734 else if (fcr31 & FPU_CSR_INE_X)
735 si.si_code = FPE_FLTRES;
737 si.si_code = __SI_FAULT;
738 force_sig_info(sig, &si, current);
742 si.si_addr = fault_addr;
744 si.si_code = BUS_ADRERR;
745 force_sig_info(sig, &si, current);
749 si.si_addr = fault_addr;
751 down_read(¤t->mm->mmap_sem);
752 if (find_vma(current->mm, (unsigned long)fault_addr))
753 si.si_code = SEGV_ACCERR;
755 si.si_code = SEGV_MAPERR;
756 up_read(¤t->mm->mmap_sem);
757 force_sig_info(sig, &si, current);
761 force_sig(sig, current);
766 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
767 unsigned long old_epc, unsigned long old_ra)
769 union mips_instruction inst = { .word = opcode };
770 void __user *fault_addr;
774 /* If it's obviously not an FP instruction, skip it */
775 switch (inst.i_format.opcode) {
789 * do_ri skipped over the instruction via compute_return_epc, undo
790 * that for the FPU emulator.
792 regs->cp0_epc = old_epc;
793 regs->regs[31] = old_ra;
795 /* Save the FP context to struct thread_struct */
798 /* Run the emulator */
799 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
801 fcr31 = current->thread.fpu.fcr31;
804 * We can't allow the emulated instruction to leave any of
805 * the cause bits set in $fcr31.
807 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
809 /* Restore the hardware register state */
812 /* Send a signal if required. */
813 process_fpemu_return(sig, fault_addr, fcr31);
819 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
821 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
823 enum ctx_state prev_state;
824 void __user *fault_addr;
827 prev_state = exception_enter();
828 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs),
829 SIGFPE) == NOTIFY_STOP)
832 /* Clear FCSR.Cause before enabling interrupts */
833 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~FPU_CSR_ALL_X);
836 die_if_kernel("FP exception in kernel code", regs);
838 if (fcr31 & FPU_CSR_UNI_X) {
840 * Unimplemented operation exception. If we've got the full
841 * software emulator on-board, let's use it...
843 * Force FPU to dump state into task/thread context. We're
844 * moving a lot of data here for what is probably a single
845 * instruction, but the alternative is to pre-decode the FP
846 * register operands before invoking the emulator, which seems
847 * a bit extreme for what should be an infrequent event.
849 /* Ensure 'resume' not overwrite saved fp context again. */
852 /* Run the emulator */
853 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
855 fcr31 = current->thread.fpu.fcr31;
858 * We can't allow the emulated instruction to leave any of
859 * the cause bits set in $fcr31.
861 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
863 /* Restore the hardware register state */
864 own_fpu(1); /* Using the FPU again. */
867 fault_addr = (void __user *) regs->cp0_epc;
870 /* Send a signal if required. */
871 process_fpemu_return(sig, fault_addr, fcr31);
874 exception_exit(prev_state);
877 void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
883 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
884 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
886 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
888 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs),
889 SIGTRAP) == NOTIFY_STOP)
893 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
894 * insns, even for trap and break codes that indicate arithmetic
895 * failures. Weird ...
896 * But should we continue the brokenness??? --macro
901 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
902 die_if_kernel(b, regs);
903 if (code == BRK_DIVZERO)
904 info.si_code = FPE_INTDIV;
906 info.si_code = FPE_INTOVF;
907 info.si_signo = SIGFPE;
909 info.si_addr = (void __user *) regs->cp0_epc;
910 force_sig_info(SIGFPE, &info, current);
913 die_if_kernel("Kernel bug detected", regs);
914 force_sig(SIGTRAP, current);
918 * This breakpoint code is used by the FPU emulator to retake
919 * control of the CPU after executing the instruction from the
920 * delay slot of an emulated branch.
922 * Terminate if exception was recognized as a delay slot return
923 * otherwise handle as normal.
925 if (do_dsemulret(regs))
928 die_if_kernel("Math emu break/trap", regs);
929 force_sig(SIGTRAP, current);
932 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
933 die_if_kernel(b, regs);
934 force_sig(SIGTRAP, current);
938 asmlinkage void do_bp(struct pt_regs *regs)
940 unsigned long epc = msk_isa16_mode(exception_epc(regs));
941 unsigned int opcode, bcode;
942 enum ctx_state prev_state;
946 if (!user_mode(regs))
949 prev_state = exception_enter();
950 if (get_isa16_mode(regs->cp0_epc)) {
953 if (__get_user(instr[0], (u16 __user *)epc))
956 if (!cpu_has_mmips) {
958 bcode = (instr[0] >> 5) & 0x3f;
959 } else if (mm_insn_16bit(instr[0])) {
960 /* 16-bit microMIPS BREAK */
961 bcode = instr[0] & 0xf;
963 /* 32-bit microMIPS BREAK */
964 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
966 opcode = (instr[0] << 16) | instr[1];
967 bcode = (opcode >> 6) & ((1 << 20) - 1);
970 if (__get_user(opcode, (unsigned int __user *)epc))
972 bcode = (opcode >> 6) & ((1 << 20) - 1);
976 * There is the ancient bug in the MIPS assemblers that the break
977 * code starts left to bit 16 instead to bit 6 in the opcode.
978 * Gas is bug-compatible, but not always, grrr...
979 * We handle both cases with a simple heuristics. --macro
981 if (bcode >= (1 << 10))
982 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
985 * notify the kprobe handlers, if instruction is likely to
990 if (notify_die(DIE_BREAK, "debug", regs, bcode,
991 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
995 case BRK_KPROBE_SSTEPBP:
996 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
997 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
1005 do_trap_or_bp(regs, bcode, "Break");
1009 exception_exit(prev_state);
1013 force_sig(SIGSEGV, current);
1017 asmlinkage void do_tr(struct pt_regs *regs)
1019 u32 opcode, tcode = 0;
1020 enum ctx_state prev_state;
1023 unsigned long epc = msk_isa16_mode(exception_epc(regs));
1026 if (!user_mode(regs))
1029 prev_state = exception_enter();
1030 if (get_isa16_mode(regs->cp0_epc)) {
1031 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1032 __get_user(instr[1], (u16 __user *)(epc + 2)))
1034 opcode = (instr[0] << 16) | instr[1];
1035 /* Immediate versions don't provide a code. */
1036 if (!(opcode & OPCODE))
1037 tcode = (opcode >> 12) & ((1 << 4) - 1);
1039 if (__get_user(opcode, (u32 __user *)epc))
1041 /* Immediate versions don't provide a code. */
1042 if (!(opcode & OPCODE))
1043 tcode = (opcode >> 6) & ((1 << 10) - 1);
1046 do_trap_or_bp(regs, tcode, "Trap");
1050 exception_exit(prev_state);
1054 force_sig(SIGSEGV, current);
1058 asmlinkage void do_ri(struct pt_regs *regs)
1060 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1061 unsigned long old_epc = regs->cp0_epc;
1062 unsigned long old31 = regs->regs[31];
1063 enum ctx_state prev_state;
1064 unsigned int opcode = 0;
1068 * Avoid any kernel code. Just emulate the R2 instruction
1069 * as quickly as possible.
1071 if (mipsr2_emulation && cpu_has_mips_r6 &&
1072 likely(user_mode(regs)) &&
1073 likely(get_user(opcode, epc) >= 0)) {
1074 unsigned long fcr31 = 0;
1076 status = mipsr2_decoder(regs, opcode, &fcr31);
1080 task_thread_info(current)->r2_emul_return = 1;
1085 process_fpemu_return(status,
1086 ¤t->thread.cp0_baduaddr,
1088 task_thread_info(current)->r2_emul_return = 1;
1095 prev_state = exception_enter();
1097 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs),
1098 SIGILL) == NOTIFY_STOP)
1101 die_if_kernel("Reserved instruction in kernel code", regs);
1103 if (unlikely(compute_return_epc(regs) < 0))
1106 if (get_isa16_mode(regs->cp0_epc)) {
1107 unsigned short mmop[2] = { 0 };
1109 if (unlikely(get_user(mmop[0], epc) < 0))
1111 if (unlikely(get_user(mmop[1], epc) < 0))
1113 opcode = (mmop[0] << 16) | mmop[1];
1116 status = simulate_rdhwr_mm(regs, opcode);
1118 if (unlikely(get_user(opcode, epc) < 0))
1121 if (!cpu_has_llsc && status < 0)
1122 status = simulate_llsc(regs, opcode);
1125 status = simulate_rdhwr_normal(regs, opcode);
1128 status = simulate_sync(regs, opcode);
1131 status = simulate_fp(regs, opcode, old_epc, old31);
1137 if (unlikely(status > 0)) {
1138 regs->cp0_epc = old_epc; /* Undo skip-over. */
1139 regs->regs[31] = old31;
1140 force_sig(status, current);
1144 exception_exit(prev_state);
1148 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1149 * emulated more than some threshold number of instructions, force migration to
1150 * a "CPU" that has FP support.
1152 static void mt_ase_fp_affinity(void)
1154 #ifdef CONFIG_MIPS_MT_FPAFF
1155 if (mt_fpemul_threshold > 0 &&
1156 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1158 * If there's no FPU present, or if the application has already
1159 * restricted the allowed set to exclude any CPUs with FPUs,
1160 * we'll skip the procedure.
1162 if (cpumask_intersects(¤t->cpus_allowed, &mt_fpu_cpumask)) {
1165 current->thread.user_cpus_allowed
1166 = current->cpus_allowed;
1167 cpumask_and(&tmask, ¤t->cpus_allowed,
1169 set_cpus_allowed_ptr(current, &tmask);
1170 set_thread_flag(TIF_FPUBOUND);
1173 #endif /* CONFIG_MIPS_MT_FPAFF */
1177 * No lock; only written during early bootup by CPU 0.
1179 static RAW_NOTIFIER_HEAD(cu2_chain);
1181 int __ref register_cu2_notifier(struct notifier_block *nb)
1183 return raw_notifier_chain_register(&cu2_chain, nb);
1186 int cu2_notifier_call_chain(unsigned long val, void *v)
1188 return raw_notifier_call_chain(&cu2_chain, val, v);
1191 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1194 struct pt_regs *regs = data;
1196 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1197 "instruction", regs);
1198 force_sig(SIGILL, current);
1203 static int wait_on_fp_mode_switch(atomic_t *p)
1206 * The FP mode for this task is currently being switched. That may
1207 * involve modifications to the format of this tasks FP context which
1208 * make it unsafe to proceed with execution for the moment. Instead,
1209 * schedule some other task.
1215 static int enable_restore_fp_context(int msa)
1217 int err, was_fpu_owner, prior_msa;
1220 * If an FP mode switch is currently underway, wait for it to
1221 * complete before proceeding.
1223 wait_on_atomic_t(¤t->mm->context.fp_mode_switching,
1224 wait_on_fp_mode_switch, TASK_KILLABLE);
1227 /* First time FP context user. */
1233 set_thread_flag(TIF_USEDMSA);
1234 set_thread_flag(TIF_MSA_CTX_LIVE);
1243 * This task has formerly used the FP context.
1245 * If this thread has no live MSA vector context then we can simply
1246 * restore the scalar FP context. If it has live MSA vector context
1247 * (that is, it has or may have used MSA since last performing a
1248 * function call) then we'll need to restore the vector context. This
1249 * applies even if we're currently only executing a scalar FP
1250 * instruction. This is because if we were to later execute an MSA
1251 * instruction then we'd either have to:
1253 * - Restore the vector context & clobber any registers modified by
1254 * scalar FP instructions between now & then.
1258 * - Not restore the vector context & lose the most significant bits
1259 * of all vector registers.
1261 * Neither of those options is acceptable. We cannot restore the least
1262 * significant bits of the registers now & only restore the most
1263 * significant bits later because the most significant bits of any
1264 * vector registers whose aliased FP register is modified now will have
1265 * been zeroed. We'd have no way to know that when restoring the vector
1266 * context & thus may load an outdated value for the most significant
1267 * bits of a vector register.
1269 if (!msa && !thread_msa_context_live())
1273 * This task is using or has previously used MSA. Thus we require
1274 * that Status.FR == 1.
1277 was_fpu_owner = is_fpu_owner();
1278 err = own_fpu_inatomic(0);
1283 write_msa_csr(current->thread.fpu.msacsr);
1284 set_thread_flag(TIF_USEDMSA);
1287 * If this is the first time that the task is using MSA and it has
1288 * previously used scalar FP in this time slice then we already nave
1289 * FP context which we shouldn't clobber. We do however need to clear
1290 * the upper 64b of each vector register so that this task has no
1291 * opportunity to see data left behind by another.
1293 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1294 if (!prior_msa && was_fpu_owner) {
1302 * Restore the least significant 64b of each vector register
1303 * from the existing scalar FP context.
1305 _restore_fp(current);
1308 * The task has not formerly used MSA, so clear the upper 64b
1309 * of each vector register such that it cannot see data left
1310 * behind by another task.
1314 /* We need to restore the vector context. */
1315 restore_msa(current);
1317 /* Restore the scalar FP control & status register */
1319 write_32bit_cp1_register(CP1_STATUS,
1320 current->thread.fpu.fcr31);
1329 asmlinkage void do_cpu(struct pt_regs *regs)
1331 enum ctx_state prev_state;
1332 unsigned int __user *epc;
1333 unsigned long old_epc, old31;
1334 void __user *fault_addr;
1335 unsigned int opcode;
1336 unsigned long fcr31;
1339 unsigned long __maybe_unused flags;
1342 prev_state = exception_enter();
1343 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1346 die_if_kernel("do_cpu invoked from kernel context!", regs);
1350 epc = (unsigned int __user *)exception_epc(regs);
1351 old_epc = regs->cp0_epc;
1352 old31 = regs->regs[31];
1356 if (unlikely(compute_return_epc(regs) < 0))
1359 if (get_isa16_mode(regs->cp0_epc)) {
1360 unsigned short mmop[2] = { 0 };
1362 if (unlikely(get_user(mmop[0], epc) < 0))
1364 if (unlikely(get_user(mmop[1], epc) < 0))
1366 opcode = (mmop[0] << 16) | mmop[1];
1369 status = simulate_rdhwr_mm(regs, opcode);
1371 if (unlikely(get_user(opcode, epc) < 0))
1374 if (!cpu_has_llsc && status < 0)
1375 status = simulate_llsc(regs, opcode);
1378 status = simulate_rdhwr_normal(regs, opcode);
1384 if (unlikely(status > 0)) {
1385 regs->cp0_epc = old_epc; /* Undo skip-over. */
1386 regs->regs[31] = old31;
1387 force_sig(status, current);
1394 * The COP3 opcode space and consequently the CP0.Status.CU3
1395 * bit and the CP0.Cause.CE=3 encoding have been removed as
1396 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1397 * up the space has been reused for COP1X instructions, that
1398 * are enabled by the CP0.Status.CU1 bit and consequently
1399 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1400 * exceptions. Some FPU-less processors that implement one
1401 * of these ISAs however use this code erroneously for COP1X
1402 * instructions. Therefore we redirect this trap to the FP
1405 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1406 force_sig(SIGILL, current);
1412 err = enable_restore_fp_context(0);
1414 if (raw_cpu_has_fpu && !err)
1417 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0,
1419 fcr31 = current->thread.fpu.fcr31;
1422 * We can't allow the emulated instruction to leave
1423 * any of the cause bits set in $fcr31.
1425 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
1427 /* Send a signal if required. */
1428 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1429 mt_ase_fp_affinity();
1434 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1438 exception_exit(prev_state);
1441 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
1443 enum ctx_state prev_state;
1445 prev_state = exception_enter();
1446 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
1447 regs_to_trapnr(regs), SIGFPE) == NOTIFY_STOP)
1450 /* Clear MSACSR.Cause before enabling interrupts */
1451 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1454 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1455 force_sig(SIGFPE, current);
1457 exception_exit(prev_state);
1460 asmlinkage void do_msa(struct pt_regs *regs)
1462 enum ctx_state prev_state;
1465 prev_state = exception_enter();
1467 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1468 force_sig(SIGILL, current);
1472 die_if_kernel("do_msa invoked from kernel context!", regs);
1474 err = enable_restore_fp_context(1);
1476 force_sig(SIGILL, current);
1478 exception_exit(prev_state);
1481 asmlinkage void do_mdmx(struct pt_regs *regs)
1483 enum ctx_state prev_state;
1485 prev_state = exception_enter();
1486 force_sig(SIGILL, current);
1487 exception_exit(prev_state);
1491 * Called with interrupts disabled.
1493 asmlinkage void do_watch(struct pt_regs *regs)
1495 enum ctx_state prev_state;
1498 prev_state = exception_enter();
1500 * Clear WP (bit 22) bit of cause register so we don't loop
1503 cause = read_c0_cause();
1504 cause &= ~(1 << 22);
1505 write_c0_cause(cause);
1508 * If the current thread has the watch registers loaded, save
1509 * their values and send SIGTRAP. Otherwise another thread
1510 * left the registers set, clear them and continue.
1512 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1513 mips_read_watch_registers();
1515 force_sig(SIGTRAP, current);
1517 mips_clear_watch_registers();
1520 exception_exit(prev_state);
1523 asmlinkage void do_mcheck(struct pt_regs *regs)
1525 const int field = 2 * sizeof(unsigned long);
1526 int multi_match = regs->cp0_status & ST0_TS;
1527 enum ctx_state prev_state;
1528 mm_segment_t old_fs = get_fs();
1530 prev_state = exception_enter();
1534 pr_err("Index : %0x\n", read_c0_index());
1535 pr_err("Pagemask: %0x\n", read_c0_pagemask());
1536 pr_err("EntryHi : %0*lx\n", field, read_c0_entryhi());
1537 pr_err("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1538 pr_err("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1539 pr_err("Wired : %0x\n", read_c0_wired());
1540 pr_err("Pagegrain: %0x\n", read_c0_pagegrain());
1542 pr_err("PWField : %0*lx\n", field, read_c0_pwfield());
1543 pr_err("PWSize : %0*lx\n", field, read_c0_pwsize());
1544 pr_err("PWCtl : %0x\n", read_c0_pwctl());
1550 if (!user_mode(regs))
1553 show_code((unsigned int __user *) regs->cp0_epc);
1558 * Some chips may have other causes of machine check (e.g. SB1
1561 panic("Caught Machine Check exception - %scaused by multiple "
1562 "matching entries in the TLB.",
1563 (multi_match) ? "" : "not ");
1566 asmlinkage void do_mt(struct pt_regs *regs)
1570 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1571 >> VPECONTROL_EXCPT_SHIFT;
1574 printk(KERN_DEBUG "Thread Underflow\n");
1577 printk(KERN_DEBUG "Thread Overflow\n");
1580 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1583 printk(KERN_DEBUG "Gating Storage Exception\n");
1586 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1589 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1592 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1596 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1598 force_sig(SIGILL, current);
1602 asmlinkage void do_dsp(struct pt_regs *regs)
1605 panic("Unexpected DSP exception");
1607 force_sig(SIGILL, current);
1610 asmlinkage void do_reserved(struct pt_regs *regs)
1613 * Game over - no way to handle this if it ever occurs. Most probably
1614 * caused by a new unknown cpu type or after another deadly
1615 * hard/software error.
1618 panic("Caught reserved exception %ld - should not happen.",
1619 (regs->cp0_cause & 0x7f) >> 2);
1622 static int __initdata l1parity = 1;
1623 static int __init nol1parity(char *s)
1628 __setup("nol1par", nol1parity);
1629 static int __initdata l2parity = 1;
1630 static int __init nol2parity(char *s)
1635 __setup("nol2par", nol2parity);
1638 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1639 * it different ways.
1641 static inline void parity_protection_init(void)
1643 switch (current_cpu_type()) {
1649 case CPU_INTERAPTIV:
1652 case CPU_QEMU_GENERIC:
1654 #define ERRCTL_PE 0x80000000
1655 #define ERRCTL_L2P 0x00800000
1656 unsigned long errctl;
1657 unsigned int l1parity_present, l2parity_present;
1659 errctl = read_c0_ecc();
1660 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1662 /* probe L1 parity support */
1663 write_c0_ecc(errctl | ERRCTL_PE);
1664 back_to_back_c0_hazard();
1665 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1667 /* probe L2 parity support */
1668 write_c0_ecc(errctl|ERRCTL_L2P);
1669 back_to_back_c0_hazard();
1670 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1672 if (l1parity_present && l2parity_present) {
1674 errctl |= ERRCTL_PE;
1675 if (l1parity ^ l2parity)
1676 errctl |= ERRCTL_L2P;
1677 } else if (l1parity_present) {
1679 errctl |= ERRCTL_PE;
1680 } else if (l2parity_present) {
1682 errctl |= ERRCTL_L2P;
1684 /* No parity available */
1687 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1689 write_c0_ecc(errctl);
1690 back_to_back_c0_hazard();
1691 errctl = read_c0_ecc();
1692 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1694 if (l1parity_present)
1695 printk(KERN_INFO "Cache parity protection %sabled\n",
1696 (errctl & ERRCTL_PE) ? "en" : "dis");
1698 if (l2parity_present) {
1699 if (l1parity_present && l1parity)
1700 errctl ^= ERRCTL_L2P;
1701 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1702 (errctl & ERRCTL_L2P) ? "en" : "dis");
1710 write_c0_ecc(0x80000000);
1711 back_to_back_c0_hazard();
1712 /* Set the PE bit (bit 31) in the c0_errctl register. */
1713 printk(KERN_INFO "Cache parity protection %sabled\n",
1714 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1718 /* Clear the DE bit (bit 16) in the c0_status register. */
1719 printk(KERN_INFO "Enable cache parity protection for "
1720 "MIPS 20KC/25KF CPUs.\n");
1721 clear_c0_status(ST0_DE);
1728 asmlinkage void cache_parity_error(void)
1730 const int field = 2 * sizeof(unsigned long);
1731 unsigned int reg_val;
1733 /* For the moment, report the problem and hang. */
1734 printk("Cache error exception:\n");
1735 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1736 reg_val = read_c0_cacheerr();
1737 printk("c0_cacheerr == %08x\n", reg_val);
1739 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1740 reg_val & (1<<30) ? "secondary" : "primary",
1741 reg_val & (1<<31) ? "data" : "insn");
1742 if ((cpu_has_mips_r2_r6) &&
1743 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1744 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1745 reg_val & (1<<29) ? "ED " : "",
1746 reg_val & (1<<28) ? "ET " : "",
1747 reg_val & (1<<27) ? "ES " : "",
1748 reg_val & (1<<26) ? "EE " : "",
1749 reg_val & (1<<25) ? "EB " : "",
1750 reg_val & (1<<24) ? "EI " : "",
1751 reg_val & (1<<23) ? "E1 " : "",
1752 reg_val & (1<<22) ? "E0 " : "");
1754 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1755 reg_val & (1<<29) ? "ED " : "",
1756 reg_val & (1<<28) ? "ET " : "",
1757 reg_val & (1<<26) ? "EE " : "",
1758 reg_val & (1<<25) ? "EB " : "",
1759 reg_val & (1<<24) ? "EI " : "",
1760 reg_val & (1<<23) ? "E1 " : "",
1761 reg_val & (1<<22) ? "E0 " : "");
1763 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1765 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1766 if (reg_val & (1<<22))
1767 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1769 if (reg_val & (1<<23))
1770 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1773 panic("Can't handle the cache error!");
1776 asmlinkage void do_ftlb(void)
1778 const int field = 2 * sizeof(unsigned long);
1779 unsigned int reg_val;
1781 /* For the moment, report the problem and hang. */
1782 if ((cpu_has_mips_r2_r6) &&
1783 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1784 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1786 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1787 reg_val = read_c0_cacheerr();
1788 pr_err("c0_cacheerr == %08x\n", reg_val);
1790 if ((reg_val & 0xc0000000) == 0xc0000000) {
1791 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1793 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1794 reg_val & (1<<30) ? "secondary" : "primary",
1795 reg_val & (1<<31) ? "data" : "insn");
1798 pr_err("FTLB error exception\n");
1800 /* Just print the cacheerr bits for now */
1801 cache_parity_error();
1805 * SDBBP EJTAG debug exception handler.
1806 * We skip the instruction and return to the next instruction.
1808 void ejtag_exception_handler(struct pt_regs *regs)
1810 const int field = 2 * sizeof(unsigned long);
1811 unsigned long depc, old_epc, old_ra;
1814 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1815 depc = read_c0_depc();
1816 debug = read_c0_debug();
1817 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1818 if (debug & 0x80000000) {
1820 * In branch delay slot.
1821 * We cheat a little bit here and use EPC to calculate the
1822 * debug return address (DEPC). EPC is restored after the
1825 old_epc = regs->cp0_epc;
1826 old_ra = regs->regs[31];
1827 regs->cp0_epc = depc;
1828 compute_return_epc(regs);
1829 depc = regs->cp0_epc;
1830 regs->cp0_epc = old_epc;
1831 regs->regs[31] = old_ra;
1834 write_c0_depc(depc);
1837 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1838 write_c0_debug(debug | 0x100);
1843 * NMI exception handler.
1844 * No lock; only written during early bootup by CPU 0.
1846 static RAW_NOTIFIER_HEAD(nmi_chain);
1848 int register_nmi_notifier(struct notifier_block *nb)
1850 return raw_notifier_chain_register(&nmi_chain, nb);
1853 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1857 raw_notifier_call_chain(&nmi_chain, 0, regs);
1859 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1860 smp_processor_id(), regs->cp0_epc);
1861 regs->cp0_epc = read_c0_errorepc();
1865 #define VECTORSPACING 0x100 /* for EI/VI mode */
1867 unsigned long ebase;
1868 unsigned long exception_handlers[32];
1869 unsigned long vi_handlers[64];
1871 void __init *set_except_vector(int n, void *addr)
1873 unsigned long handler = (unsigned long) addr;
1874 unsigned long old_handler;
1876 #ifdef CONFIG_CPU_MICROMIPS
1878 * Only the TLB handlers are cache aligned with an even
1879 * address. All other handlers are on an odd address and
1880 * require no modification. Otherwise, MIPS32 mode will
1881 * be entered when handling any TLB exceptions. That
1882 * would be bad...since we must stay in microMIPS mode.
1884 if (!(handler & 0x1))
1887 old_handler = xchg(&exception_handlers[n], handler);
1889 if (n == 0 && cpu_has_divec) {
1890 #ifdef CONFIG_CPU_MICROMIPS
1891 unsigned long jump_mask = ~((1 << 27) - 1);
1893 unsigned long jump_mask = ~((1 << 28) - 1);
1895 u32 *buf = (u32 *)(ebase + 0x200);
1896 unsigned int k0 = 26;
1897 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1898 uasm_i_j(&buf, handler & ~jump_mask);
1901 UASM_i_LA(&buf, k0, handler);
1902 uasm_i_jr(&buf, k0);
1905 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1907 return (void *)old_handler;
1910 static void do_default_vi(void)
1912 show_regs(get_irq_regs());
1913 panic("Caught unexpected vectored interrupt.");
1916 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1918 unsigned long handler;
1919 unsigned long old_handler = vi_handlers[n];
1920 int srssets = current_cpu_data.srsets;
1924 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1927 handler = (unsigned long) do_default_vi;
1930 handler = (unsigned long) addr;
1931 vi_handlers[n] = handler;
1933 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1936 panic("Shadow register set %d not supported", srs);
1939 if (board_bind_eic_interrupt)
1940 board_bind_eic_interrupt(n, srs);
1941 } else if (cpu_has_vint) {
1942 /* SRSMap is only defined if shadow sets are implemented */
1944 change_c0_srsmap(0xf << n*4, srs << n*4);
1949 * If no shadow set is selected then use the default handler
1950 * that does normal register saving and standard interrupt exit
1952 extern char except_vec_vi, except_vec_vi_lui;
1953 extern char except_vec_vi_ori, except_vec_vi_end;
1954 extern char rollback_except_vec_vi;
1955 char *vec_start = using_rollback_handler() ?
1956 &rollback_except_vec_vi : &except_vec_vi;
1957 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1958 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1959 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1961 const int lui_offset = &except_vec_vi_lui - vec_start;
1962 const int ori_offset = &except_vec_vi_ori - vec_start;
1964 const int handler_len = &except_vec_vi_end - vec_start;
1966 if (handler_len > VECTORSPACING) {
1968 * Sigh... panicing won't help as the console
1969 * is probably not configured :(
1971 panic("VECTORSPACING too small");
1974 set_handler(((unsigned long)b - ebase), vec_start,
1975 #ifdef CONFIG_CPU_MICROMIPS
1980 h = (u16 *)(b + lui_offset);
1981 *h = (handler >> 16) & 0xffff;
1982 h = (u16 *)(b + ori_offset);
1983 *h = (handler & 0xffff);
1984 local_flush_icache_range((unsigned long)b,
1985 (unsigned long)(b+handler_len));
1989 * In other cases jump directly to the interrupt handler. It
1990 * is the handler's responsibility to save registers if required
1991 * (eg hi/lo) and return from the exception using "eret".
1997 #ifdef CONFIG_CPU_MICROMIPS
1998 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
2000 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
2002 h[0] = (insn >> 16) & 0xffff;
2003 h[1] = insn & 0xffff;
2006 local_flush_icache_range((unsigned long)b,
2007 (unsigned long)(b+8));
2010 return (void *)old_handler;
2013 void *set_vi_handler(int n, vi_handler_t addr)
2015 return set_vi_srs_handler(n, addr, 0);
2018 extern void tlb_init(void);
2023 int cp0_compare_irq;
2024 EXPORT_SYMBOL_GPL(cp0_compare_irq);
2025 int cp0_compare_irq_shift;
2028 * Performance counter IRQ or -1 if shared with timer
2030 int cp0_perfcount_irq;
2031 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2034 * Fast debug channel IRQ or -1 if not present
2037 EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2041 static int __init ulri_disable(char *s)
2043 pr_info("Disabling ulri\n");
2048 __setup("noulri", ulri_disable);
2050 /* configure STATUS register */
2051 static void configure_status(void)
2054 * Disable coprocessors and select 32-bit or 64-bit addressing
2055 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2056 * flag that some firmware may have left set and the TS bit (for
2057 * IP27). Set XX for ISA IV code to work.
2059 unsigned int status_set = ST0_CU0;
2061 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2063 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
2064 status_set |= ST0_XX;
2066 status_set |= ST0_MX;
2068 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
2072 /* configure HWRENA register */
2073 static void configure_hwrena(void)
2075 unsigned int hwrena = cpu_hwrena_impl_bits;
2077 if (cpu_has_mips_r2_r6)
2078 hwrena |= 0x0000000f;
2080 if (!noulri && cpu_has_userlocal)
2081 hwrena |= (1 << 29);
2084 write_c0_hwrena(hwrena);
2087 static void configure_exception_vector(void)
2089 if (cpu_has_veic || cpu_has_vint) {
2090 unsigned long sr = set_c0_status(ST0_BEV);
2091 write_c0_ebase(ebase);
2092 write_c0_status(sr);
2093 /* Setting vector spacing enables EI/VI mode */
2094 change_c0_intctl(0x3e0, VECTORSPACING);
2096 if (cpu_has_divec) {
2097 if (cpu_has_mipsmt) {
2098 unsigned int vpflags = dvpe();
2099 set_c0_cause(CAUSEF_IV);
2102 set_c0_cause(CAUSEF_IV);
2106 void per_cpu_trap_init(bool is_boot_cpu)
2108 unsigned int cpu = smp_processor_id();
2113 configure_exception_vector();
2116 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2118 * o read IntCtl.IPTI to determine the timer interrupt
2119 * o read IntCtl.IPPCI to determine the performance counter interrupt
2120 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
2122 if (cpu_has_mips_r2_r6) {
2123 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2124 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2125 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2126 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2131 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2132 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2133 cp0_perfcount_irq = -1;
2137 if (!cpu_data[cpu].asid_cache)
2138 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
2140 atomic_inc(&init_mm.mm_count);
2141 current->active_mm = &init_mm;
2142 BUG_ON(current->mm);
2143 enter_lazy_tlb(&init_mm, current);
2145 /* Boot CPU's cache setup in setup_arch(). */
2149 TLBMISS_HANDLER_SETUP();
2152 /* Install CPU exception handler */
2153 void set_handler(unsigned long offset, void *addr, unsigned long size)
2155 #ifdef CONFIG_CPU_MICROMIPS
2156 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2158 memcpy((void *)(ebase + offset), addr, size);
2160 local_flush_icache_range(ebase + offset, ebase + offset + size);
2163 static char panic_null_cerr[] =
2164 "Trying to set NULL cache error exception handler";
2167 * Install uncached CPU exception handler.
2168 * This is suitable only for the cache error exception which is the only
2169 * exception handler that is being run uncached.
2171 void set_uncached_handler(unsigned long offset, void *addr,
2174 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
2177 panic(panic_null_cerr);
2179 memcpy((void *)(uncached_ebase + offset), addr, size);
2182 static int __initdata rdhwr_noopt;
2183 static int __init set_rdhwr_noopt(char *str)
2189 __setup("rdhwr_noopt", set_rdhwr_noopt);
2191 void __init trap_init(void)
2193 extern char except_vec3_generic;
2194 extern char except_vec4;
2195 extern char except_vec3_r4000;
2200 #if defined(CONFIG_KGDB)
2201 if (kgdb_early_setup)
2202 return; /* Already done */
2205 if (cpu_has_veic || cpu_has_vint) {
2206 unsigned long size = 0x200 + VECTORSPACING*64;
2207 ebase = (unsigned long)
2208 __alloc_bootmem(size, 1 << fls(size), 0);
2210 #ifdef CONFIG_KVM_GUEST
2211 #define KVM_GUEST_KSEG0 0x40000000
2212 ebase = KVM_GUEST_KSEG0;
2216 if (cpu_has_mips_r2_r6)
2217 ebase += (read_c0_ebase() & 0x3ffff000);
2220 if (cpu_has_mmips) {
2221 unsigned int config3 = read_c0_config3();
2223 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2224 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2226 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2229 if (board_ebase_setup)
2230 board_ebase_setup();
2231 per_cpu_trap_init(true);
2234 * Copy the generic exception handlers to their final destination.
2235 * This will be overriden later as suitable for a particular
2238 set_handler(0x180, &except_vec3_generic, 0x80);
2241 * Setup default vectors
2243 for (i = 0; i <= 31; i++)
2244 set_except_vector(i, handle_reserved);
2247 * Copy the EJTAG debug exception vector handler code to it's final
2250 if (cpu_has_ejtag && board_ejtag_handler_setup)
2251 board_ejtag_handler_setup();
2254 * Only some CPUs have the watch exceptions.
2257 set_except_vector(23, handle_watch);
2260 * Initialise interrupt handlers
2262 if (cpu_has_veic || cpu_has_vint) {
2263 int nvec = cpu_has_veic ? 64 : 8;
2264 for (i = 0; i < nvec; i++)
2265 set_vi_handler(i, NULL);
2267 else if (cpu_has_divec)
2268 set_handler(0x200, &except_vec4, 0x8);
2271 * Some CPUs can enable/disable for cache parity detection, but does
2272 * it different ways.
2274 parity_protection_init();
2277 * The Data Bus Errors / Instruction Bus Errors are signaled
2278 * by external hardware. Therefore these two exceptions
2279 * may have board specific handlers.
2284 set_except_vector(0, using_rollback_handler() ? rollback_handle_int
2286 set_except_vector(1, handle_tlbm);
2287 set_except_vector(2, handle_tlbl);
2288 set_except_vector(3, handle_tlbs);
2290 set_except_vector(4, handle_adel);
2291 set_except_vector(5, handle_ades);
2293 set_except_vector(6, handle_ibe);
2294 set_except_vector(7, handle_dbe);
2296 set_except_vector(8, handle_sys);
2297 set_except_vector(9, handle_bp);
2298 set_except_vector(10, rdhwr_noopt ? handle_ri :
2299 (cpu_has_vtag_icache ?
2300 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
2301 set_except_vector(11, handle_cpu);
2302 set_except_vector(12, handle_ov);
2303 set_except_vector(13, handle_tr);
2304 set_except_vector(14, handle_msa_fpe);
2306 if (current_cpu_type() == CPU_R6000 ||
2307 current_cpu_type() == CPU_R6000A) {
2309 * The R6000 is the only R-series CPU that features a machine
2310 * check exception (similar to the R4000 cache error) and
2311 * unaligned ldc1/sdc1 exception. The handlers have not been
2312 * written yet. Well, anyway there is no R6000 machine on the
2313 * current list of targets for Linux/MIPS.
2314 * (Duh, crap, there is someone with a triple R6k machine)
2316 //set_except_vector(14, handle_mc);
2317 //set_except_vector(15, handle_ndc);
2321 if (board_nmi_handler_setup)
2322 board_nmi_handler_setup();
2324 if (cpu_has_fpu && !cpu_has_nofpuex)
2325 set_except_vector(15, handle_fpe);
2327 set_except_vector(16, handle_ftlb);
2329 if (cpu_has_rixiex) {
2330 set_except_vector(19, tlb_do_page_fault_0);
2331 set_except_vector(20, tlb_do_page_fault_0);
2334 set_except_vector(21, handle_msa);
2335 set_except_vector(22, handle_mdmx);
2338 set_except_vector(24, handle_mcheck);
2341 set_except_vector(25, handle_mt);
2343 set_except_vector(26, handle_dsp);
2345 if (board_cache_error_setup)
2346 board_cache_error_setup();
2349 /* Special exception: R4[04]00 uses also the divec space. */
2350 set_handler(0x180, &except_vec3_r4000, 0x100);
2351 else if (cpu_has_4kex)
2352 set_handler(0x180, &except_vec3_generic, 0x80);
2354 set_handler(0x080, &except_vec3_generic, 0x80);
2356 local_flush_icache_range(ebase, ebase + 0x400);
2358 sort_extable(__start___dbe_table, __stop___dbe_table);
2360 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
2363 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2367 case CPU_PM_ENTER_FAILED:
2371 configure_exception_vector();
2373 /* Restore register with CPU number for TLB handlers */
2374 TLBMISS_HANDLER_RESTORE();
2382 static struct notifier_block trap_pm_notifier_block = {
2383 .notifier_call = trap_pm_notifier,
2386 static int __init trap_pm_init(void)
2388 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2390 arch_initcall(trap_pm_init);