2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (c) 2014 Imagination Technologies Ltd.
7 * Author: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
8 * Author: Markos Chandras <markos.chandras@imgtec.com>
10 * MIPS R2 user space instruction emulator for MIPS R6
13 #include <linux/bug.h>
14 #include <linux/compiler.h>
15 #include <linux/debugfs.h>
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/ptrace.h>
20 #include <linux/seq_file.h>
23 #include <asm/branch.h>
24 #include <asm/break.h>
26 #include <asm/fpu_emulator.h>
28 #include <asm/mips-r2-to-r6-emul.h>
29 #include <asm/local.h>
30 #include <asm/ptrace.h>
31 #include <asm/uaccess.h>
34 #define ADDIU "daddiu "
38 #define ADDIU "addiu "
41 #endif /* CONFIG_64BIT */
48 DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2emustats);
49 DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2bdemustats);
50 DEFINE_PER_CPU(struct mips_r2br_emulator_stats, mipsr2bremustats);
52 extern const unsigned int fpucondbit[8];
54 #define MIPS_R2_EMUL_TOTAL_PASS 10
56 int mipsr2_emulation = 0;
58 static int __init mipsr2emu_enable(char *s)
62 pr_info("MIPS R2-to-R6 Emulator Enabled!");
66 __setup("mipsr2emu", mipsr2emu_enable);
69 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
70 * for performance instead of the traditional way of using a stack trampoline
71 * which is rather slow.
72 * @regs: Process register set
75 static inline int mipsr6_emul(struct pt_regs *regs, u32 ir)
77 switch (MIPSInst_OPCODE(ir)) {
80 regs->regs[MIPSInst_RT(ir)] =
81 (s32)regs->regs[MIPSInst_RS(ir)] +
82 (s32)MIPSInst_SIMM(ir);
85 if (config_enabled(CONFIG_32BIT))
89 regs->regs[MIPSInst_RT(ir)] =
90 (s64)regs->regs[MIPSInst_RS(ir)] +
91 (s64)MIPSInst_SIMM(ir);
97 /* FPU instructions in delay slot */
100 switch (MIPSInst_FUNC(ir)) {
103 regs->regs[MIPSInst_RD(ir)] =
104 regs->regs[MIPSInst_RS(ir)] |
105 regs->regs[MIPSInst_RT(ir)];
112 regs->regs[MIPSInst_RD(ir)] =
113 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) <<
121 regs->regs[MIPSInst_RD(ir)] =
122 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) >>
130 regs->regs[MIPSInst_RD(ir)] =
131 (s32)((u32)regs->regs[MIPSInst_RS(ir)] +
132 (u32)regs->regs[MIPSInst_RT(ir)]);
139 regs->regs[MIPSInst_RD(ir)] =
140 (s32)((u32)regs->regs[MIPSInst_RS(ir)] -
141 (u32)regs->regs[MIPSInst_RT(ir)]);
144 if (config_enabled(CONFIG_32BIT) || MIPSInst_RS(ir))
148 regs->regs[MIPSInst_RD(ir)] =
149 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) <<
153 if (config_enabled(CONFIG_32BIT) || MIPSInst_RS(ir))
157 regs->regs[MIPSInst_RD(ir)] =
158 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) >>
162 if (config_enabled(CONFIG_32BIT) || MIPSInst_FD(ir))
166 regs->regs[MIPSInst_RD(ir)] =
167 (u64)regs->regs[MIPSInst_RS(ir)] +
168 (u64)regs->regs[MIPSInst_RT(ir)];
171 if (config_enabled(CONFIG_32BIT) || MIPSInst_FD(ir))
175 regs->regs[MIPSInst_RD(ir)] =
176 (s64)((u64)regs->regs[MIPSInst_RS(ir)] -
177 (u64)regs->regs[MIPSInst_RT(ir)]);
182 pr_debug("No fastpath BD emulation for instruction 0x%08x (op: %02x)\n",
183 ir, MIPSInst_OPCODE(ir));
190 * movf_func - Emulate a MOVF instruction
191 * @regs: Process register set
194 * Returns 0 since it always succeeds.
196 static int movf_func(struct pt_regs *regs, u32 ir)
201 csr = current->thread.fpu.fcr31;
202 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
204 if (((csr & cond) == 0) && MIPSInst_RD(ir))
205 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
213 * movt_func - Emulate a MOVT instruction
214 * @regs: Process register set
217 * Returns 0 since it always succeeds.
219 static int movt_func(struct pt_regs *regs, u32 ir)
224 csr = current->thread.fpu.fcr31;
225 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
227 if (((csr & cond) != 0) && MIPSInst_RD(ir))
228 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
236 * jr_func - Emulate a JR instruction.
237 * @pt_regs: Process register set
240 * Returns SIGILL if JR was in delay slot, SIGEMT if we
241 * can't compute the EPC, SIGSEGV if we can't access the
242 * userland instruction or 0 on success.
244 static int jr_func(struct pt_regs *regs, u32 ir)
247 unsigned long cepc, epc, nepc;
250 if (delay_slot(regs))
253 /* EPC after the RI/JR instruction */
254 nepc = regs->cp0_epc;
255 /* Roll back to the reserved R2 JR instruction */
258 err = __compute_return_epc(regs);
265 cepc = regs->cp0_epc;
267 /* Get DS instruction */
268 err = __get_user(nir, (u32 __user *)nepc);
272 MIPS_R2BR_STATS(jrs);
274 /* If nir == 0(NOP), then nothing else to do */
277 * Negative err means FPU instruction in BD-slot,
278 * Zero err means 'BD-slot emulation done'
279 * For anything else we go back to trampoline emulation.
281 err = mipsr6_emul(regs, nir);
283 regs->cp0_epc = nepc;
284 err = mips_dsemul(regs, nir, cepc);
287 MIPS_R2_STATS(dsemul);
295 * movz_func - Emulate a MOVZ instruction
296 * @regs: Process register set
299 * Returns 0 since it always succeeds.
301 static int movz_func(struct pt_regs *regs, u32 ir)
303 if (((regs->regs[MIPSInst_RT(ir)]) == 0) && MIPSInst_RD(ir))
304 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
311 * movn_func - Emulate a MOVZ instruction
312 * @regs: Process register set
315 * Returns 0 since it always succeeds.
317 static int movn_func(struct pt_regs *regs, u32 ir)
319 if (((regs->regs[MIPSInst_RT(ir)]) != 0) && MIPSInst_RD(ir))
320 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
327 * mfhi_func - Emulate a MFHI instruction
328 * @regs: Process register set
331 * Returns 0 since it always succeeds.
333 static int mfhi_func(struct pt_regs *regs, u32 ir)
336 regs->regs[MIPSInst_RD(ir)] = regs->hi;
344 * mthi_func - Emulate a MTHI instruction
345 * @regs: Process register set
348 * Returns 0 since it always succeeds.
350 static int mthi_func(struct pt_regs *regs, u32 ir)
352 regs->hi = regs->regs[MIPSInst_RS(ir)];
360 * mflo_func - Emulate a MFLO instruction
361 * @regs: Process register set
364 * Returns 0 since it always succeeds.
366 static int mflo_func(struct pt_regs *regs, u32 ir)
369 regs->regs[MIPSInst_RD(ir)] = regs->lo;
377 * mtlo_func - Emulate a MTLO instruction
378 * @regs: Process register set
381 * Returns 0 since it always succeeds.
383 static int mtlo_func(struct pt_regs *regs, u32 ir)
385 regs->lo = regs->regs[MIPSInst_RS(ir)];
393 * mult_func - Emulate a MULT instruction
394 * @regs: Process register set
397 * Returns 0 since it always succeeds.
399 static int mult_func(struct pt_regs *regs, u32 ir)
404 rt = regs->regs[MIPSInst_RT(ir)];
405 rs = regs->regs[MIPSInst_RS(ir)];
406 res = (s64)rt * (s64)rs;
420 * multu_func - Emulate a MULTU instruction
421 * @regs: Process register set
424 * Returns 0 since it always succeeds.
426 static int multu_func(struct pt_regs *regs, u32 ir)
431 rt = regs->regs[MIPSInst_RT(ir)];
432 rs = regs->regs[MIPSInst_RS(ir)];
433 res = (u64)rt * (u64)rs;
436 regs->hi = (s64)(res >> 32);
444 * div_func - Emulate a DIV instruction
445 * @regs: Process register set
448 * Returns 0 since it always succeeds.
450 static int div_func(struct pt_regs *regs, u32 ir)
454 rt = regs->regs[MIPSInst_RT(ir)];
455 rs = regs->regs[MIPSInst_RS(ir)];
457 regs->lo = (s64)(rs / rt);
458 regs->hi = (s64)(rs % rt);
466 * divu_func - Emulate a DIVU instruction
467 * @regs: Process register set
470 * Returns 0 since it always succeeds.
472 static int divu_func(struct pt_regs *regs, u32 ir)
476 rt = regs->regs[MIPSInst_RT(ir)];
477 rs = regs->regs[MIPSInst_RS(ir)];
479 regs->lo = (s64)(rs / rt);
480 regs->hi = (s64)(rs % rt);
488 * dmult_func - Emulate a DMULT instruction
489 * @regs: Process register set
492 * Returns 0 on success or SIGILL for 32-bit kernels.
494 static int dmult_func(struct pt_regs *regs, u32 ir)
499 if (config_enabled(CONFIG_32BIT))
502 rt = regs->regs[MIPSInst_RT(ir)];
503 rs = regs->regs[MIPSInst_RS(ir)];
507 __asm__ __volatile__(
508 "dmuh %0, %1, %2\t\n"
520 * dmultu_func - Emulate a DMULTU instruction
521 * @regs: Process register set
524 * Returns 0 on success or SIGILL for 32-bit kernels.
526 static int dmultu_func(struct pt_regs *regs, u32 ir)
531 if (config_enabled(CONFIG_32BIT))
534 rt = regs->regs[MIPSInst_RT(ir)];
535 rs = regs->regs[MIPSInst_RS(ir)];
539 __asm__ __volatile__(
540 "dmuhu %0, %1, %2\t\n"
552 * ddiv_func - Emulate a DDIV instruction
553 * @regs: Process register set
556 * Returns 0 on success or SIGILL for 32-bit kernels.
558 static int ddiv_func(struct pt_regs *regs, u32 ir)
562 if (config_enabled(CONFIG_32BIT))
565 rt = regs->regs[MIPSInst_RT(ir)];
566 rs = regs->regs[MIPSInst_RS(ir)];
577 * ddivu_func - Emulate a DDIVU instruction
578 * @regs: Process register set
581 * Returns 0 on success or SIGILL for 32-bit kernels.
583 static int ddivu_func(struct pt_regs *regs, u32 ir)
587 if (config_enabled(CONFIG_32BIT))
590 rt = regs->regs[MIPSInst_RT(ir)];
591 rs = regs->regs[MIPSInst_RS(ir)];
601 /* R6 removed instructions for the SPECIAL opcode */
602 static struct r2_decoder_table spec_op_table[] = {
603 { 0xfc1ff83f, 0x00000008, jr_func },
604 { 0xfc00ffff, 0x00000018, mult_func },
605 { 0xfc00ffff, 0x00000019, multu_func },
606 { 0xfc00ffff, 0x0000001c, dmult_func },
607 { 0xfc00ffff, 0x0000001d, dmultu_func },
608 { 0xffff07ff, 0x00000010, mfhi_func },
609 { 0xfc1fffff, 0x00000011, mthi_func },
610 { 0xffff07ff, 0x00000012, mflo_func },
611 { 0xfc1fffff, 0x00000013, mtlo_func },
612 { 0xfc0307ff, 0x00000001, movf_func },
613 { 0xfc0307ff, 0x00010001, movt_func },
614 { 0xfc0007ff, 0x0000000a, movz_func },
615 { 0xfc0007ff, 0x0000000b, movn_func },
616 { 0xfc00ffff, 0x0000001a, div_func },
617 { 0xfc00ffff, 0x0000001b, divu_func },
618 { 0xfc00ffff, 0x0000001e, ddiv_func },
619 { 0xfc00ffff, 0x0000001f, ddivu_func },
624 * madd_func - Emulate a MADD instruction
625 * @regs: Process register set
628 * Returns 0 since it always succeeds.
630 static int madd_func(struct pt_regs *regs, u32 ir)
635 rt = regs->regs[MIPSInst_RT(ir)];
636 rs = regs->regs[MIPSInst_RS(ir)];
637 res = (s64)rt * (s64)rs;
640 res += ((((s64)rt) << 32) | (u32)rs);
653 * maddu_func - Emulate a MADDU instruction
654 * @regs: Process register set
657 * Returns 0 since it always succeeds.
659 static int maddu_func(struct pt_regs *regs, u32 ir)
664 rt = regs->regs[MIPSInst_RT(ir)];
665 rs = regs->regs[MIPSInst_RS(ir)];
666 res = (u64)rt * (u64)rs;
669 res += ((((s64)rt) << 32) | (u32)rs);
682 * msub_func - Emulate a MSUB instruction
683 * @regs: Process register set
686 * Returns 0 since it always succeeds.
688 static int msub_func(struct pt_regs *regs, u32 ir)
693 rt = regs->regs[MIPSInst_RT(ir)];
694 rs = regs->regs[MIPSInst_RS(ir)];
695 res = (s64)rt * (s64)rs;
698 res = ((((s64)rt) << 32) | (u32)rs) - res;
711 * msubu_func - Emulate a MSUBU instruction
712 * @regs: Process register set
715 * Returns 0 since it always succeeds.
717 static int msubu_func(struct pt_regs *regs, u32 ir)
722 rt = regs->regs[MIPSInst_RT(ir)];
723 rs = regs->regs[MIPSInst_RS(ir)];
724 res = (u64)rt * (u64)rs;
727 res = ((((s64)rt) << 32) | (u32)rs) - res;
740 * mul_func - Emulate a MUL instruction
741 * @regs: Process register set
744 * Returns 0 since it always succeeds.
746 static int mul_func(struct pt_regs *regs, u32 ir)
751 if (!MIPSInst_RD(ir))
753 rt = regs->regs[MIPSInst_RT(ir)];
754 rs = regs->regs[MIPSInst_RS(ir)];
755 res = (s64)rt * (s64)rs;
758 regs->regs[MIPSInst_RD(ir)] = (s64)rs;
766 * clz_func - Emulate a CLZ instruction
767 * @regs: Process register set
770 * Returns 0 since it always succeeds.
772 static int clz_func(struct pt_regs *regs, u32 ir)
777 if (!MIPSInst_RD(ir))
780 rs = regs->regs[MIPSInst_RS(ir)];
781 __asm__ __volatile__("clz %0, %1" : "=r"(res) : "r"(rs));
782 regs->regs[MIPSInst_RD(ir)] = res;
790 * clo_func - Emulate a CLO instruction
791 * @regs: Process register set
794 * Returns 0 since it always succeeds.
797 static int clo_func(struct pt_regs *regs, u32 ir)
802 if (!MIPSInst_RD(ir))
805 rs = regs->regs[MIPSInst_RS(ir)];
806 __asm__ __volatile__("clo %0, %1" : "=r"(res) : "r"(rs));
807 regs->regs[MIPSInst_RD(ir)] = res;
815 * dclz_func - Emulate a DCLZ instruction
816 * @regs: Process register set
819 * Returns 0 since it always succeeds.
821 static int dclz_func(struct pt_regs *regs, u32 ir)
826 if (config_enabled(CONFIG_32BIT))
829 if (!MIPSInst_RD(ir))
832 rs = regs->regs[MIPSInst_RS(ir)];
833 __asm__ __volatile__("dclz %0, %1" : "=r"(res) : "r"(rs));
834 regs->regs[MIPSInst_RD(ir)] = res;
842 * dclo_func - Emulate a DCLO instruction
843 * @regs: Process register set
846 * Returns 0 since it always succeeds.
848 static int dclo_func(struct pt_regs *regs, u32 ir)
853 if (config_enabled(CONFIG_32BIT))
856 if (!MIPSInst_RD(ir))
859 rs = regs->regs[MIPSInst_RS(ir)];
860 __asm__ __volatile__("dclo %0, %1" : "=r"(res) : "r"(rs));
861 regs->regs[MIPSInst_RD(ir)] = res;
868 /* R6 removed instructions for the SPECIAL2 opcode */
869 static struct r2_decoder_table spec2_op_table[] = {
870 { 0xfc00ffff, 0x70000000, madd_func },
871 { 0xfc00ffff, 0x70000001, maddu_func },
872 { 0xfc0007ff, 0x70000002, mul_func },
873 { 0xfc00ffff, 0x70000004, msub_func },
874 { 0xfc00ffff, 0x70000005, msubu_func },
875 { 0xfc0007ff, 0x70000020, clz_func },
876 { 0xfc0007ff, 0x70000021, clo_func },
877 { 0xfc0007ff, 0x70000024, dclz_func },
878 { 0xfc0007ff, 0x70000025, dclo_func },
882 static inline int mipsr2_find_op_func(struct pt_regs *regs, u32 inst,
883 struct r2_decoder_table *table)
885 struct r2_decoder_table *p;
888 for (p = table; p->func; p++) {
889 if ((inst & p->mask) == p->code) {
890 err = (p->func)(regs, inst);
898 * mipsr2_decoder: Decode and emulate a MIPS R2 instruction
899 * @regs: Process register set
900 * @inst: Instruction to decode and emulate
901 * @fcr31: Floating Point Control and Status Register returned
903 int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
908 unsigned long cpc, epc, nepc, r31, res, rs, rt;
910 void __user *fault_addr = NULL;
914 r31 = regs->regs[31];
916 err = compute_return_epc(regs);
921 pr_debug("Emulating the 0x%08x R2 instruction @ 0x%08lx (pass=%d))\n",
924 switch (MIPSInst_OPCODE(inst)) {
926 err = mipsr2_find_op_func(regs, inst, spec_op_table);
928 /* FPU instruction under JR */
929 regs->cp0_cause |= CAUSEF_BD;
934 err = mipsr2_find_op_func(regs, inst, spec2_op_table);
937 rt = MIPSInst_RT(inst);
938 rs = MIPSInst_RS(inst);
941 if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst))
942 do_trap_or_bp(regs, 0, "TGEI");
944 MIPS_R2_STATS(traps);
948 if (regs->regs[rs] >= MIPSInst_UIMM(inst))
949 do_trap_or_bp(regs, 0, "TGEIU");
951 MIPS_R2_STATS(traps);
955 if ((long)regs->regs[rs] < MIPSInst_SIMM(inst))
956 do_trap_or_bp(regs, 0, "TLTI");
958 MIPS_R2_STATS(traps);
962 if (regs->regs[rs] < MIPSInst_UIMM(inst))
963 do_trap_or_bp(regs, 0, "TLTIU");
965 MIPS_R2_STATS(traps);
969 if (regs->regs[rs] == MIPSInst_SIMM(inst))
970 do_trap_or_bp(regs, 0, "TEQI");
972 MIPS_R2_STATS(traps);
976 if (regs->regs[rs] != MIPSInst_SIMM(inst))
977 do_trap_or_bp(regs, 0, "TNEI");
979 MIPS_R2_STATS(traps);
986 if (delay_slot(regs)) {
990 regs->regs[31] = r31;
992 err = __compute_return_epc(regs);
995 if (err != BRANCH_LIKELY_TAKEN)
999 err = __get_user(nir, (u32 __user *)nepc);
1005 * This will probably be optimized away when
1006 * CONFIG_DEBUG_FS is not enabled
1010 MIPS_R2BR_STATS(bltzl);
1013 MIPS_R2BR_STATS(bgezl);
1016 MIPS_R2BR_STATS(bltzall);
1019 MIPS_R2BR_STATS(bgezall);
1023 switch (MIPSInst_OPCODE(nir)) {
1028 regs->cp0_cause |= CAUSEF_BD;
1032 err = mipsr6_emul(regs, nir);
1034 err = mips_dsemul(regs, nir, cpc);
1037 MIPS_R2_STATS(dsemul);
1043 if (delay_slot(regs)) {
1047 regs->regs[31] = r31;
1048 regs->cp0_epc = epc;
1049 err = __compute_return_epc(regs);
1052 cpc = regs->cp0_epc;
1054 err = __get_user(nir, (u32 __user *)nepc);
1060 * This will probably be optimized away when
1061 * CONFIG_DEBUG_FS is not enabled
1065 MIPS_R2BR_STATS(bltzal);
1068 MIPS_R2BR_STATS(bgezal);
1072 switch (MIPSInst_OPCODE(nir)) {
1077 regs->cp0_cause |= CAUSEF_BD;
1081 err = mipsr6_emul(regs, nir);
1083 err = mips_dsemul(regs, nir, cpc);
1086 MIPS_R2_STATS(dsemul);
1091 regs->regs[31] = r31;
1092 regs->cp0_epc = epc;
1102 if (delay_slot(regs)) {
1106 regs->regs[31] = r31;
1107 regs->cp0_epc = epc;
1108 err = __compute_return_epc(regs);
1111 if (err != BRANCH_LIKELY_TAKEN)
1113 cpc = regs->cp0_epc;
1115 err = __get_user(nir, (u32 __user *)nepc);
1121 * This will probably be optimized away when
1122 * CONFIG_DEBUG_FS is not enabled
1124 switch (MIPSInst_OPCODE(inst)) {
1126 MIPS_R2BR_STATS(beql);
1129 MIPS_R2BR_STATS(bnel);
1132 MIPS_R2BR_STATS(blezl);
1135 MIPS_R2BR_STATS(bgtzl);
1139 switch (MIPSInst_OPCODE(nir)) {
1144 regs->cp0_cause |= CAUSEF_BD;
1148 err = mipsr6_emul(regs, nir);
1150 err = mips_dsemul(regs, nir, cpc);
1153 MIPS_R2_STATS(dsemul);
1162 regs->regs[31] = r31;
1163 regs->cp0_epc = epc;
1164 if (!used_math()) { /* First time FPU user. */
1168 lose_fpu(1); /* Save FPU state for the emulator. */
1170 err = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0,
1172 *fcr31 = current->thread.fpu.fcr31;
1175 * We can't allow the emulated instruction to leave any of
1176 * the cause bits set in $fcr31.
1178 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
1181 * this is a tricky issue - lose_fpu() uses LL/SC atomics
1182 * if FPU is owned and effectively cancels user level LL/SC.
1183 * So, it could be logical to don't restore FPU ownership here.
1184 * But the sequence of multiple FPU instructions is much much
1185 * more often than LL-FPU-SC and I prefer loop here until
1186 * next scheduler cycle cancels FPU ownership
1188 own_fpu(1); /* Restore FPU state. */
1191 current->thread.cp0_baduaddr = (unsigned long)fault_addr;
1193 MIPS_R2_STATS(fpus);
1198 rt = regs->regs[MIPSInst_RT(inst)];
1199 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1200 if (!access_ok(VERIFY_READ, vaddr, 4)) {
1201 current->thread.cp0_baduaddr = vaddr;
1205 __asm__ __volatile__(
1208 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1209 "1:" LB "%1, 0(%2)\n"
1210 INS "%0, %1, 24, 8\n"
1211 " andi %1, %2, 0x3\n"
1213 ADDIU "%2, %2, -1\n"
1214 "2:" LB "%1, 0(%2)\n"
1215 INS "%0, %1, 16, 8\n"
1216 " andi %1, %2, 0x3\n"
1218 ADDIU "%2, %2, -1\n"
1219 "3:" LB "%1, 0(%2)\n"
1220 INS "%0, %1, 8, 8\n"
1221 " andi %1, %2, 0x3\n"
1223 ADDIU "%2, %2, -1\n"
1224 "4:" LB "%1, 0(%2)\n"
1225 INS "%0, %1, 0, 8\n"
1226 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1227 "1:" LB "%1, 0(%2)\n"
1228 INS "%0, %1, 24, 8\n"
1230 " andi %1, %2, 0x3\n"
1232 "2:" LB "%1, 0(%2)\n"
1233 INS "%0, %1, 16, 8\n"
1235 " andi %1, %2, 0x3\n"
1237 "3:" LB "%1, 0(%2)\n"
1238 INS "%0, %1, 8, 8\n"
1240 " andi %1, %2, 0x3\n"
1242 "4:" LB "%1, 0(%2)\n"
1243 INS "%0, %1, 0, 8\n"
1244 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1245 "9: sll %0, %0, 0\n"
1248 " .section .fixup,\"ax\"\n"
1252 " .section __ex_table,\"a\"\n"
1259 : "+&r"(rt), "=&r"(rs),
1260 "+&r"(vaddr), "+&r"(err)
1263 if (MIPSInst_RT(inst) && !err)
1264 regs->regs[MIPSInst_RT(inst)] = rt;
1266 MIPS_R2_STATS(loads);
1271 rt = regs->regs[MIPSInst_RT(inst)];
1272 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1273 if (!access_ok(VERIFY_READ, vaddr, 4)) {
1274 current->thread.cp0_baduaddr = vaddr;
1278 __asm__ __volatile__(
1281 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1282 "1:" LB "%1, 0(%2)\n"
1283 INS "%0, %1, 0, 8\n"
1285 " andi %1, %2, 0x3\n"
1287 "2:" LB "%1, 0(%2)\n"
1288 INS "%0, %1, 8, 8\n"
1290 " andi %1, %2, 0x3\n"
1292 "3:" LB "%1, 0(%2)\n"
1293 INS "%0, %1, 16, 8\n"
1295 " andi %1, %2, 0x3\n"
1297 "4:" LB "%1, 0(%2)\n"
1298 INS "%0, %1, 24, 8\n"
1300 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1301 "1:" LB "%1, 0(%2)\n"
1302 INS "%0, %1, 0, 8\n"
1303 " andi %1, %2, 0x3\n"
1305 ADDIU "%2, %2, -1\n"
1306 "2:" LB "%1, 0(%2)\n"
1307 INS "%0, %1, 8, 8\n"
1308 " andi %1, %2, 0x3\n"
1310 ADDIU "%2, %2, -1\n"
1311 "3:" LB "%1, 0(%2)\n"
1312 INS "%0, %1, 16, 8\n"
1313 " andi %1, %2, 0x3\n"
1315 ADDIU "%2, %2, -1\n"
1316 "4:" LB "%1, 0(%2)\n"
1317 INS "%0, %1, 24, 8\n"
1319 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1323 " .section .fixup,\"ax\"\n"
1327 " .section __ex_table,\"a\"\n"
1334 : "+&r"(rt), "=&r"(rs),
1335 "+&r"(vaddr), "+&r"(err)
1337 if (MIPSInst_RT(inst) && !err)
1338 regs->regs[MIPSInst_RT(inst)] = rt;
1340 MIPS_R2_STATS(loads);
1345 rt = regs->regs[MIPSInst_RT(inst)];
1346 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1347 if (!access_ok(VERIFY_WRITE, vaddr, 4)) {
1348 current->thread.cp0_baduaddr = vaddr;
1352 __asm__ __volatile__(
1355 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1356 EXT "%1, %0, 24, 8\n"
1357 "1:" SB "%1, 0(%2)\n"
1358 " andi %1, %2, 0x3\n"
1360 ADDIU "%2, %2, -1\n"
1361 EXT "%1, %0, 16, 8\n"
1362 "2:" SB "%1, 0(%2)\n"
1363 " andi %1, %2, 0x3\n"
1365 ADDIU "%2, %2, -1\n"
1366 EXT "%1, %0, 8, 8\n"
1367 "3:" SB "%1, 0(%2)\n"
1368 " andi %1, %2, 0x3\n"
1370 ADDIU "%2, %2, -1\n"
1371 EXT "%1, %0, 0, 8\n"
1372 "4:" SB "%1, 0(%2)\n"
1373 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1374 EXT "%1, %0, 24, 8\n"
1375 "1:" SB "%1, 0(%2)\n"
1377 " andi %1, %2, 0x3\n"
1379 EXT "%1, %0, 16, 8\n"
1380 "2:" SB "%1, 0(%2)\n"
1382 " andi %1, %2, 0x3\n"
1384 EXT "%1, %0, 8, 8\n"
1385 "3:" SB "%1, 0(%2)\n"
1387 " andi %1, %2, 0x3\n"
1389 EXT "%1, %0, 0, 8\n"
1390 "4:" SB "%1, 0(%2)\n"
1391 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1394 " .section .fixup,\"ax\"\n"
1398 " .section __ex_table,\"a\"\n"
1405 : "+&r"(rt), "=&r"(rs),
1406 "+&r"(vaddr), "+&r"(err)
1410 MIPS_R2_STATS(stores);
1415 rt = regs->regs[MIPSInst_RT(inst)];
1416 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1417 if (!access_ok(VERIFY_WRITE, vaddr, 4)) {
1418 current->thread.cp0_baduaddr = vaddr;
1422 __asm__ __volatile__(
1425 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1426 EXT "%1, %0, 0, 8\n"
1427 "1:" SB "%1, 0(%2)\n"
1429 " andi %1, %2, 0x3\n"
1431 EXT "%1, %0, 8, 8\n"
1432 "2:" SB "%1, 0(%2)\n"
1434 " andi %1, %2, 0x3\n"
1436 EXT "%1, %0, 16, 8\n"
1437 "3:" SB "%1, 0(%2)\n"
1439 " andi %1, %2, 0x3\n"
1441 EXT "%1, %0, 24, 8\n"
1442 "4:" SB "%1, 0(%2)\n"
1443 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1444 EXT "%1, %0, 0, 8\n"
1445 "1:" SB "%1, 0(%2)\n"
1446 " andi %1, %2, 0x3\n"
1448 ADDIU "%2, %2, -1\n"
1449 EXT "%1, %0, 8, 8\n"
1450 "2:" SB "%1, 0(%2)\n"
1451 " andi %1, %2, 0x3\n"
1453 ADDIU "%2, %2, -1\n"
1454 EXT "%1, %0, 16, 8\n"
1455 "3:" SB "%1, 0(%2)\n"
1456 " andi %1, %2, 0x3\n"
1458 ADDIU "%2, %2, -1\n"
1459 EXT "%1, %0, 24, 8\n"
1460 "4:" SB "%1, 0(%2)\n"
1461 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1464 " .section .fixup,\"ax\"\n"
1468 " .section __ex_table,\"a\"\n"
1475 : "+&r"(rt), "=&r"(rs),
1476 "+&r"(vaddr), "+&r"(err)
1480 MIPS_R2_STATS(stores);
1485 if (config_enabled(CONFIG_32BIT)) {
1490 rt = regs->regs[MIPSInst_RT(inst)];
1491 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1492 if (!access_ok(VERIFY_READ, vaddr, 8)) {
1493 current->thread.cp0_baduaddr = vaddr;
1497 __asm__ __volatile__(
1500 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1502 " dinsu %0, %1, 56, 8\n"
1503 " andi %1, %2, 0x7\n"
1505 " daddiu %2, %2, -1\n"
1507 " dinsu %0, %1, 48, 8\n"
1508 " andi %1, %2, 0x7\n"
1510 " daddiu %2, %2, -1\n"
1512 " dinsu %0, %1, 40, 8\n"
1513 " andi %1, %2, 0x7\n"
1515 " daddiu %2, %2, -1\n"
1517 " dinsu %0, %1, 32, 8\n"
1518 " andi %1, %2, 0x7\n"
1520 " daddiu %2, %2, -1\n"
1522 " dins %0, %1, 24, 8\n"
1523 " andi %1, %2, 0x7\n"
1525 " daddiu %2, %2, -1\n"
1527 " dins %0, %1, 16, 8\n"
1528 " andi %1, %2, 0x7\n"
1530 " daddiu %2, %2, -1\n"
1532 " dins %0, %1, 8, 8\n"
1533 " andi %1, %2, 0x7\n"
1535 " daddiu %2, %2, -1\n"
1537 " dins %0, %1, 0, 8\n"
1538 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1540 " dinsu %0, %1, 56, 8\n"
1541 " daddiu %2, %2, 1\n"
1542 " andi %1, %2, 0x7\n"
1545 " dinsu %0, %1, 48, 8\n"
1546 " daddiu %2, %2, 1\n"
1547 " andi %1, %2, 0x7\n"
1550 " dinsu %0, %1, 40, 8\n"
1551 " daddiu %2, %2, 1\n"
1552 " andi %1, %2, 0x7\n"
1555 " dinsu %0, %1, 32, 8\n"
1556 " daddiu %2, %2, 1\n"
1557 " andi %1, %2, 0x7\n"
1560 " dins %0, %1, 24, 8\n"
1561 " daddiu %2, %2, 1\n"
1562 " andi %1, %2, 0x7\n"
1565 " dins %0, %1, 16, 8\n"
1566 " daddiu %2, %2, 1\n"
1567 " andi %1, %2, 0x7\n"
1570 " dins %0, %1, 8, 8\n"
1571 " daddiu %2, %2, 1\n"
1572 " andi %1, %2, 0x7\n"
1575 " dins %0, %1, 0, 8\n"
1576 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1579 " .section .fixup,\"ax\"\n"
1583 " .section __ex_table,\"a\"\n"
1594 : "+&r"(rt), "=&r"(rs),
1595 "+&r"(vaddr), "+&r"(err)
1597 if (MIPSInst_RT(inst) && !err)
1598 regs->regs[MIPSInst_RT(inst)] = rt;
1600 MIPS_R2_STATS(loads);
1604 if (config_enabled(CONFIG_32BIT)) {
1609 rt = regs->regs[MIPSInst_RT(inst)];
1610 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1611 if (!access_ok(VERIFY_READ, vaddr, 8)) {
1612 current->thread.cp0_baduaddr = vaddr;
1616 __asm__ __volatile__(
1619 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1621 " dins %0, %1, 0, 8\n"
1622 " daddiu %2, %2, 1\n"
1623 " andi %1, %2, 0x7\n"
1626 " dins %0, %1, 8, 8\n"
1627 " daddiu %2, %2, 1\n"
1628 " andi %1, %2, 0x7\n"
1631 " dins %0, %1, 16, 8\n"
1632 " daddiu %2, %2, 1\n"
1633 " andi %1, %2, 0x7\n"
1636 " dins %0, %1, 24, 8\n"
1637 " daddiu %2, %2, 1\n"
1638 " andi %1, %2, 0x7\n"
1641 " dinsu %0, %1, 32, 8\n"
1642 " daddiu %2, %2, 1\n"
1643 " andi %1, %2, 0x7\n"
1646 " dinsu %0, %1, 40, 8\n"
1647 " daddiu %2, %2, 1\n"
1648 " andi %1, %2, 0x7\n"
1651 " dinsu %0, %1, 48, 8\n"
1652 " daddiu %2, %2, 1\n"
1653 " andi %1, %2, 0x7\n"
1656 " dinsu %0, %1, 56, 8\n"
1657 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1659 " dins %0, %1, 0, 8\n"
1660 " andi %1, %2, 0x7\n"
1662 " daddiu %2, %2, -1\n"
1664 " dins %0, %1, 8, 8\n"
1665 " andi %1, %2, 0x7\n"
1667 " daddiu %2, %2, -1\n"
1669 " dins %0, %1, 16, 8\n"
1670 " andi %1, %2, 0x7\n"
1672 " daddiu %2, %2, -1\n"
1674 " dins %0, %1, 24, 8\n"
1675 " andi %1, %2, 0x7\n"
1677 " daddiu %2, %2, -1\n"
1679 " dinsu %0, %1, 32, 8\n"
1680 " andi %1, %2, 0x7\n"
1682 " daddiu %2, %2, -1\n"
1684 " dinsu %0, %1, 40, 8\n"
1685 " andi %1, %2, 0x7\n"
1687 " daddiu %2, %2, -1\n"
1689 " dinsu %0, %1, 48, 8\n"
1690 " andi %1, %2, 0x7\n"
1692 " daddiu %2, %2, -1\n"
1694 " dinsu %0, %1, 56, 8\n"
1695 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1698 " .section .fixup,\"ax\"\n"
1702 " .section __ex_table,\"a\"\n"
1713 : "+&r"(rt), "=&r"(rs),
1714 "+&r"(vaddr), "+&r"(err)
1716 if (MIPSInst_RT(inst) && !err)
1717 regs->regs[MIPSInst_RT(inst)] = rt;
1719 MIPS_R2_STATS(loads);
1723 if (config_enabled(CONFIG_32BIT)) {
1728 rt = regs->regs[MIPSInst_RT(inst)];
1729 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1730 if (!access_ok(VERIFY_WRITE, vaddr, 8)) {
1731 current->thread.cp0_baduaddr = vaddr;
1735 __asm__ __volatile__(
1738 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1739 " dextu %1, %0, 56, 8\n"
1741 " andi %1, %2, 0x7\n"
1743 " daddiu %2, %2, -1\n"
1744 " dextu %1, %0, 48, 8\n"
1746 " andi %1, %2, 0x7\n"
1748 " daddiu %2, %2, -1\n"
1749 " dextu %1, %0, 40, 8\n"
1751 " andi %1, %2, 0x7\n"
1753 " daddiu %2, %2, -1\n"
1754 " dextu %1, %0, 32, 8\n"
1756 " andi %1, %2, 0x7\n"
1758 " daddiu %2, %2, -1\n"
1759 " dext %1, %0, 24, 8\n"
1761 " andi %1, %2, 0x7\n"
1763 " daddiu %2, %2, -1\n"
1764 " dext %1, %0, 16, 8\n"
1766 " andi %1, %2, 0x7\n"
1768 " daddiu %2, %2, -1\n"
1769 " dext %1, %0, 8, 8\n"
1771 " andi %1, %2, 0x7\n"
1773 " daddiu %2, %2, -1\n"
1774 " dext %1, %0, 0, 8\n"
1776 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1777 " dextu %1, %0, 56, 8\n"
1779 " daddiu %2, %2, 1\n"
1780 " andi %1, %2, 0x7\n"
1782 " dextu %1, %0, 48, 8\n"
1784 " daddiu %2, %2, 1\n"
1785 " andi %1, %2, 0x7\n"
1787 " dextu %1, %0, 40, 8\n"
1789 " daddiu %2, %2, 1\n"
1790 " andi %1, %2, 0x7\n"
1792 " dextu %1, %0, 32, 8\n"
1794 " daddiu %2, %2, 1\n"
1795 " andi %1, %2, 0x7\n"
1797 " dext %1, %0, 24, 8\n"
1799 " daddiu %2, %2, 1\n"
1800 " andi %1, %2, 0x7\n"
1802 " dext %1, %0, 16, 8\n"
1804 " daddiu %2, %2, 1\n"
1805 " andi %1, %2, 0x7\n"
1807 " dext %1, %0, 8, 8\n"
1809 " daddiu %2, %2, 1\n"
1810 " andi %1, %2, 0x7\n"
1812 " dext %1, %0, 0, 8\n"
1814 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1817 " .section .fixup,\"ax\"\n"
1821 " .section __ex_table,\"a\"\n"
1832 : "+&r"(rt), "=&r"(rs),
1833 "+&r"(vaddr), "+&r"(err)
1837 MIPS_R2_STATS(stores);
1841 if (config_enabled(CONFIG_32BIT)) {
1846 rt = regs->regs[MIPSInst_RT(inst)];
1847 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1848 if (!access_ok(VERIFY_WRITE, vaddr, 8)) {
1849 current->thread.cp0_baduaddr = vaddr;
1853 __asm__ __volatile__(
1856 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1857 " dext %1, %0, 0, 8\n"
1859 " daddiu %2, %2, 1\n"
1860 " andi %1, %2, 0x7\n"
1862 " dext %1, %0, 8, 8\n"
1864 " daddiu %2, %2, 1\n"
1865 " andi %1, %2, 0x7\n"
1867 " dext %1, %0, 16, 8\n"
1869 " daddiu %2, %2, 1\n"
1870 " andi %1, %2, 0x7\n"
1872 " dext %1, %0, 24, 8\n"
1874 " daddiu %2, %2, 1\n"
1875 " andi %1, %2, 0x7\n"
1877 " dextu %1, %0, 32, 8\n"
1879 " daddiu %2, %2, 1\n"
1880 " andi %1, %2, 0x7\n"
1882 " dextu %1, %0, 40, 8\n"
1884 " daddiu %2, %2, 1\n"
1885 " andi %1, %2, 0x7\n"
1887 " dextu %1, %0, 48, 8\n"
1889 " daddiu %2, %2, 1\n"
1890 " andi %1, %2, 0x7\n"
1892 " dextu %1, %0, 56, 8\n"
1894 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1895 " dext %1, %0, 0, 8\n"
1897 " andi %1, %2, 0x7\n"
1899 " daddiu %2, %2, -1\n"
1900 " dext %1, %0, 8, 8\n"
1902 " andi %1, %2, 0x7\n"
1904 " daddiu %2, %2, -1\n"
1905 " dext %1, %0, 16, 8\n"
1907 " andi %1, %2, 0x7\n"
1909 " daddiu %2, %2, -1\n"
1910 " dext %1, %0, 24, 8\n"
1912 " andi %1, %2, 0x7\n"
1914 " daddiu %2, %2, -1\n"
1915 " dextu %1, %0, 32, 8\n"
1917 " andi %1, %2, 0x7\n"
1919 " daddiu %2, %2, -1\n"
1920 " dextu %1, %0, 40, 8\n"
1922 " andi %1, %2, 0x7\n"
1924 " daddiu %2, %2, -1\n"
1925 " dextu %1, %0, 48, 8\n"
1927 " andi %1, %2, 0x7\n"
1929 " daddiu %2, %2, -1\n"
1930 " dextu %1, %0, 56, 8\n"
1932 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1935 " .section .fixup,\"ax\"\n"
1939 " .section __ex_table,\"a\"\n"
1950 : "+&r"(rt), "=&r"(rs),
1951 "+&r"(vaddr), "+&r"(err)
1955 MIPS_R2_STATS(stores);
1959 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1961 current->thread.cp0_baduaddr = vaddr;
1965 if (!access_ok(VERIFY_READ, vaddr, 4)) {
1966 current->thread.cp0_baduaddr = vaddr;
1971 if (!cpu_has_rw_llb) {
1973 * An LL/SC block can't be safely emulated without
1974 * a Config5/LLB availability. So it's probably time to
1975 * kill our process before things get any worse. This is
1976 * because Config5/LLB allows us to use ERETNC so that
1977 * the LLAddr/LLB bit is not cleared when we return from
1978 * an exception. MIPS R2 LL/SC instructions trap with an
1979 * RI exception so once we emulate them here, we return
1980 * back to userland with ERETNC. That preserves the
1981 * LLAddr/LLB so the subsequent SC instruction will
1982 * succeed preserving the atomic semantics of the LL/SC
1983 * block. Without that, there is no safe way to emulate
1984 * an LL/SC block in MIPSR2 userland.
1986 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
1991 __asm__ __volatile__(
1996 ".section .fixup,\"ax\"\n"
2001 ".section __ex_table,\"a\"\n"
2004 : "=&r"(res), "+&r"(err)
2005 : "r"(vaddr), "i"(SIGSEGV)
2008 if (MIPSInst_RT(inst) && !err)
2009 regs->regs[MIPSInst_RT(inst)] = res;
2010 MIPS_R2_STATS(llsc);
2015 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
2017 current->thread.cp0_baduaddr = vaddr;
2021 if (!access_ok(VERIFY_WRITE, vaddr, 4)) {
2022 current->thread.cp0_baduaddr = vaddr;
2027 if (!cpu_has_rw_llb) {
2029 * An LL/SC block can't be safely emulated without
2030 * a Config5/LLB availability. So it's probably time to
2031 * kill our process before things get any worse. This is
2032 * because Config5/LLB allows us to use ERETNC so that
2033 * the LLAddr/LLB bit is not cleared when we return from
2034 * an exception. MIPS R2 LL/SC instructions trap with an
2035 * RI exception so once we emulate them here, we return
2036 * back to userland with ERETNC. That preserves the
2037 * LLAddr/LLB so the subsequent SC instruction will
2038 * succeed preserving the atomic semantics of the LL/SC
2039 * block. Without that, there is no safe way to emulate
2040 * an LL/SC block in MIPSR2 userland.
2042 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2047 res = regs->regs[MIPSInst_RT(inst)];
2049 __asm__ __volatile__(
2054 ".section .fixup,\"ax\"\n"
2059 ".section __ex_table,\"a\"\n"
2062 : "+&r"(res), "+&r"(err)
2063 : "r"(vaddr), "i"(SIGSEGV));
2065 if (MIPSInst_RT(inst) && !err)
2066 regs->regs[MIPSInst_RT(inst)] = res;
2068 MIPS_R2_STATS(llsc);
2073 if (config_enabled(CONFIG_32BIT)) {
2078 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
2080 current->thread.cp0_baduaddr = vaddr;
2084 if (!access_ok(VERIFY_READ, vaddr, 8)) {
2085 current->thread.cp0_baduaddr = vaddr;
2090 if (!cpu_has_rw_llb) {
2092 * An LL/SC block can't be safely emulated without
2093 * a Config5/LLB availability. So it's probably time to
2094 * kill our process before things get any worse. This is
2095 * because Config5/LLB allows us to use ERETNC so that
2096 * the LLAddr/LLB bit is not cleared when we return from
2097 * an exception. MIPS R2 LL/SC instructions trap with an
2098 * RI exception so once we emulate them here, we return
2099 * back to userland with ERETNC. That preserves the
2100 * LLAddr/LLB so the subsequent SC instruction will
2101 * succeed preserving the atomic semantics of the LL/SC
2102 * block. Without that, there is no safe way to emulate
2103 * an LL/SC block in MIPSR2 userland.
2105 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2110 __asm__ __volatile__(
2115 ".section .fixup,\"ax\"\n"
2120 ".section __ex_table,\"a\"\n"
2123 : "=&r"(res), "+&r"(err)
2124 : "r"(vaddr), "i"(SIGSEGV)
2126 if (MIPSInst_RT(inst) && !err)
2127 regs->regs[MIPSInst_RT(inst)] = res;
2129 MIPS_R2_STATS(llsc);
2134 if (config_enabled(CONFIG_32BIT)) {
2139 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
2141 current->thread.cp0_baduaddr = vaddr;
2145 if (!access_ok(VERIFY_WRITE, vaddr, 8)) {
2146 current->thread.cp0_baduaddr = vaddr;
2151 if (!cpu_has_rw_llb) {
2153 * An LL/SC block can't be safely emulated without
2154 * a Config5/LLB availability. So it's probably time to
2155 * kill our process before things get any worse. This is
2156 * because Config5/LLB allows us to use ERETNC so that
2157 * the LLAddr/LLB bit is not cleared when we return from
2158 * an exception. MIPS R2 LL/SC instructions trap with an
2159 * RI exception so once we emulate them here, we return
2160 * back to userland with ERETNC. That preserves the
2161 * LLAddr/LLB so the subsequent SC instruction will
2162 * succeed preserving the atomic semantics of the LL/SC
2163 * block. Without that, there is no safe way to emulate
2164 * an LL/SC block in MIPSR2 userland.
2166 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2171 res = regs->regs[MIPSInst_RT(inst)];
2173 __asm__ __volatile__(
2178 ".section .fixup,\"ax\"\n"
2183 ".section __ex_table,\"a\"\n"
2186 : "+&r"(res), "+&r"(err)
2187 : "r"(vaddr), "i"(SIGSEGV));
2189 if (MIPSInst_RT(inst) && !err)
2190 regs->regs[MIPSInst_RT(inst)] = res;
2192 MIPS_R2_STATS(llsc);
2203 * Lets not return to userland just yet. It's constly and
2204 * it's likely we have more R2 instructions to emulate
2206 if (!err && (pass++ < MIPS_R2_EMUL_TOTAL_PASS)) {
2207 regs->cp0_cause &= ~CAUSEF_BD;
2208 err = get_user(inst, (u32 __user *)regs->cp0_epc);
2216 if (err && (err != SIGEMT)) {
2217 regs->regs[31] = r31;
2218 regs->cp0_epc = epc;
2221 /* Likely a MIPS R6 compatible instruction */
2222 if (pass && (err == SIGILL))
2228 #ifdef CONFIG_DEBUG_FS
2230 static int mipsr2_stats_show(struct seq_file *s, void *unused)
2233 seq_printf(s, "Instruction\tTotal\tBDslot\n------------------------------\n");
2234 seq_printf(s, "movs\t\t%ld\t%ld\n",
2235 (unsigned long)__this_cpu_read(mipsr2emustats.movs),
2236 (unsigned long)__this_cpu_read(mipsr2bdemustats.movs));
2237 seq_printf(s, "hilo\t\t%ld\t%ld\n",
2238 (unsigned long)__this_cpu_read(mipsr2emustats.hilo),
2239 (unsigned long)__this_cpu_read(mipsr2bdemustats.hilo));
2240 seq_printf(s, "muls\t\t%ld\t%ld\n",
2241 (unsigned long)__this_cpu_read(mipsr2emustats.muls),
2242 (unsigned long)__this_cpu_read(mipsr2bdemustats.muls));
2243 seq_printf(s, "divs\t\t%ld\t%ld\n",
2244 (unsigned long)__this_cpu_read(mipsr2emustats.divs),
2245 (unsigned long)__this_cpu_read(mipsr2bdemustats.divs));
2246 seq_printf(s, "dsps\t\t%ld\t%ld\n",
2247 (unsigned long)__this_cpu_read(mipsr2emustats.dsps),
2248 (unsigned long)__this_cpu_read(mipsr2bdemustats.dsps));
2249 seq_printf(s, "bops\t\t%ld\t%ld\n",
2250 (unsigned long)__this_cpu_read(mipsr2emustats.bops),
2251 (unsigned long)__this_cpu_read(mipsr2bdemustats.bops));
2252 seq_printf(s, "traps\t\t%ld\t%ld\n",
2253 (unsigned long)__this_cpu_read(mipsr2emustats.traps),
2254 (unsigned long)__this_cpu_read(mipsr2bdemustats.traps));
2255 seq_printf(s, "fpus\t\t%ld\t%ld\n",
2256 (unsigned long)__this_cpu_read(mipsr2emustats.fpus),
2257 (unsigned long)__this_cpu_read(mipsr2bdemustats.fpus));
2258 seq_printf(s, "loads\t\t%ld\t%ld\n",
2259 (unsigned long)__this_cpu_read(mipsr2emustats.loads),
2260 (unsigned long)__this_cpu_read(mipsr2bdemustats.loads));
2261 seq_printf(s, "stores\t\t%ld\t%ld\n",
2262 (unsigned long)__this_cpu_read(mipsr2emustats.stores),
2263 (unsigned long)__this_cpu_read(mipsr2bdemustats.stores));
2264 seq_printf(s, "llsc\t\t%ld\t%ld\n",
2265 (unsigned long)__this_cpu_read(mipsr2emustats.llsc),
2266 (unsigned long)__this_cpu_read(mipsr2bdemustats.llsc));
2267 seq_printf(s, "dsemul\t\t%ld\t%ld\n",
2268 (unsigned long)__this_cpu_read(mipsr2emustats.dsemul),
2269 (unsigned long)__this_cpu_read(mipsr2bdemustats.dsemul));
2270 seq_printf(s, "jr\t\t%ld\n",
2271 (unsigned long)__this_cpu_read(mipsr2bremustats.jrs));
2272 seq_printf(s, "bltzl\t\t%ld\n",
2273 (unsigned long)__this_cpu_read(mipsr2bremustats.bltzl));
2274 seq_printf(s, "bgezl\t\t%ld\n",
2275 (unsigned long)__this_cpu_read(mipsr2bremustats.bgezl));
2276 seq_printf(s, "bltzll\t\t%ld\n",
2277 (unsigned long)__this_cpu_read(mipsr2bremustats.bltzll));
2278 seq_printf(s, "bgezll\t\t%ld\n",
2279 (unsigned long)__this_cpu_read(mipsr2bremustats.bgezll));
2280 seq_printf(s, "bltzal\t\t%ld\n",
2281 (unsigned long)__this_cpu_read(mipsr2bremustats.bltzal));
2282 seq_printf(s, "bgezal\t\t%ld\n",
2283 (unsigned long)__this_cpu_read(mipsr2bremustats.bgezal));
2284 seq_printf(s, "beql\t\t%ld\n",
2285 (unsigned long)__this_cpu_read(mipsr2bremustats.beql));
2286 seq_printf(s, "bnel\t\t%ld\n",
2287 (unsigned long)__this_cpu_read(mipsr2bremustats.bnel));
2288 seq_printf(s, "blezl\t\t%ld\n",
2289 (unsigned long)__this_cpu_read(mipsr2bremustats.blezl));
2290 seq_printf(s, "bgtzl\t\t%ld\n",
2291 (unsigned long)__this_cpu_read(mipsr2bremustats.bgtzl));
2296 static int mipsr2_stats_clear_show(struct seq_file *s, void *unused)
2298 mipsr2_stats_show(s, unused);
2300 __this_cpu_write((mipsr2emustats).movs, 0);
2301 __this_cpu_write((mipsr2bdemustats).movs, 0);
2302 __this_cpu_write((mipsr2emustats).hilo, 0);
2303 __this_cpu_write((mipsr2bdemustats).hilo, 0);
2304 __this_cpu_write((mipsr2emustats).muls, 0);
2305 __this_cpu_write((mipsr2bdemustats).muls, 0);
2306 __this_cpu_write((mipsr2emustats).divs, 0);
2307 __this_cpu_write((mipsr2bdemustats).divs, 0);
2308 __this_cpu_write((mipsr2emustats).dsps, 0);
2309 __this_cpu_write((mipsr2bdemustats).dsps, 0);
2310 __this_cpu_write((mipsr2emustats).bops, 0);
2311 __this_cpu_write((mipsr2bdemustats).bops, 0);
2312 __this_cpu_write((mipsr2emustats).traps, 0);
2313 __this_cpu_write((mipsr2bdemustats).traps, 0);
2314 __this_cpu_write((mipsr2emustats).fpus, 0);
2315 __this_cpu_write((mipsr2bdemustats).fpus, 0);
2316 __this_cpu_write((mipsr2emustats).loads, 0);
2317 __this_cpu_write((mipsr2bdemustats).loads, 0);
2318 __this_cpu_write((mipsr2emustats).stores, 0);
2319 __this_cpu_write((mipsr2bdemustats).stores, 0);
2320 __this_cpu_write((mipsr2emustats).llsc, 0);
2321 __this_cpu_write((mipsr2bdemustats).llsc, 0);
2322 __this_cpu_write((mipsr2emustats).dsemul, 0);
2323 __this_cpu_write((mipsr2bdemustats).dsemul, 0);
2324 __this_cpu_write((mipsr2bremustats).jrs, 0);
2325 __this_cpu_write((mipsr2bremustats).bltzl, 0);
2326 __this_cpu_write((mipsr2bremustats).bgezl, 0);
2327 __this_cpu_write((mipsr2bremustats).bltzll, 0);
2328 __this_cpu_write((mipsr2bremustats).bgezll, 0);
2329 __this_cpu_write((mipsr2bremustats).bltzal, 0);
2330 __this_cpu_write((mipsr2bremustats).bgezal, 0);
2331 __this_cpu_write((mipsr2bremustats).beql, 0);
2332 __this_cpu_write((mipsr2bremustats).bnel, 0);
2333 __this_cpu_write((mipsr2bremustats).blezl, 0);
2334 __this_cpu_write((mipsr2bremustats).bgtzl, 0);
2339 static int mipsr2_stats_open(struct inode *inode, struct file *file)
2341 return single_open(file, mipsr2_stats_show, inode->i_private);
2344 static int mipsr2_stats_clear_open(struct inode *inode, struct file *file)
2346 return single_open(file, mipsr2_stats_clear_show, inode->i_private);
2349 static const struct file_operations mipsr2_emul_fops = {
2350 .open = mipsr2_stats_open,
2352 .llseek = seq_lseek,
2353 .release = single_release,
2356 static const struct file_operations mipsr2_clear_fops = {
2357 .open = mipsr2_stats_clear_open,
2359 .llseek = seq_lseek,
2360 .release = single_release,
2364 static int __init mipsr2_init_debugfs(void)
2366 extern struct dentry *mips_debugfs_dir;
2367 struct dentry *mipsr2_emul;
2369 if (!mips_debugfs_dir)
2372 mipsr2_emul = debugfs_create_file("r2_emul_stats", S_IRUGO,
2373 mips_debugfs_dir, NULL,
2378 mipsr2_emul = debugfs_create_file("r2_emul_stats_clear", S_IRUGO,
2379 mips_debugfs_dir, NULL,
2380 &mipsr2_clear_fops);
2387 device_initcall(mipsr2_init_debugfs);
2389 #endif /* CONFIG_DEBUG_FS */