2 * Copyright (C) 2003, Axis Communications AB.
7 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/errno.h>
11 #include <linux/init.h>
12 #include <linux/profile.h>
14 #include <linux/of_irq.h>
15 #include <linux/proc_fs.h>
16 #include <linux/seq_file.h>
17 #include <linux/threads.h>
18 #include <linux/spinlock.h>
19 #include <linux/kernel_stat.h>
20 #include <hwregs/reg_map.h>
21 #include <hwregs/reg_rdwr.h>
22 #include <hwregs/intr_vect.h>
23 #include <hwregs/intr_vect_defs.h>
27 /* IRQ masks (refer to comment for crisv32_do_multiple) */
28 #if TIMER0_INTR_VECT - FIRST_IRQ < 32
29 #define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ))
32 #define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ - 32))
35 #ifdef CONFIG_ETRAX_KGDB
36 #if defined(CONFIG_ETRAX_KGDB_PORT0)
37 #define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ))
38 #elif defined(CONFIG_ETRAX_KGDB_PORT1)
39 #define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ))
40 #elif defined(CONFIG_ETRAX_KGDB_PORT2)
41 #define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ))
42 #elif defined(CONFIG_ETRAX_KGDB_PORT3)
43 #define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ))
47 DEFINE_SPINLOCK(irq_lock);
49 struct cris_irq_allocation
51 int cpu; /* The CPU to which the IRQ is currently allocated. */
52 cpumask_t mask; /* The CPUs to which the IRQ may be allocated. */
55 struct cris_irq_allocation irq_allocations[NR_REAL_IRQS] =
56 { [0 ... NR_REAL_IRQS - 1] = {0, CPU_MASK_ALL} };
58 static unsigned long irq_regs[NR_CPUS] =
69 unsigned long cpu_irq_counters[NR_CPUS];
70 unsigned long irq_counters[NR_REAL_IRQS];
73 extern void weird_irq(void);
76 extern void system_call(void);
77 extern void nmi_interrupt(void);
78 extern void multiple_interrupt(void);
79 extern void gdb_handle_exception(void);
80 extern void i_mmu_refill(void);
81 extern void i_mmu_invalid(void);
82 extern void i_mmu_access(void);
83 extern void i_mmu_execute(void);
84 extern void d_mmu_refill(void);
85 extern void d_mmu_invalid(void);
86 extern void d_mmu_access(void);
87 extern void d_mmu_write(void);
90 extern void kgdb_init(void);
91 extern void breakpoint(void);
94 extern void breakh_BUG(void);
97 * Build the IRQ handler stubs using macros from irq.h.
99 #ifdef CONFIG_CRIS_MACH_ARTPEC3
100 BUILD_TIMER_IRQ(0x31, 0)
129 #ifdef CONFIG_ETRAXFS
130 BUILD_TIMER_IRQ(0x4b, 0)
174 /* Pointers to the low-level handlers. */
175 static void (*interrupt[MACH_IRQS])(void) = {
176 IRQ0x31_interrupt, IRQ0x32_interrupt, IRQ0x33_interrupt,
177 IRQ0x34_interrupt, IRQ0x35_interrupt, IRQ0x36_interrupt,
178 IRQ0x37_interrupt, IRQ0x38_interrupt, IRQ0x39_interrupt,
179 IRQ0x3a_interrupt, IRQ0x3b_interrupt, IRQ0x3c_interrupt,
180 IRQ0x3d_interrupt, IRQ0x3e_interrupt, IRQ0x3f_interrupt,
181 IRQ0x40_interrupt, IRQ0x41_interrupt, IRQ0x42_interrupt,
182 IRQ0x43_interrupt, IRQ0x44_interrupt, IRQ0x45_interrupt,
183 IRQ0x46_interrupt, IRQ0x47_interrupt, IRQ0x48_interrupt,
184 IRQ0x49_interrupt, IRQ0x4a_interrupt, IRQ0x4b_interrupt,
185 IRQ0x4c_interrupt, IRQ0x4d_interrupt, IRQ0x4e_interrupt,
186 IRQ0x4f_interrupt, IRQ0x50_interrupt,
188 IRQ0x51_interrupt, IRQ0x52_interrupt, IRQ0x53_interrupt,
189 IRQ0x54_interrupt, IRQ0x55_interrupt, IRQ0x56_interrupt,
190 IRQ0x57_interrupt, IRQ0x58_interrupt, IRQ0x59_interrupt,
191 IRQ0x5a_interrupt, IRQ0x5b_interrupt, IRQ0x5c_interrupt,
192 IRQ0x5d_interrupt, IRQ0x5e_interrupt, IRQ0x5f_interrupt,
193 IRQ0x60_interrupt, IRQ0x61_interrupt, IRQ0x62_interrupt,
194 IRQ0x63_interrupt, IRQ0x64_interrupt, IRQ0x65_interrupt,
195 IRQ0x66_interrupt, IRQ0x67_interrupt, IRQ0x68_interrupt,
196 IRQ0x69_interrupt, IRQ0x6a_interrupt, IRQ0x6b_interrupt,
197 IRQ0x6c_interrupt, IRQ0x6d_interrupt, IRQ0x6e_interrupt,
198 IRQ0x6f_interrupt, IRQ0x70_interrupt,
203 block_irq(int irq, int cpu)
208 spin_lock_irqsave(&irq_lock, flags);
209 /* Remember, 1 let thru, 0 block. */
210 if (irq - FIRST_IRQ < 32) {
211 intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
213 intr_mask &= ~(1 << (irq - FIRST_IRQ));
214 REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
217 intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
219 intr_mask &= ~(1 << (irq - FIRST_IRQ - 32));
220 REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
223 spin_unlock_irqrestore(&irq_lock, flags);
227 unblock_irq(int irq, int cpu)
232 spin_lock_irqsave(&irq_lock, flags);
233 /* Remember, 1 let thru, 0 block. */
234 if (irq - FIRST_IRQ < 32) {
235 intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
237 intr_mask |= (1 << (irq - FIRST_IRQ));
238 REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
241 intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
243 intr_mask |= (1 << (irq - FIRST_IRQ - 32));
244 REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
247 spin_unlock_irqrestore(&irq_lock, flags);
250 /* Find out which CPU the irq should be allocated to. */
251 static int irq_cpu(int irq)
256 spin_lock_irqsave(&irq_lock, flags);
257 cpu = irq_allocations[irq - FIRST_IRQ].cpu;
259 /* Fixed interrupts stay on the local CPU. */
260 if (cpu == CPU_FIXED)
262 spin_unlock_irqrestore(&irq_lock, flags);
263 return smp_processor_id();
267 /* Let the interrupt stay if possible */
268 if (cpumask_test_cpu(cpu, &irq_allocations[irq - FIRST_IRQ].mask))
271 /* IRQ must be moved to another CPU. */
272 cpu = cpumask_first(&irq_allocations[irq - FIRST_IRQ].mask);
273 irq_allocations[irq - FIRST_IRQ].cpu = cpu;
275 spin_unlock_irqrestore(&irq_lock, flags);
279 void crisv32_mask_irq(int irq)
283 for (cpu = 0; cpu < NR_CPUS; cpu++)
287 void crisv32_unmask_irq(int irq)
289 unblock_irq(irq, irq_cpu(irq));
293 static void enable_crisv32_irq(struct irq_data *data)
295 crisv32_unmask_irq(data->irq);
298 static void disable_crisv32_irq(struct irq_data *data)
300 crisv32_mask_irq(data->irq);
303 static int set_affinity_crisv32_irq(struct irq_data *data,
304 const struct cpumask *dest, bool force)
308 spin_lock_irqsave(&irq_lock, flags);
309 irq_allocations[data->irq - FIRST_IRQ].mask = *dest;
310 spin_unlock_irqrestore(&irq_lock, flags);
314 static struct irq_chip crisv32_irq_type = {
316 .irq_shutdown = disable_crisv32_irq,
317 .irq_enable = enable_crisv32_irq,
318 .irq_disable = disable_crisv32_irq,
319 .irq_set_affinity = set_affinity_crisv32_irq,
323 set_exception_vector(int n, irqvectptr addr)
325 etrax_irv->v[n] = (irqvectptr) addr;
328 extern void do_IRQ(int irq, struct pt_regs * regs);
331 crisv32_do_IRQ(int irq, int block, struct pt_regs* regs)
333 /* Interrupts that may not be moved to another CPU may
334 * skip blocking. This is currently only valid for the
335 * timer IRQ and the IPI and is used for the timer
336 * interrupt to avoid watchdog starvation.
343 block_irq(irq, smp_processor_id());
346 unblock_irq(irq, irq_cpu(irq));
349 /* If multiple interrupts occur simultaneously we get a multiple
350 * interrupt from the CPU and software has to sort out which
351 * interrupts that happened. There are two special cases here:
353 * 1. Timer interrupts may never be blocked because of the
354 * watchdog (refer to comment in include/asr/arch/irq.h)
355 * 2. GDB serial port IRQs are unhandled here and will be handled
356 * as a single IRQ when it strikes again because the GDB
357 * stubb wants to save the registers in its own fashion.
360 crisv32_do_multiple(struct pt_regs* regs)
364 int masked[NBR_REGS];
368 cpu = smp_processor_id();
370 /* An extra irq_enter here to prevent softIRQs to run after
371 * each do_IRQ. This will decrease the interrupt latency.
375 for (i = 0; i < NBR_REGS; i++) {
376 /* Get which IRQs that happened. */
377 masked[i] = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
380 /* Calculate new IRQ mask with these IRQs disabled. */
381 mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);
384 /* Timer IRQ is never masked */
386 if ((i == 1) && (masked[0] & TIMER_MASK))
389 if ((i == 0) && (masked[0] & TIMER_MASK))
392 /* Block all the IRQs */
393 REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);
395 /* Check for timer IRQ and handle it special. */
397 if ((i == 1) && (masked[i] & TIMER_MASK)) {
398 masked[i] &= ~TIMER_MASK;
399 do_IRQ(TIMER0_INTR_VECT, regs);
402 if ((i == 0) && (masked[i] & TIMER_MASK)) {
403 masked[i] &= ~TIMER_MASK;
404 do_IRQ(TIMER0_INTR_VECT, regs);
410 /* Remove IRQs that can't be handled as multiple. */
411 masked[0] &= ~IGNORE_MASK;
414 /* Handle the rest of the IRQs. */
415 for (i = 0; i < NBR_REGS; i++) {
416 for (bit = 0; bit < 32; bit++) {
417 if (masked[i] & (1 << bit))
418 do_IRQ(bit + FIRST_IRQ + i*32, regs);
422 /* Unblock all the IRQs. */
423 for (i = 0; i < NBR_REGS; i++) {
424 mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);
426 REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);
429 /* This irq_exit() will trigger the soft IRQs. */
433 static int crisv32_irq_map(struct irq_domain *h, unsigned int virq,
434 irq_hw_number_t hw_irq_num)
436 irq_set_chip_and_handler(virq, &crisv32_irq_type, handle_simple_irq);
441 static struct irq_domain_ops crisv32_irq_ops = {
442 .map = crisv32_irq_map,
443 .xlate = irq_domain_xlate_onecell,
447 * This is called by start_kernel. It fixes the IRQ masks and setup the
448 * interrupt vector table to point to bad_interrupt pointers.
455 reg_intr_vect_rw_mask vect_mask = {0};
456 struct device_node *np;
457 struct irq_domain *domain;
459 /* Clear all interrupts masks. */
460 for (i = 0; i < NBR_REGS; i++)
461 REG_WR_VECT(intr_vect, regi_irq, rw_mask, i, vect_mask);
463 for (i = 0; i < 256; i++)
464 etrax_irv->v[i] = weird_irq;
466 np = of_find_compatible_node(NULL, NULL, "axis,crisv32-intc");
467 domain = irq_domain_add_legacy(np, NBR_INTR_VECT - FIRST_IRQ,
468 FIRST_IRQ, FIRST_IRQ,
469 &crisv32_irq_ops, NULL);
471 irq_set_default_host(domain);
474 for (i = FIRST_IRQ, j = 0; j < NBR_INTR_VECT; i++, j++) {
475 set_exception_vector(i, interrupt[j]);
478 /* Mark Timer and IPI IRQs as CPU local */
479 irq_allocations[TIMER0_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
480 irq_set_status_flags(TIMER0_INTR_VECT, IRQ_PER_CPU);
481 irq_allocations[IPI_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
482 irq_set_status_flags(IPI_INTR_VECT, IRQ_PER_CPU);
484 set_exception_vector(0x00, nmi_interrupt);
485 set_exception_vector(0x30, multiple_interrupt);
487 /* Set up handler for various MMU bus faults. */
488 set_exception_vector(0x04, i_mmu_refill);
489 set_exception_vector(0x05, i_mmu_invalid);
490 set_exception_vector(0x06, i_mmu_access);
491 set_exception_vector(0x07, i_mmu_execute);
492 set_exception_vector(0x08, d_mmu_refill);
493 set_exception_vector(0x09, d_mmu_invalid);
494 set_exception_vector(0x0a, d_mmu_access);
495 set_exception_vector(0x0b, d_mmu_write);
498 /* Break 14 handler, used to implement cheap BUG(). */
499 set_exception_vector(0x1e, breakh_BUG);
502 /* The system-call trap is reached by "break 13". */
503 set_exception_vector(0x1d, system_call);
505 /* Exception handlers for debugging, both user-mode and kernel-mode. */
508 set_exception_vector(0x18, gdb_handle_exception);
509 /* Hardware single step. */
510 set_exception_vector(0x3, gdb_handle_exception);
511 /* Hardware breakpoint. */
512 set_exception_vector(0xc, gdb_handle_exception);
514 #ifdef CONFIG_ETRAX_KGDB
516 /* Everything is set up; now trap the kernel. */