2 * Set up the interrupt priorities
4 * Copyright 2004-2009 Analog Devices Inc.
5 * 2003 Bas Vermeulen <bas@buyways.nl>
6 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
11 * Licensed under the GPL-2
14 #include <linux/module.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/seq_file.h>
17 #include <linux/irq.h>
18 #include <linux/sched.h>
19 #include <linux/syscore_ops.h>
20 #include <asm/delay.h>
22 #include <linux/ipipe.h>
24 #include <asm/traps.h>
25 #include <asm/blackfin.h>
27 #include <asm/irq_handler.h>
29 #include <asm/traps.h>
33 * - we have separated the physical Hardware interrupt from the
34 * levels that the LINUX kernel sees (see the description in irq.h)
39 /* Initialize this to an actual value to force it into the .data
40 * section so that we know it is properly initialized at entry into
41 * the kernel but before bss is initialized to zero (which is where
42 * it would live otherwise). The 0x1f magic represents the IRQs we
43 * cannot actually mask out in hardware.
45 unsigned long bfin_irq_flags = 0x1f;
46 EXPORT_SYMBOL(bfin_irq_flags);
50 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
56 /* irq number for request_irq, available in mach-bf5xx/irq.h */
58 /* corresponding bit in the SIC_ISR register */
60 } ivg_table[NR_PERI_INTS];
62 static struct ivg_slice {
63 /* position of first irq in ivg_table for given ivg */
66 } ivg7_13[IVG13 - IVG7 + 1];
70 * Search SIC_IAR and fill tables with the irqvalues
71 * and their positions in the SIC_ISR register.
73 static void __init search_IAR(void)
75 unsigned ivg, irq_pos = 0;
76 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
79 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
81 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
84 bfin_read32((unsigned long *)SIC_IAR0 +
85 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
86 defined(CONFIG_BF538) || defined(CONFIG_BF539)
87 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
92 for (irqn = irqN; irqn < irqN + 4; ++irqn) {
93 int iar_shift = (irqn & 7) * 4;
94 if (ivg == (0xf & (iar >> iar_shift))) {
95 ivg_table[irq_pos].irqno = IVG7 + irqn;
96 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
107 * This is for core internal IRQs
109 void bfin_ack_noop(struct irq_data *d)
111 /* Dummy function. */
114 static void bfin_core_mask_irq(struct irq_data *d)
116 bfin_irq_flags &= ~(1 << d->irq);
117 if (!hard_irqs_disabled())
118 hard_local_irq_enable();
121 static void bfin_core_unmask_irq(struct irq_data *d)
123 bfin_irq_flags |= 1 << d->irq;
125 * If interrupts are enabled, IMASK must contain the same value
126 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
127 * are currently disabled we need not do anything; one of the
128 * callers will take care of setting IMASK to the proper value
129 * when reenabling interrupts.
130 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
133 if (!hard_irqs_disabled())
134 hard_local_irq_enable();
139 void bfin_internal_mask_irq(unsigned int irq)
141 unsigned long flags = hard_local_irq_save();
143 unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
144 unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
145 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
147 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
148 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
152 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
153 ~(1 << BFIN_SYSIRQ(irq)));
154 #endif /* end of SIC_IMASK0 */
155 hard_local_irq_restore(flags);
158 static void bfin_internal_mask_irq_chip(struct irq_data *d)
160 bfin_internal_mask_irq(d->irq);
164 void bfin_internal_unmask_irq_affinity(unsigned int irq,
165 const struct cpumask *affinity)
167 void bfin_internal_unmask_irq(unsigned int irq)
170 unsigned long flags = hard_local_irq_save();
173 unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
174 unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
176 if (cpumask_test_cpu(0, affinity))
178 bfin_write_SIC_IMASK(mask_bank,
179 bfin_read_SIC_IMASK(mask_bank) |
182 if (cpumask_test_cpu(1, affinity))
183 bfin_write_SICB_IMASK(mask_bank,
184 bfin_read_SICB_IMASK(mask_bank) |
188 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
189 (1 << BFIN_SYSIRQ(irq)));
191 hard_local_irq_restore(flags);
195 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
197 bfin_internal_unmask_irq_affinity(d->irq,
198 irq_data_get_affinity_mask(d));
201 static int bfin_internal_set_affinity(struct irq_data *d,
202 const struct cpumask *mask, bool force)
204 bfin_internal_mask_irq(d->irq);
205 bfin_internal_unmask_irq_affinity(d->irq, mask);
210 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
212 bfin_internal_unmask_irq(d->irq);
216 #if defined(CONFIG_PM)
217 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
219 u32 bank, bit, wakeup = 0;
221 bank = BFIN_SYSIRQ(irq) / 32;
222 bit = BFIN_SYSIRQ(irq) % 32;
254 flags = hard_local_irq_save();
257 bfin_sic_iwr[bank] |= (1 << bit);
261 bfin_sic_iwr[bank] &= ~(1 << bit);
262 vr_wakeup &= ~wakeup;
265 hard_local_irq_restore(flags);
270 static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
272 return bfin_internal_set_wake(d->irq, state);
275 inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
279 # define bfin_internal_set_wake_chip NULL
283 static void bfin_sec_preflow_handler(struct irq_data *d)
285 unsigned long flags = hard_local_irq_save();
286 unsigned int sid = BFIN_SYSIRQ(d->irq);
288 bfin_write_SEC_SCI(0, SEC_CSID, sid);
290 hard_local_irq_restore(flags);
293 static void bfin_sec_mask_ack_irq(struct irq_data *d)
295 unsigned long flags = hard_local_irq_save();
296 unsigned int sid = BFIN_SYSIRQ(d->irq);
298 bfin_write_SEC_SCI(0, SEC_CSID, sid);
300 hard_local_irq_restore(flags);
303 static void bfin_sec_unmask_irq(struct irq_data *d)
305 unsigned long flags = hard_local_irq_save();
306 unsigned int sid = BFIN_SYSIRQ(d->irq);
308 bfin_write32(SEC_END, sid);
310 hard_local_irq_restore(flags);
313 static void bfin_sec_enable_ssi(unsigned int sid)
315 unsigned long flags = hard_local_irq_save();
316 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
318 reg_sctl |= SEC_SCTL_SRC_EN;
319 bfin_write_SEC_SCTL(sid, reg_sctl);
321 hard_local_irq_restore(flags);
324 static void bfin_sec_disable_ssi(unsigned int sid)
326 unsigned long flags = hard_local_irq_save();
327 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
329 reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
330 bfin_write_SEC_SCTL(sid, reg_sctl);
332 hard_local_irq_restore(flags);
335 static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
337 unsigned long flags = hard_local_irq_save();
338 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
340 reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
341 bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
343 hard_local_irq_restore(flags);
346 static void bfin_sec_enable_sci(unsigned int sid)
348 unsigned long flags = hard_local_irq_save();
349 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
351 if (sid == BFIN_SYSIRQ(IRQ_WATCH0))
352 reg_sctl |= SEC_SCTL_FAULT_EN;
354 reg_sctl |= SEC_SCTL_INT_EN;
355 bfin_write_SEC_SCTL(sid, reg_sctl);
357 hard_local_irq_restore(flags);
360 static void bfin_sec_disable_sci(unsigned int sid)
362 unsigned long flags = hard_local_irq_save();
363 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
365 reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
366 bfin_write_SEC_SCTL(sid, reg_sctl);
368 hard_local_irq_restore(flags);
371 static void bfin_sec_enable(struct irq_data *d)
373 unsigned long flags = hard_local_irq_save();
374 unsigned int sid = BFIN_SYSIRQ(d->irq);
376 bfin_sec_enable_sci(sid);
377 bfin_sec_enable_ssi(sid);
379 hard_local_irq_restore(flags);
382 static void bfin_sec_disable(struct irq_data *d)
384 unsigned long flags = hard_local_irq_save();
385 unsigned int sid = BFIN_SYSIRQ(d->irq);
387 bfin_sec_disable_sci(sid);
388 bfin_sec_disable_ssi(sid);
390 hard_local_irq_restore(flags);
393 static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority)
395 unsigned long flags = hard_local_irq_save();
399 bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels);
401 for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) {
402 reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO;
403 reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET;
404 bfin_write_SEC_SCTL(i, reg_sctl);
407 hard_local_irq_restore(flags);
410 void bfin_sec_raise_irq(unsigned int irq)
412 unsigned long flags = hard_local_irq_save();
413 unsigned int sid = BFIN_SYSIRQ(irq);
415 bfin_write32(SEC_RAISE, sid);
417 hard_local_irq_restore(flags);
420 static void init_software_driven_irq(void)
422 bfin_sec_set_ssi_coreid(34, 0);
423 bfin_sec_set_ssi_coreid(35, 1);
425 bfin_sec_enable_sci(35);
426 bfin_sec_enable_ssi(35);
427 bfin_sec_set_ssi_coreid(36, 0);
428 bfin_sec_set_ssi_coreid(37, 1);
429 bfin_sec_enable_sci(37);
430 bfin_sec_enable_ssi(37);
433 void handle_sec_sfi_fault(uint32_t gstat)
438 void handle_sec_sci_fault(uint32_t gstat)
443 core_id = gstat & SEC_GSTAT_SCI;
444 cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
445 if (cstat & SEC_CSTAT_ERR) {
446 switch (cstat & SEC_CSTAT_ERRC) {
447 case SEC_CSTAT_ACKERR:
448 printk(KERN_DEBUG "sec ack err\n");
451 printk(KERN_DEBUG "sec sci unknown err\n");
457 void handle_sec_ssi_fault(uint32_t gstat)
462 sid = gstat & SEC_GSTAT_SID;
463 sstat = bfin_read_SEC_SSTAT(sid);
467 void handle_sec_fault(uint32_t sec_gstat)
469 if (sec_gstat & SEC_GSTAT_ERR) {
471 switch (sec_gstat & SEC_GSTAT_ERRC) {
473 handle_sec_sfi_fault(sec_gstat);
475 case SEC_GSTAT_SCIERR:
476 handle_sec_sci_fault(sec_gstat);
478 case SEC_GSTAT_SSIERR:
479 handle_sec_ssi_fault(sec_gstat);
487 static struct irqaction bfin_fault_irq = {
488 .name = "Blackfin fault",
491 static irqreturn_t bfin_fault_routine(int irq, void *data)
493 struct pt_regs *fp = get_irq_regs();
496 case IRQ_C0_DBL_FAULT:
500 dump_bfin_process(fp);
503 printk(KERN_NOTICE "Kernel Stack\n");
504 show_stack(current, NULL);
506 panic("Core 0 hardware error");
508 case IRQ_C0_NMI_L1_PARITY_ERR:
509 panic("Core 0 NMI L1 parity error");
512 pr_err("SEC error\n");
513 handle_sec_fault(bfin_read32(SEC_GSTAT));
516 panic("Unknown fault %d", irq);
521 #endif /* SEC_GCTL */
523 static struct irq_chip bfin_core_irqchip = {
525 .irq_mask = bfin_core_mask_irq,
526 .irq_unmask = bfin_core_unmask_irq,
530 static struct irq_chip bfin_internal_irqchip = {
532 .irq_mask = bfin_internal_mask_irq_chip,
533 .irq_unmask = bfin_internal_unmask_irq_chip,
534 .irq_disable = bfin_internal_mask_irq_chip,
535 .irq_enable = bfin_internal_unmask_irq_chip,
537 .irq_set_affinity = bfin_internal_set_affinity,
539 .irq_set_wake = bfin_internal_set_wake_chip,
542 static struct irq_chip bfin_sec_irqchip = {
544 .irq_mask_ack = bfin_sec_mask_ack_irq,
545 .irq_mask = bfin_sec_mask_ack_irq,
546 .irq_unmask = bfin_sec_unmask_irq,
547 .irq_eoi = bfin_sec_unmask_irq,
548 .irq_disable = bfin_sec_disable,
549 .irq_enable = bfin_sec_enable,
553 void bfin_handle_irq(unsigned irq)
556 struct pt_regs regs; /* Contents not used. */
557 ipipe_trace_irq_entry(irq);
558 __ipipe_handle_irq(irq, ®s);
559 ipipe_trace_irq_exit(irq);
560 #else /* !CONFIG_IPIPE */
561 generic_handle_irq(irq);
562 #endif /* !CONFIG_IPIPE */
565 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
566 static int mac_stat_int_mask;
568 static void bfin_mac_status_ack_irq(unsigned int irq)
572 bfin_write_EMAC_MMC_TIRQS(
573 bfin_read_EMAC_MMC_TIRQE() &
574 bfin_read_EMAC_MMC_TIRQS());
575 bfin_write_EMAC_MMC_RIRQS(
576 bfin_read_EMAC_MMC_RIRQE() &
577 bfin_read_EMAC_MMC_RIRQS());
579 case IRQ_MAC_RXFSINT:
580 bfin_write_EMAC_RX_STKY(
581 bfin_read_EMAC_RX_IRQE() &
582 bfin_read_EMAC_RX_STKY());
584 case IRQ_MAC_TXFSINT:
585 bfin_write_EMAC_TX_STKY(
586 bfin_read_EMAC_TX_IRQE() &
587 bfin_read_EMAC_TX_STKY());
589 case IRQ_MAC_WAKEDET:
590 bfin_write_EMAC_WKUP_CTL(
591 bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
594 /* These bits are W1C */
595 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
600 static void bfin_mac_status_mask_irq(struct irq_data *d)
602 unsigned int irq = d->irq;
604 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
608 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
614 if (!mac_stat_int_mask)
615 bfin_internal_mask_irq(IRQ_MAC_ERROR);
617 bfin_mac_status_ack_irq(irq);
620 static void bfin_mac_status_unmask_irq(struct irq_data *d)
622 unsigned int irq = d->irq;
627 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
633 if (!mac_stat_int_mask)
634 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
636 mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
640 int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
643 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
645 return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
649 # define bfin_mac_status_set_wake NULL
652 static struct irq_chip bfin_mac_status_irqchip = {
654 .irq_mask = bfin_mac_status_mask_irq,
655 .irq_unmask = bfin_mac_status_unmask_irq,
656 .irq_set_wake = bfin_mac_status_set_wake,
659 void bfin_demux_mac_status_irq(struct irq_desc *inta_desc)
662 u32 status = bfin_read_EMAC_SYSTAT();
664 for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
665 if (status & (1L << i)) {
666 irq = IRQ_MAC_PHYINT + i;
671 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
672 bfin_handle_irq(irq);
674 bfin_mac_status_ack_irq(irq);
676 " MASKED MAC ERROR INTERRUPT ASSERTED\n",
681 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
682 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
683 "(EMAC_SYSTAT=0x%X)\n",
684 __func__, __FILE__, __LINE__, status);
688 static inline void bfin_set_irq_handler(struct irq_data *d, irq_flow_handler_t handle)
691 handle = handle_level_irq;
693 irq_set_handler_locked(d, handle);
696 #ifdef CONFIG_GPIO_ADI
698 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
700 static void bfin_gpio_ack_irq(struct irq_data *d)
702 /* AFAIK ack_irq in case mask_ack is provided
703 * get's only called for edge sense irqs
705 set_gpio_data(irq_to_gpio(d->irq), 0);
708 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
710 unsigned int irq = d->irq;
711 u32 gpionr = irq_to_gpio(irq);
713 if (!irqd_is_level_type(d))
714 set_gpio_data(gpionr, 0);
716 set_gpio_maska(gpionr, 0);
719 static void bfin_gpio_mask_irq(struct irq_data *d)
721 set_gpio_maska(irq_to_gpio(d->irq), 0);
724 static void bfin_gpio_unmask_irq(struct irq_data *d)
726 set_gpio_maska(irq_to_gpio(d->irq), 1);
729 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
731 u32 gpionr = irq_to_gpio(d->irq);
733 if (__test_and_set_bit(gpionr, gpio_enabled))
734 bfin_gpio_irq_prepare(gpionr);
736 bfin_gpio_unmask_irq(d);
741 static void bfin_gpio_irq_shutdown(struct irq_data *d)
743 u32 gpionr = irq_to_gpio(d->irq);
745 bfin_gpio_mask_irq(d);
746 __clear_bit(gpionr, gpio_enabled);
747 bfin_gpio_irq_free(gpionr);
750 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
752 unsigned int irq = d->irq;
755 u32 gpionr = irq_to_gpio(irq);
757 if (type == IRQ_TYPE_PROBE) {
758 /* only probe unenabled GPIO interrupt lines */
759 if (test_bit(gpionr, gpio_enabled))
761 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
764 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
765 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
767 snprintf(buf, 16, "gpio-irq%d", irq);
768 ret = bfin_gpio_irq_request(gpionr, buf);
772 if (__test_and_set_bit(gpionr, gpio_enabled))
773 bfin_gpio_irq_prepare(gpionr);
776 __clear_bit(gpionr, gpio_enabled);
780 set_gpio_inen(gpionr, 0);
781 set_gpio_dir(gpionr, 0);
783 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
784 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
785 set_gpio_both(gpionr, 1);
787 set_gpio_both(gpionr, 0);
789 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
790 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
792 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
794 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
795 set_gpio_edge(gpionr, 1);
796 set_gpio_inen(gpionr, 1);
797 set_gpio_data(gpionr, 0);
800 set_gpio_edge(gpionr, 0);
801 set_gpio_inen(gpionr, 1);
804 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
805 bfin_set_irq_handler(d, handle_edge_irq);
807 bfin_set_irq_handler(d, handle_level_irq);
812 static void bfin_demux_gpio_block(unsigned int irq)
814 unsigned int gpio, mask;
816 gpio = irq_to_gpio(irq);
817 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
821 bfin_handle_irq(irq);
827 void bfin_demux_gpio_irq(struct irq_desc *desc)
829 unsigned int inta_irq = irq_desc_get_irq(desc);
833 #if defined(BF537_FAMILY)
834 case IRQ_PF_INTA_PG_INTA:
835 bfin_demux_gpio_block(IRQ_PF0);
838 case IRQ_PH_INTA_MAC_RX:
841 #elif defined(BF533_FAMILY)
845 #elif defined(BF538_FAMILY)
849 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
859 #elif defined(CONFIG_BF561)
875 bfin_demux_gpio_block(irq);
880 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
882 return bfin_gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
887 # define bfin_gpio_set_wake NULL
891 static struct irq_chip bfin_gpio_irqchip = {
893 .irq_ack = bfin_gpio_ack_irq,
894 .irq_mask = bfin_gpio_mask_irq,
895 .irq_mask_ack = bfin_gpio_mask_ack_irq,
896 .irq_unmask = bfin_gpio_unmask_irq,
897 .irq_disable = bfin_gpio_mask_irq,
898 .irq_enable = bfin_gpio_unmask_irq,
899 .irq_set_type = bfin_gpio_irq_type,
900 .irq_startup = bfin_gpio_irq_startup,
901 .irq_shutdown = bfin_gpio_irq_shutdown,
902 .irq_set_wake = bfin_gpio_set_wake,
910 static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
912 static int sec_suspend(void)
916 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
917 save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0));
921 static void sec_resume(void)
925 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
927 bfin_write_SEC_GCTL(SEC_GCTL_EN);
928 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
930 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
931 bfin_write_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
934 static struct syscore_ops sec_pm_syscore_ops = {
935 .suspend = sec_suspend,
936 .resume = sec_resume,
942 void init_exception_vectors(void)
944 /* cannot program in software:
945 * evt0 - emulation (jtag)
948 bfin_write_EVT2(evt_nmi);
949 bfin_write_EVT3(trap);
950 bfin_write_EVT5(evt_ivhw);
951 bfin_write_EVT6(evt_timer);
952 bfin_write_EVT7(evt_evt7);
953 bfin_write_EVT8(evt_evt8);
954 bfin_write_EVT9(evt_evt9);
955 bfin_write_EVT10(evt_evt10);
956 bfin_write_EVT11(evt_evt11);
957 bfin_write_EVT12(evt_evt12);
958 bfin_write_EVT13(evt_evt13);
959 bfin_write_EVT14(evt_evt14);
960 bfin_write_EVT15(evt_system_call);
966 * This function should be called during kernel startup to initialize
967 * the BFin IRQ handling routines.
970 int __init init_arch_irq(void)
973 unsigned long ilat = 0;
975 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
977 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
978 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
980 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
982 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
983 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
984 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
987 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
992 for (irq = 0; irq <= SYS_IRQS; irq++) {
993 if (irq <= IRQ_CORETMR)
994 irq_set_chip(irq, &bfin_core_irqchip);
996 irq_set_chip(irq, &bfin_internal_irqchip);
1000 #if defined(BF537_FAMILY)
1001 case IRQ_PH_INTA_MAC_RX:
1002 case IRQ_PF_INTA_PG_INTA:
1003 #elif defined(BF533_FAMILY)
1005 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1006 case IRQ_PORTF_INTA:
1007 case IRQ_PORTG_INTA:
1008 case IRQ_PORTH_INTA:
1009 #elif defined(CONFIG_BF561)
1010 case IRQ_PROG0_INTA:
1011 case IRQ_PROG1_INTA:
1012 case IRQ_PROG2_INTA:
1013 #elif defined(BF538_FAMILY)
1014 case IRQ_PORTF_INTA:
1016 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1019 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1021 irq_set_chained_handler(irq,
1022 bfin_demux_mac_status_irq);
1025 #if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1028 irq_set_handler(irq, handle_percpu_irq);
1032 #ifdef CONFIG_TICKSOURCE_CORETMR
1035 irq_set_handler(irq, handle_percpu_irq);
1037 irq_set_handler(irq, handle_simple_irq);
1042 #ifdef CONFIG_TICKSOURCE_GPTMR0
1044 irq_set_handler(irq, handle_simple_irq);
1050 irq_set_handler(irq, handle_level_irq);
1052 irq_set_handler(irq, handle_simple_irq);
1060 #if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1061 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1062 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
1065 /* if configured as edge, then will be changed to do_edge_IRQ */
1066 #ifdef CONFIG_GPIO_ADI
1067 for (irq = GPIO_IRQ_BASE;
1068 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1069 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1072 bfin_write_IMASK(0);
1074 ilat = bfin_read_ILAT();
1076 bfin_write_ILAT(ilat);
1079 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1080 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1081 * local_irq_enable()
1084 /* Therefore it's better to setup IARs before interrupts enabled */
1087 /* Enable interrupts IVG7-15 */
1088 bfin_irq_flags |= IMASK_IVG15 |
1089 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1090 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1093 /* This implicitly covers ANOMALY_05000171
1094 * Boot-ROM code modifies SICA_IWRx wakeup registers
1097 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1099 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1100 * will screw up the bootrom as it relies on MDMA0/1 waking it
1101 * up from IDLE instructions. See this report for more info:
1102 * http://blackfin.uclinux.org/gf/tracker/4323
1104 if (ANOMALY_05000435)
1105 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1107 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1110 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1113 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1118 #ifdef CONFIG_DO_IRQ_L1
1119 __attribute__((l1_text))
1121 static int vec_to_irq(int vec)
1123 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1124 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1125 unsigned long sic_status[3];
1126 if (likely(vec == EVT_IVTMR_P))
1129 sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1131 if (smp_processor_id()) {
1133 /* This will be optimized out in UP mode. */
1134 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1135 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1138 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1139 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1143 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1147 if (ivg >= ivg_stop)
1150 if (sic_status[0] & ivg->isrflag)
1152 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1158 #else /* SEC_GCTL */
1161 * This function should be called during kernel startup to initialize
1162 * the BFin IRQ handling routines.
1165 int __init init_arch_irq(void)
1168 unsigned long ilat = 0;
1170 bfin_write_SEC_GCTL(SEC_GCTL_RESET);
1172 local_irq_disable();
1174 for (irq = 0; irq <= SYS_IRQS; irq++) {
1175 if (irq <= IRQ_CORETMR) {
1176 irq_set_chip_and_handler(irq, &bfin_core_irqchip,
1178 #if defined(CONFIG_TICKSOURCE_CORETMR) && defined(CONFIG_SMP)
1179 if (irq == IRQ_CORETMR)
1180 irq_set_handler(irq, handle_percpu_irq);
1182 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
1183 irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1186 irq_set_chip(irq, &bfin_sec_irqchip);
1187 irq_set_handler(irq, handle_fasteoi_irq);
1188 __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
1192 bfin_write_IMASK(0);
1194 ilat = bfin_read_ILAT();
1196 bfin_write_ILAT(ilat);
1199 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1201 bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
1203 /* Enable interrupts IVG7-15 */
1204 bfin_irq_flags |= IMASK_IVG15 |
1205 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1206 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1209 bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
1210 bfin_sec_enable_sci(BFIN_SYSIRQ(IRQ_WATCH0));
1211 bfin_sec_enable_ssi(BFIN_SYSIRQ(IRQ_WATCH0));
1212 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1214 bfin_write_SEC_GCTL(SEC_GCTL_EN);
1215 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1216 bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1218 init_software_driven_irq();
1221 register_syscore_ops(&sec_pm_syscore_ops);
1224 bfin_fault_irq.handler = bfin_fault_routine;
1225 #ifdef CONFIG_L1_PARITY_CHECK
1226 setup_irq(IRQ_C0_NMI_L1_PARITY_ERR, &bfin_fault_irq);
1228 setup_irq(IRQ_C0_DBL_FAULT, &bfin_fault_irq);
1229 setup_irq(IRQ_SEC_ERR, &bfin_fault_irq);
1234 #ifdef CONFIG_DO_IRQ_L1
1235 __attribute__((l1_text))
1237 static int vec_to_irq(int vec)
1239 if (likely(vec == EVT_IVTMR_P))
1242 return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
1244 #endif /* SEC_GCTL */
1246 #ifdef CONFIG_DO_IRQ_L1
1247 __attribute__((l1_text))
1249 void do_irq(int vec, struct pt_regs *fp)
1251 int irq = vec_to_irq(vec);
1254 asm_do_IRQ(irq, fp);
1259 int __ipipe_get_irq_priority(unsigned irq)
1263 if (irq <= IRQ_CORETMR)
1267 if (irq >= BFIN_IRQ(0))
1270 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1271 struct ivgx *ivg = ivg_table + ient;
1272 if (ivg->irqno == irq) {
1273 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1274 if (ivg7_13[prio].ifirst <= ivg &&
1275 ivg7_13[prio].istop > ivg)
1285 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1286 #ifdef CONFIG_DO_IRQ_L1
1287 __attribute__((l1_text))
1289 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1291 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1292 struct ipipe_domain *this_domain = __ipipe_current_domain;
1295 irq = vec_to_irq(vec);
1299 if (irq == IRQ_SYSTMR) {
1300 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1301 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1303 /* This is basically what we need from the register frame. */
1304 __this_cpu_write(__ipipe_tick_regs.ipend, regs->ipend);
1305 __this_cpu_write(__ipipe_tick_regs.pc, regs->pc);
1306 if (this_domain != ipipe_root_domain)
1307 __this_cpu_and(__ipipe_tick_regs.ipend, ~0x10);
1309 __this_cpu_or(__ipipe_tick_regs.ipend, 0x10);
1313 * We don't want Linux interrupt handlers to run at the
1314 * current core priority level (i.e. < EVT15), since this
1315 * might delay other interrupts handled by a high priority
1316 * domain. Here is what we do instead:
1318 * - we raise the SYNCDEFER bit to prevent
1319 * __ipipe_handle_irq() to sync the pipeline for the root
1320 * stage for the incoming interrupt. Upon return, that IRQ is
1321 * pending in the interrupt log.
1323 * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1324 * that _schedule_and_signal_from_int will eventually sync the
1325 * pipeline from EVT15.
1327 if (this_domain == ipipe_root_domain) {
1328 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1332 ipipe_trace_irq_entry(irq);
1333 __ipipe_handle_irq(irq, regs);
1334 ipipe_trace_irq_exit(irq);
1336 if (user_mode(regs) &&
1337 !ipipe_test_foreign_stack() &&
1338 (current->ipipe_flags & PF_EVTRET) != 0) {
1340 * Testing for user_regs() does NOT fully eliminate
1341 * foreign stack contexts, because of the forged
1342 * interrupt returns we do through
1343 * __ipipe_call_irqtail. In that case, we might have
1344 * preempted a foreign stack context in a high
1345 * priority domain, with a single interrupt level now
1346 * pending after the irqtail unwinding is done. In
1347 * which case user_mode() is now true, and the event
1348 * gets dispatched spuriously.
1350 current->ipipe_flags &= ~PF_EVTRET;
1351 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1354 if (this_domain == ipipe_root_domain) {
1355 set_thread_flag(TIF_IRQ_SYNC);
1357 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1358 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1365 #endif /* CONFIG_IPIPE */