2 * Based on arch/arm/mm/proc.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
23 #include <asm/assembler.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/hwcap.h>
26 #include <asm/pgtable-hwdef.h>
27 #include <asm/pgtable.h>
29 #include "proc-macros.S"
31 #ifdef CONFIG_ARM64_64K_PAGES
32 #define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
34 #define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
38 #define TCR_SMP_FLAGS TCR_SHARED
40 #define TCR_SMP_FLAGS 0
43 /* PTWs cacheable, inner/outer WBWA */
44 #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
46 #define MAIR(attr, mt) ((attr) << ((mt) * 8))
51 * Turn the CPU D-cache off.
55 bic x0, x0, #1 << 2 // clear SCTLR.C
59 ENDPROC(cpu_cache_off)
64 * Perform a soft reset of the system. Put the CPU into the same state
65 * as it would be if it had been reset, and branch to what would be the
66 * reset vector. It must be executed with the flat identity mapping.
68 * - loc - location to jump to for soft reset
74 msr sctlr_el1, x1 // disable the MMU
79 ENTRY(cpu_soft_restart)
80 /* Save address of cpu_reset() and reset address */
84 /* Turn D-cache off */
87 /* Push out all dirty data, and ensure cache is empty */
92 ENDPROC(cpu_soft_restart)
97 * Idle the processor (wait for interrupt).
100 dsb sy // WFI may enter a low-power mode
107 * cpu_do_suspend - save CPU registers context
109 * x0: virtual address of context pointer
111 ENTRY(cpu_do_suspend)
114 mrs x4, contextidr_el1
124 stp x4, x5, [x0, #16]
125 stp x6, x7, [x0, #32]
126 stp x8, x9, [x0, #48]
127 stp x10, x11, [x0, #64]
130 ENDPROC(cpu_do_suspend)
133 * cpu_do_resume - restore CPU register context
135 * x0: Physical address of context pointer
136 * x1: ttbr0_el1 to be restored
139 * sctlr_el1 value in x0
143 * Invalidate local tlb entries before turning on MMU
147 ldp x4, x5, [x0, #16]
148 ldp x6, x7, [x0, #32]
149 ldp x8, x9, [x0, #48]
150 ldp x10, x11, [x0, #64]
154 msr contextidr_el1, x4
159 tcr_set_idmap_t0sz x8, x7
164 * Restore oslsr_el1 by writing oslar_el1
166 ubfx x11, x11, #1, #1
169 dsb nsh // Make sure local tlb invalidation completed
172 ENDPROC(cpu_do_resume)
176 * cpu_do_switch_mm(pgd_phys, tsk)
178 * Set the translation table base pointer to be pgd_phys.
180 * - pgd_phys - physical address of new TTB
182 ENTRY(cpu_do_switch_mm)
183 mmid w1, x1 // get mm->context.id
184 bfi x0, x1, #48, #16 // set the ASID
185 msr ttbr0_el1, x0 // set TTBR0
188 ENDPROC(cpu_do_switch_mm)
190 .section ".text.init", #alloc, #execinstr
195 * Initialise the processor for turning the MMU on. Return in x0 the
196 * value of the SCTLR_EL1 register.
199 ic iallu // I+BTB cache invalidate
200 tlbi vmalle1is // invalidate I + D TLBs
204 msr cpacr_el1, x0 // Enable FP/ASIMD
205 msr mdscr_el1, xzr // Reset mdscr_el1
207 * Memory region attributes for LPAE:
211 * DEVICE_nGnRnE 000 00000000
212 * DEVICE_nGnRE 001 00000100
213 * DEVICE_GRE 010 00001100
214 * NORMAL_NC 011 01000100
215 * NORMAL 100 11111111
217 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
218 MAIR(0x04, MT_DEVICE_nGnRE) | \
219 MAIR(0x0c, MT_DEVICE_GRE) | \
220 MAIR(0x44, MT_NORMAL_NC) | \
221 MAIR(0xff, MT_NORMAL)
229 bic x0, x0, x5 // clear bits
230 orr x0, x0, x6 // set bits
232 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
233 * both user and kernel.
235 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
236 TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0
237 tcr_set_idmap_t0sz x10, x9
240 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
243 mrs x9, ID_AA64MMFR0_EL1
246 ret // return to head.S
250 * We set the desired value explicitly, including those of the
251 * reserved bits. The values of bits EE & E0E were set early in
252 * el2_setup, which are left untouched below.
255 * U E WT T UD US IHBS
256 * CE0 XWHW CZ ME TEEA S
257 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
258 * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved
259 * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings
263 .word 0xfcffffff // clear
264 .word 0x34d5d91d // set