2 * Copyright (C) 2013 Huawei Ltd.
3 * Author: Jiang Liu <liuj97@gmail.com>
5 * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/bitops.h>
20 #include <linux/bug.h>
21 #include <linux/compiler.h>
22 #include <linux/kernel.h>
24 #include <linux/smp.h>
25 #include <linux/spinlock.h>
26 #include <linux/stop_machine.h>
27 #include <linux/types.h>
28 #include <linux/uaccess.h>
30 #include <asm/cacheflush.h>
31 #include <asm/debug-monitors.h>
32 #include <asm/fixmap.h>
35 #define AARCH64_INSN_SF_BIT BIT(31)
36 #define AARCH64_INSN_N_BIT BIT(22)
38 static int aarch64_insn_encoding_class[] = {
39 AARCH64_INSN_CLS_UNKNOWN,
40 AARCH64_INSN_CLS_UNKNOWN,
41 AARCH64_INSN_CLS_UNKNOWN,
42 AARCH64_INSN_CLS_UNKNOWN,
43 AARCH64_INSN_CLS_LDST,
44 AARCH64_INSN_CLS_DP_REG,
45 AARCH64_INSN_CLS_LDST,
46 AARCH64_INSN_CLS_DP_FPSIMD,
47 AARCH64_INSN_CLS_DP_IMM,
48 AARCH64_INSN_CLS_DP_IMM,
49 AARCH64_INSN_CLS_BR_SYS,
50 AARCH64_INSN_CLS_BR_SYS,
51 AARCH64_INSN_CLS_LDST,
52 AARCH64_INSN_CLS_DP_REG,
53 AARCH64_INSN_CLS_LDST,
54 AARCH64_INSN_CLS_DP_FPSIMD,
57 enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
59 return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
62 /* NOP is an alias of HINT */
63 bool __kprobes aarch64_insn_is_nop(u32 insn)
65 if (!aarch64_insn_is_hint(insn))
68 switch (insn & 0xFE0) {
69 case AARCH64_INSN_HINT_YIELD:
70 case AARCH64_INSN_HINT_WFE:
71 case AARCH64_INSN_HINT_WFI:
72 case AARCH64_INSN_HINT_SEV:
73 case AARCH64_INSN_HINT_SEVL:
80 static DEFINE_RAW_SPINLOCK(patch_lock);
82 static void __kprobes *patch_map(void *addr, int fixmap)
84 unsigned long uintaddr = (uintptr_t) addr;
85 bool module = !core_kernel_text(uintaddr);
88 if (module && IS_ENABLED(CONFIG_DEBUG_SET_MODULE_RONX))
89 page = vmalloc_to_page(addr);
90 else if (!module && IS_ENABLED(CONFIG_DEBUG_RODATA))
91 page = virt_to_page(addr);
96 set_fixmap(fixmap, page_to_phys(page));
98 return (void *) (__fix_to_virt(fixmap) + (uintaddr & ~PAGE_MASK));
101 static void __kprobes patch_unmap(int fixmap)
103 clear_fixmap(fixmap);
106 * In ARMv8-A, A64 instructions have a fixed length of 32 bits and are always
109 int __kprobes aarch64_insn_read(void *addr, u32 *insnp)
114 ret = probe_kernel_read(&val, addr, AARCH64_INSN_SIZE);
116 *insnp = le32_to_cpu(val);
121 static int __kprobes __aarch64_insn_write(void *addr, u32 insn)
124 unsigned long flags = 0;
127 raw_spin_lock_irqsave(&patch_lock, flags);
128 waddr = patch_map(addr, FIX_TEXT_POKE0);
130 ret = probe_kernel_write(waddr, &insn, AARCH64_INSN_SIZE);
132 patch_unmap(FIX_TEXT_POKE0);
133 raw_spin_unlock_irqrestore(&patch_lock, flags);
138 int __kprobes aarch64_insn_write(void *addr, u32 insn)
140 insn = cpu_to_le32(insn);
141 return __aarch64_insn_write(addr, insn);
144 static bool __kprobes __aarch64_insn_hotpatch_safe(u32 insn)
146 if (aarch64_get_insn_class(insn) != AARCH64_INSN_CLS_BR_SYS)
149 return aarch64_insn_is_b(insn) ||
150 aarch64_insn_is_bl(insn) ||
151 aarch64_insn_is_svc(insn) ||
152 aarch64_insn_is_hvc(insn) ||
153 aarch64_insn_is_smc(insn) ||
154 aarch64_insn_is_brk(insn) ||
155 aarch64_insn_is_nop(insn);
159 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
160 * Section B2.6.5 "Concurrent modification and execution of instructions":
161 * Concurrent modification and execution of instructions can lead to the
162 * resulting instruction performing any behavior that can be achieved by
163 * executing any sequence of instructions that can be executed from the
164 * same Exception level, except where the instruction before modification
165 * and the instruction after modification is a B, BL, NOP, BKPT, SVC, HVC,
166 * or SMC instruction.
168 bool __kprobes aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn)
170 return __aarch64_insn_hotpatch_safe(old_insn) &&
171 __aarch64_insn_hotpatch_safe(new_insn);
174 int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn)
179 /* A64 instructions must be word aligned */
180 if ((uintptr_t)tp & 0x3)
183 ret = aarch64_insn_write(tp, insn);
185 flush_icache_range((uintptr_t)tp,
186 (uintptr_t)tp + AARCH64_INSN_SIZE);
191 struct aarch64_insn_patch {
198 static int __kprobes aarch64_insn_patch_text_cb(void *arg)
201 struct aarch64_insn_patch *pp = arg;
203 /* The first CPU becomes master */
204 if (atomic_inc_return(&pp->cpu_count) == 1) {
205 for (i = 0; ret == 0 && i < pp->insn_cnt; i++)
206 ret = aarch64_insn_patch_text_nosync(pp->text_addrs[i],
209 * aarch64_insn_patch_text_nosync() calls flush_icache_range(),
210 * which ends with "dsb; isb" pair guaranteeing global
213 /* Notify other processors with an additional increment. */
214 atomic_inc(&pp->cpu_count);
216 while (atomic_read(&pp->cpu_count) <= num_online_cpus())
224 int __kprobes aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt)
226 struct aarch64_insn_patch patch = {
230 .cpu_count = ATOMIC_INIT(0),
236 return stop_machine(aarch64_insn_patch_text_cb, &patch,
240 int __kprobes aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt)
245 /* Unsafe to patch multiple instructions without synchronizaiton */
247 ret = aarch64_insn_read(addrs[0], &insn);
251 if (aarch64_insn_hotpatch_safe(insn, insns[0])) {
253 * ARMv8 architecture doesn't guarantee all CPUs see
254 * the new instruction after returning from function
255 * aarch64_insn_patch_text_nosync(). So send IPIs to
256 * all other CPUs to achieve instruction
259 ret = aarch64_insn_patch_text_nosync(addrs[0], insns[0]);
260 kick_all_cpus_sync();
265 return aarch64_insn_patch_text_sync(addrs, insns, cnt);
268 static int __kprobes aarch64_get_imm_shift_mask(enum aarch64_insn_imm_type type,
269 u32 *maskp, int *shiftp)
275 case AARCH64_INSN_IMM_26:
279 case AARCH64_INSN_IMM_19:
283 case AARCH64_INSN_IMM_16:
287 case AARCH64_INSN_IMM_14:
291 case AARCH64_INSN_IMM_12:
295 case AARCH64_INSN_IMM_9:
299 case AARCH64_INSN_IMM_7:
303 case AARCH64_INSN_IMM_6:
304 case AARCH64_INSN_IMM_S:
308 case AARCH64_INSN_IMM_R:
322 #define ADR_IMM_HILOSPLIT 2
323 #define ADR_IMM_SIZE SZ_2M
324 #define ADR_IMM_LOMASK ((1 << ADR_IMM_HILOSPLIT) - 1)
325 #define ADR_IMM_HIMASK ((ADR_IMM_SIZE >> ADR_IMM_HILOSPLIT) - 1)
326 #define ADR_IMM_LOSHIFT 29
327 #define ADR_IMM_HISHIFT 5
329 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn)
331 u32 immlo, immhi, mask;
335 case AARCH64_INSN_IMM_ADR:
337 immlo = (insn >> ADR_IMM_LOSHIFT) & ADR_IMM_LOMASK;
338 immhi = (insn >> ADR_IMM_HISHIFT) & ADR_IMM_HIMASK;
339 insn = (immhi << ADR_IMM_HILOSPLIT) | immlo;
340 mask = ADR_IMM_SIZE - 1;
343 if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
344 pr_err("aarch64_insn_decode_immediate: unknown immediate encoding %d\n",
350 return (insn >> shift) & mask;
353 u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
356 u32 immlo, immhi, mask;
360 case AARCH64_INSN_IMM_ADR:
362 immlo = (imm & ADR_IMM_LOMASK) << ADR_IMM_LOSHIFT;
363 imm >>= ADR_IMM_HILOSPLIT;
364 immhi = (imm & ADR_IMM_HIMASK) << ADR_IMM_HISHIFT;
366 mask = ((ADR_IMM_LOMASK << ADR_IMM_LOSHIFT) |
367 (ADR_IMM_HIMASK << ADR_IMM_HISHIFT));
370 if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
371 pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
377 /* Update the immediate field. */
378 insn &= ~(mask << shift);
379 insn |= (imm & mask) << shift;
384 static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
386 enum aarch64_insn_register reg)
390 if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) {
391 pr_err("%s: unknown register encoding %d\n", __func__, reg);
396 case AARCH64_INSN_REGTYPE_RT:
397 case AARCH64_INSN_REGTYPE_RD:
400 case AARCH64_INSN_REGTYPE_RN:
403 case AARCH64_INSN_REGTYPE_RT2:
404 case AARCH64_INSN_REGTYPE_RA:
407 case AARCH64_INSN_REGTYPE_RM:
411 pr_err("%s: unknown register type encoding %d\n", __func__,
416 insn &= ~(GENMASK(4, 0) << shift);
417 insn |= reg << shift;
422 static u32 aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,
428 case AARCH64_INSN_SIZE_8:
431 case AARCH64_INSN_SIZE_16:
434 case AARCH64_INSN_SIZE_32:
437 case AARCH64_INSN_SIZE_64:
441 pr_err("%s: unknown size encoding %d\n", __func__, type);
445 insn &= ~GENMASK(31, 30);
451 static inline long branch_imm_common(unsigned long pc, unsigned long addr,
457 * PC: A 64-bit Program Counter holding the address of the current
458 * instruction. A64 instructions must be word-aligned.
460 BUG_ON((pc & 0x3) || (addr & 0x3));
462 offset = ((long)addr - (long)pc);
463 BUG_ON(offset < -range || offset >= range);
468 u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
469 enum aarch64_insn_branch_type type)
475 * B/BL support [-128M, 128M) offset
476 * ARM64 virtual address arrangement guarantees all kernel and module
477 * texts are within +/-128M.
479 offset = branch_imm_common(pc, addr, SZ_128M);
482 case AARCH64_INSN_BRANCH_LINK:
483 insn = aarch64_insn_get_bl_value();
485 case AARCH64_INSN_BRANCH_NOLINK:
486 insn = aarch64_insn_get_b_value();
490 return AARCH64_BREAK_FAULT;
493 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
497 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
498 enum aarch64_insn_register reg,
499 enum aarch64_insn_variant variant,
500 enum aarch64_insn_branch_type type)
505 offset = branch_imm_common(pc, addr, SZ_1M);
508 case AARCH64_INSN_BRANCH_COMP_ZERO:
509 insn = aarch64_insn_get_cbz_value();
511 case AARCH64_INSN_BRANCH_COMP_NONZERO:
512 insn = aarch64_insn_get_cbnz_value();
516 return AARCH64_BREAK_FAULT;
520 case AARCH64_INSN_VARIANT_32BIT:
522 case AARCH64_INSN_VARIANT_64BIT:
523 insn |= AARCH64_INSN_SF_BIT;
527 return AARCH64_BREAK_FAULT;
530 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
532 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
536 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
537 enum aarch64_insn_condition cond)
542 offset = branch_imm_common(pc, addr, SZ_1M);
544 insn = aarch64_insn_get_bcond_value();
546 BUG_ON(cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL);
549 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
553 u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)
555 return aarch64_insn_get_hint_value() | op;
558 u32 __kprobes aarch64_insn_gen_nop(void)
560 return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
563 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
564 enum aarch64_insn_branch_type type)
569 case AARCH64_INSN_BRANCH_NOLINK:
570 insn = aarch64_insn_get_br_value();
572 case AARCH64_INSN_BRANCH_LINK:
573 insn = aarch64_insn_get_blr_value();
575 case AARCH64_INSN_BRANCH_RETURN:
576 insn = aarch64_insn_get_ret_value();
580 return AARCH64_BREAK_FAULT;
583 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg);
586 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
587 enum aarch64_insn_register base,
588 enum aarch64_insn_register offset,
589 enum aarch64_insn_size_type size,
590 enum aarch64_insn_ldst_type type)
595 case AARCH64_INSN_LDST_LOAD_REG_OFFSET:
596 insn = aarch64_insn_get_ldr_reg_value();
598 case AARCH64_INSN_LDST_STORE_REG_OFFSET:
599 insn = aarch64_insn_get_str_reg_value();
603 return AARCH64_BREAK_FAULT;
606 insn = aarch64_insn_encode_ldst_size(size, insn);
608 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
610 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
613 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
617 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
618 enum aarch64_insn_register reg2,
619 enum aarch64_insn_register base,
621 enum aarch64_insn_variant variant,
622 enum aarch64_insn_ldst_type type)
628 case AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX:
629 insn = aarch64_insn_get_ldp_pre_value();
631 case AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX:
632 insn = aarch64_insn_get_stp_pre_value();
634 case AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX:
635 insn = aarch64_insn_get_ldp_post_value();
637 case AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX:
638 insn = aarch64_insn_get_stp_post_value();
642 return AARCH64_BREAK_FAULT;
646 case AARCH64_INSN_VARIANT_32BIT:
647 /* offset must be multiples of 4 in the range [-256, 252] */
648 BUG_ON(offset & 0x3);
649 BUG_ON(offset < -256 || offset > 252);
652 case AARCH64_INSN_VARIANT_64BIT:
653 /* offset must be multiples of 8 in the range [-512, 504] */
654 BUG_ON(offset & 0x7);
655 BUG_ON(offset < -512 || offset > 504);
657 insn |= AARCH64_INSN_SF_BIT;
661 return AARCH64_BREAK_FAULT;
664 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
667 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
670 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
673 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_7, insn,
677 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
678 enum aarch64_insn_register src,
679 int imm, enum aarch64_insn_variant variant,
680 enum aarch64_insn_adsb_type type)
685 case AARCH64_INSN_ADSB_ADD:
686 insn = aarch64_insn_get_add_imm_value();
688 case AARCH64_INSN_ADSB_SUB:
689 insn = aarch64_insn_get_sub_imm_value();
691 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
692 insn = aarch64_insn_get_adds_imm_value();
694 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
695 insn = aarch64_insn_get_subs_imm_value();
699 return AARCH64_BREAK_FAULT;
703 case AARCH64_INSN_VARIANT_32BIT:
705 case AARCH64_INSN_VARIANT_64BIT:
706 insn |= AARCH64_INSN_SF_BIT;
710 return AARCH64_BREAK_FAULT;
713 BUG_ON(imm & ~(SZ_4K - 1));
715 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
717 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
719 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
722 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
723 enum aarch64_insn_register src,
725 enum aarch64_insn_variant variant,
726 enum aarch64_insn_bitfield_type type)
732 case AARCH64_INSN_BITFIELD_MOVE:
733 insn = aarch64_insn_get_bfm_value();
735 case AARCH64_INSN_BITFIELD_MOVE_UNSIGNED:
736 insn = aarch64_insn_get_ubfm_value();
738 case AARCH64_INSN_BITFIELD_MOVE_SIGNED:
739 insn = aarch64_insn_get_sbfm_value();
743 return AARCH64_BREAK_FAULT;
747 case AARCH64_INSN_VARIANT_32BIT:
748 mask = GENMASK(4, 0);
750 case AARCH64_INSN_VARIANT_64BIT:
751 insn |= AARCH64_INSN_SF_BIT | AARCH64_INSN_N_BIT;
752 mask = GENMASK(5, 0);
756 return AARCH64_BREAK_FAULT;
759 BUG_ON(immr & ~mask);
760 BUG_ON(imms & ~mask);
762 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
764 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
766 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
768 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
771 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
773 enum aarch64_insn_variant variant,
774 enum aarch64_insn_movewide_type type)
779 case AARCH64_INSN_MOVEWIDE_ZERO:
780 insn = aarch64_insn_get_movz_value();
782 case AARCH64_INSN_MOVEWIDE_KEEP:
783 insn = aarch64_insn_get_movk_value();
785 case AARCH64_INSN_MOVEWIDE_INVERSE:
786 insn = aarch64_insn_get_movn_value();
790 return AARCH64_BREAK_FAULT;
793 BUG_ON(imm & ~(SZ_64K - 1));
796 case AARCH64_INSN_VARIANT_32BIT:
797 BUG_ON(shift != 0 && shift != 16);
799 case AARCH64_INSN_VARIANT_64BIT:
800 insn |= AARCH64_INSN_SF_BIT;
801 BUG_ON(shift != 0 && shift != 16 && shift != 32 &&
806 return AARCH64_BREAK_FAULT;
809 insn |= (shift >> 4) << 21;
811 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
813 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
816 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
817 enum aarch64_insn_register src,
818 enum aarch64_insn_register reg,
820 enum aarch64_insn_variant variant,
821 enum aarch64_insn_adsb_type type)
826 case AARCH64_INSN_ADSB_ADD:
827 insn = aarch64_insn_get_add_value();
829 case AARCH64_INSN_ADSB_SUB:
830 insn = aarch64_insn_get_sub_value();
832 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
833 insn = aarch64_insn_get_adds_value();
835 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
836 insn = aarch64_insn_get_subs_value();
840 return AARCH64_BREAK_FAULT;
844 case AARCH64_INSN_VARIANT_32BIT:
845 BUG_ON(shift & ~(SZ_32 - 1));
847 case AARCH64_INSN_VARIANT_64BIT:
848 insn |= AARCH64_INSN_SF_BIT;
849 BUG_ON(shift & ~(SZ_64 - 1));
853 return AARCH64_BREAK_FAULT;
857 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
859 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
861 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
863 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
866 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
867 enum aarch64_insn_register src,
868 enum aarch64_insn_variant variant,
869 enum aarch64_insn_data1_type type)
874 case AARCH64_INSN_DATA1_REVERSE_16:
875 insn = aarch64_insn_get_rev16_value();
877 case AARCH64_INSN_DATA1_REVERSE_32:
878 insn = aarch64_insn_get_rev32_value();
880 case AARCH64_INSN_DATA1_REVERSE_64:
881 BUG_ON(variant != AARCH64_INSN_VARIANT_64BIT);
882 insn = aarch64_insn_get_rev64_value();
886 return AARCH64_BREAK_FAULT;
890 case AARCH64_INSN_VARIANT_32BIT:
892 case AARCH64_INSN_VARIANT_64BIT:
893 insn |= AARCH64_INSN_SF_BIT;
897 return AARCH64_BREAK_FAULT;
900 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
902 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
905 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
906 enum aarch64_insn_register src,
907 enum aarch64_insn_register reg,
908 enum aarch64_insn_variant variant,
909 enum aarch64_insn_data2_type type)
914 case AARCH64_INSN_DATA2_UDIV:
915 insn = aarch64_insn_get_udiv_value();
917 case AARCH64_INSN_DATA2_SDIV:
918 insn = aarch64_insn_get_sdiv_value();
920 case AARCH64_INSN_DATA2_LSLV:
921 insn = aarch64_insn_get_lslv_value();
923 case AARCH64_INSN_DATA2_LSRV:
924 insn = aarch64_insn_get_lsrv_value();
926 case AARCH64_INSN_DATA2_ASRV:
927 insn = aarch64_insn_get_asrv_value();
929 case AARCH64_INSN_DATA2_RORV:
930 insn = aarch64_insn_get_rorv_value();
934 return AARCH64_BREAK_FAULT;
938 case AARCH64_INSN_VARIANT_32BIT:
940 case AARCH64_INSN_VARIANT_64BIT:
941 insn |= AARCH64_INSN_SF_BIT;
945 return AARCH64_BREAK_FAULT;
948 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
950 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
952 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
955 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
956 enum aarch64_insn_register src,
957 enum aarch64_insn_register reg1,
958 enum aarch64_insn_register reg2,
959 enum aarch64_insn_variant variant,
960 enum aarch64_insn_data3_type type)
965 case AARCH64_INSN_DATA3_MADD:
966 insn = aarch64_insn_get_madd_value();
968 case AARCH64_INSN_DATA3_MSUB:
969 insn = aarch64_insn_get_msub_value();
973 return AARCH64_BREAK_FAULT;
977 case AARCH64_INSN_VARIANT_32BIT:
979 case AARCH64_INSN_VARIANT_64BIT:
980 insn |= AARCH64_INSN_SF_BIT;
984 return AARCH64_BREAK_FAULT;
987 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
989 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RA, insn, src);
991 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
994 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
998 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
999 enum aarch64_insn_register src,
1000 enum aarch64_insn_register reg,
1002 enum aarch64_insn_variant variant,
1003 enum aarch64_insn_logic_type type)
1008 case AARCH64_INSN_LOGIC_AND:
1009 insn = aarch64_insn_get_and_value();
1011 case AARCH64_INSN_LOGIC_BIC:
1012 insn = aarch64_insn_get_bic_value();
1014 case AARCH64_INSN_LOGIC_ORR:
1015 insn = aarch64_insn_get_orr_value();
1017 case AARCH64_INSN_LOGIC_ORN:
1018 insn = aarch64_insn_get_orn_value();
1020 case AARCH64_INSN_LOGIC_EOR:
1021 insn = aarch64_insn_get_eor_value();
1023 case AARCH64_INSN_LOGIC_EON:
1024 insn = aarch64_insn_get_eon_value();
1026 case AARCH64_INSN_LOGIC_AND_SETFLAGS:
1027 insn = aarch64_insn_get_ands_value();
1029 case AARCH64_INSN_LOGIC_BIC_SETFLAGS:
1030 insn = aarch64_insn_get_bics_value();
1034 return AARCH64_BREAK_FAULT;
1038 case AARCH64_INSN_VARIANT_32BIT:
1039 BUG_ON(shift & ~(SZ_32 - 1));
1041 case AARCH64_INSN_VARIANT_64BIT:
1042 insn |= AARCH64_INSN_SF_BIT;
1043 BUG_ON(shift & ~(SZ_64 - 1));
1047 return AARCH64_BREAK_FAULT;
1051 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1053 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1055 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1057 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
1060 bool aarch32_insn_is_wide(u32 insn)
1062 return insn >= 0xe800;
1066 * Macros/defines for extracting register numbers from instruction.
1068 u32 aarch32_insn_extract_reg_num(u32 insn, int offset)
1070 return (insn & (0xf << offset)) >> offset;
1073 #define OPC2_MASK 0x7
1074 #define OPC2_OFFSET 5
1075 u32 aarch32_insn_mcr_extract_opc2(u32 insn)
1077 return (insn & (OPC2_MASK << OPC2_OFFSET)) >> OPC2_OFFSET;
1080 #define CRM_MASK 0xf
1081 u32 aarch32_insn_mcr_extract_crm(u32 insn)
1083 return insn & CRM_MASK;