2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "CPU features: " fmt
21 #include <linux/bsearch.h>
22 #include <linux/cpumask.h>
23 #include <linux/sort.h>
24 #include <linux/stop_machine.h>
25 #include <linux/types.h>
27 #include <asm/cpufeature.h>
28 #include <asm/cpu_ops.h>
29 #include <asm/processor.h>
30 #include <asm/sysreg.h>
32 unsigned long elf_hwcap __read_mostly;
33 EXPORT_SYMBOL_GPL(elf_hwcap);
36 #define COMPAT_ELF_HWCAP_DEFAULT \
37 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
38 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
39 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
40 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
41 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
43 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
44 unsigned int compat_elf_hwcap2 __read_mostly;
47 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
49 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
56 .safe_val = SAFE_VAL, \
59 /* Define a feature with signed values */
60 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
61 __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
63 /* Define a feature with unsigned value */
64 #define U_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
65 __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
67 #define ARM64_FTR_END \
72 static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
73 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
74 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
75 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
76 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
77 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
78 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
79 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
80 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
81 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
85 static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
86 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
87 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
88 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
89 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
90 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
91 /* Linux doesn't care about the EL3 */
92 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
93 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
94 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
95 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
99 static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
100 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
101 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
102 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
103 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
104 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
105 /* Linux shouldn't care about secure memory */
106 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
107 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
108 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
110 * Differing PARange is fine as long as all peripherals and memory are mapped
111 * within the minimum PARange of all CPUs
113 U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
117 static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
118 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
119 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
120 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
121 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
122 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
123 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
124 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
128 static struct arm64_ftr_bits ftr_ctr[] = {
129 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
130 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
131 U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
132 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
133 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
135 * Linux can handle differing I-cache policies. Userspace JITs will
136 * make use of *minLine
138 U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0), /* L1Ip */
139 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */
140 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
144 static struct arm64_ftr_bits ftr_id_mmfr0[] = {
145 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0), /* InnerShr */
146 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
147 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
148 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */
149 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */
150 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* OuterShr */
151 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
152 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
156 static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
157 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
158 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
159 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
160 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
161 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
162 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
163 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
167 static struct arm64_ftr_bits ftr_mvfr2[] = {
168 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
169 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
170 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
174 static struct arm64_ftr_bits ftr_dczid[] = {
175 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0), /* RAZ */
176 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
177 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
182 static struct arm64_ftr_bits ftr_id_isar5[] = {
183 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
184 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0), /* RAZ */
185 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
186 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
187 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
188 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
189 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
193 static struct arm64_ftr_bits ftr_id_mmfr4[] = {
194 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
195 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
196 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
200 static struct arm64_ftr_bits ftr_id_pfr0[] = {
201 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0), /* RAZ */
202 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
203 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
204 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */
205 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */
210 * Common ftr bits for a 32bit register with all hidden, strict
211 * attributes, with 4bit feature fields and a default safe value of
212 * 0. Covers the following 32bit registers:
213 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
215 static struct arm64_ftr_bits ftr_generic_32bits[] = {
216 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
217 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
218 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
219 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
220 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
221 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
222 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
223 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
227 static struct arm64_ftr_bits ftr_generic[] = {
228 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
232 static struct arm64_ftr_bits ftr_generic32[] = {
233 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
237 static struct arm64_ftr_bits ftr_aa64raz[] = {
238 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
242 #define ARM64_FTR_REG(id, table) \
246 .ftr_bits = &((table)[0]), \
249 static struct arm64_ftr_reg arm64_ftr_regs[] = {
251 /* Op1 = 0, CRn = 0, CRm = 1 */
252 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
253 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
254 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_generic_32bits),
255 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
256 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
257 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
258 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
260 /* Op1 = 0, CRn = 0, CRm = 2 */
261 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
262 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
263 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
264 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
265 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
266 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
267 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
269 /* Op1 = 0, CRn = 0, CRm = 3 */
270 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
271 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
272 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
274 /* Op1 = 0, CRn = 0, CRm = 4 */
275 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
276 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
278 /* Op1 = 0, CRn = 0, CRm = 5 */
279 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
280 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
282 /* Op1 = 0, CRn = 0, CRm = 6 */
283 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
284 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
286 /* Op1 = 0, CRn = 0, CRm = 7 */
287 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
288 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
290 /* Op1 = 3, CRn = 0, CRm = 0 */
291 ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
292 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
294 /* Op1 = 3, CRn = 14, CRm = 0 */
295 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
298 static int search_cmp_ftr_reg(const void *id, const void *regp)
300 return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
304 * get_arm64_ftr_reg - Lookup a feature register entry using its
305 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
306 * ascending order of sys_id , we use binary search to find a matching
309 * returns - Upon success, matching ftr_reg entry for id.
310 * - NULL on failure. It is upto the caller to decide
311 * the impact of a failure.
313 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
315 return bsearch((const void *)(unsigned long)sys_id,
317 ARRAY_SIZE(arm64_ftr_regs),
318 sizeof(arm64_ftr_regs[0]),
322 static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
324 u64 mask = arm64_ftr_mask(ftrp);
327 reg |= (ftr_val << ftrp->shift) & mask;
331 static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
335 switch (ftrp->type) {
337 ret = ftrp->safe_val;
340 ret = new < cur ? new : cur;
342 case FTR_HIGHER_SAFE:
343 ret = new > cur ? new : cur;
352 static int __init sort_cmp_ftr_regs(const void *a, const void *b)
354 return ((const struct arm64_ftr_reg *)a)->sys_id -
355 ((const struct arm64_ftr_reg *)b)->sys_id;
358 static void __init swap_ftr_regs(void *a, void *b, int size)
360 struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
361 *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
362 *(struct arm64_ftr_reg *)b = tmp;
365 static void __init sort_ftr_regs(void)
367 /* Keep the array sorted so that we can do the binary search */
369 ARRAY_SIZE(arm64_ftr_regs),
370 sizeof(arm64_ftr_regs[0]),
376 * Initialise the CPU feature register from Boot CPU values.
377 * Also initiliases the strict_mask for the register.
379 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
382 u64 strict_mask = ~0x0ULL;
383 struct arm64_ftr_bits *ftrp;
384 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
388 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
389 s64 ftr_new = arm64_ftr_value(ftrp, new);
391 val = arm64_ftr_set_value(ftrp, val, ftr_new);
393 strict_mask &= ~arm64_ftr_mask(ftrp);
396 reg->strict_mask = strict_mask;
399 void __init init_cpu_features(struct cpuinfo_arm64 *info)
401 /* Before we start using the tables, make sure it is sorted */
404 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
405 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
406 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
407 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
408 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
409 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
410 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
411 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
412 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
413 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
414 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
415 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
416 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
417 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
418 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
419 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
420 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
421 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
422 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
423 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
424 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
425 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
426 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
427 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
428 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
429 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
430 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
433 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
435 struct arm64_ftr_bits *ftrp;
437 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
438 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
439 s64 ftr_new = arm64_ftr_value(ftrp, new);
441 if (ftr_cur == ftr_new)
443 /* Find a safe value */
444 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
445 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
450 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
452 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
455 update_cpu_ftr_reg(regp, val);
456 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
458 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
459 regp->name, boot, cpu, val);
464 * Update system wide CPU feature registers with the values from a
465 * non-boot CPU. Also performs SANITY checks to make sure that there
466 * aren't any insane variations from that of the boot CPU.
468 void update_cpu_features(int cpu,
469 struct cpuinfo_arm64 *info,
470 struct cpuinfo_arm64 *boot)
475 * The kernel can handle differing I-cache policies, but otherwise
476 * caches should look identical. Userspace JITs will make use of
479 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
480 info->reg_ctr, boot->reg_ctr);
483 * Userspace may perform DC ZVA instructions. Mismatched block sizes
484 * could result in too much or too little memory being zeroed if a
485 * process is preempted and migrated between CPUs.
487 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
488 info->reg_dczid, boot->reg_dczid);
490 /* If different, timekeeping will be broken (especially with KVM) */
491 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
492 info->reg_cntfrq, boot->reg_cntfrq);
495 * The kernel uses self-hosted debug features and expects CPUs to
496 * support identical debug features. We presently need CTX_CMPs, WRPs,
497 * and BRPs to be identical.
498 * ID_AA64DFR1 is currently RES0.
500 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
501 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
502 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
503 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
505 * Even in big.LITTLE, processors should be identical instruction-set
508 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
509 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
510 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
511 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
514 * Differing PARange support is fine as long as all peripherals and
515 * memory are mapped within the minimum PARange of all CPUs.
516 * Linux should not care about secure memory.
518 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
519 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
520 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
521 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
524 * EL3 is not our concern.
525 * ID_AA64PFR1 is currently RES0.
527 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
528 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
529 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
530 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
533 * If we have AArch32, we care about 32-bit features for compat. These
534 * registers should be RES0 otherwise.
536 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
537 info->reg_id_dfr0, boot->reg_id_dfr0);
538 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
539 info->reg_id_isar0, boot->reg_id_isar0);
540 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
541 info->reg_id_isar1, boot->reg_id_isar1);
542 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
543 info->reg_id_isar2, boot->reg_id_isar2);
544 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
545 info->reg_id_isar3, boot->reg_id_isar3);
546 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
547 info->reg_id_isar4, boot->reg_id_isar4);
548 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
549 info->reg_id_isar5, boot->reg_id_isar5);
552 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
553 * ACTLR formats could differ across CPUs and therefore would have to
554 * be trapped for virtualization anyway.
556 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
557 info->reg_id_mmfr0, boot->reg_id_mmfr0);
558 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
559 info->reg_id_mmfr1, boot->reg_id_mmfr1);
560 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
561 info->reg_id_mmfr2, boot->reg_id_mmfr2);
562 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
563 info->reg_id_mmfr3, boot->reg_id_mmfr3);
564 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
565 info->reg_id_pfr0, boot->reg_id_pfr0);
566 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
567 info->reg_id_pfr1, boot->reg_id_pfr1);
568 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
569 info->reg_mvfr0, boot->reg_mvfr0);
570 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
571 info->reg_mvfr1, boot->reg_mvfr1);
572 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
573 info->reg_mvfr2, boot->reg_mvfr2);
576 * Mismatched CPU features are a recipe for disaster. Don't even
577 * pretend to support them.
579 WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
580 "Unsupported CPU feature variation.\n");
583 u64 read_system_reg(u32 id)
585 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
587 /* We shouldn't get a request for an unsupported register */
589 return regp->sys_val;
592 #include <linux/irqchip/arm-gic-v3.h>
595 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
597 int val = cpuid_feature_extract_field(reg, entry->field_pos);
599 return val >= entry->min_field_value;
603 has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
607 val = read_system_reg(entry->sys_reg);
608 return feature_matches(val, entry);
611 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
615 if (!has_cpuid_feature(entry))
618 has_sre = gic_enable_sre();
620 pr_warn_once("%s present but disabled by higher exception level\n",
626 static const struct arm64_cpu_capabilities arm64_features[] = {
628 .desc = "GIC system register CPU interface",
629 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
630 .matches = has_useable_gicv3_cpuif,
631 .sys_reg = SYS_ID_AA64PFR0_EL1,
632 .field_pos = ID_AA64PFR0_GIC_SHIFT,
633 .min_field_value = 1,
635 #ifdef CONFIG_ARM64_PAN
637 .desc = "Privileged Access Never",
638 .capability = ARM64_HAS_PAN,
639 .matches = has_cpuid_feature,
640 .sys_reg = SYS_ID_AA64MMFR1_EL1,
641 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
642 .min_field_value = 1,
643 .enable = cpu_enable_pan,
645 #endif /* CONFIG_ARM64_PAN */
646 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
648 .desc = "LSE atomic instructions",
649 .capability = ARM64_HAS_LSE_ATOMICS,
650 .matches = has_cpuid_feature,
651 .sys_reg = SYS_ID_AA64ISAR0_EL1,
652 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
653 .min_field_value = 2,
655 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
659 #define HWCAP_CAP(reg, field, min_value, type, cap) \
662 .matches = has_cpuid_feature, \
664 .field_pos = field, \
665 .min_field_value = min_value, \
666 .hwcap_type = type, \
670 static const struct arm64_cpu_capabilities arm64_hwcaps[] = {
671 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 2, CAP_HWCAP, HWCAP_PMULL),
672 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 1, CAP_HWCAP, HWCAP_AES),
673 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, 1, CAP_HWCAP, HWCAP_SHA1),
674 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 1, CAP_HWCAP, HWCAP_SHA2),
675 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 1, CAP_HWCAP, HWCAP_CRC32),
676 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 2, CAP_HWCAP, HWCAP_ATOMICS),
677 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 0, CAP_HWCAP, HWCAP_FP),
678 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 0, CAP_HWCAP, HWCAP_ASIMD),
680 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
681 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
682 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
683 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
684 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
689 static void cap_set_hwcap(const struct arm64_cpu_capabilities *cap)
691 switch (cap->hwcap_type) {
693 elf_hwcap |= cap->hwcap;
696 case CAP_COMPAT_HWCAP:
697 compat_elf_hwcap |= (u32)cap->hwcap;
699 case CAP_COMPAT_HWCAP2:
700 compat_elf_hwcap2 |= (u32)cap->hwcap;
709 /* Check if we have a particular HWCAP enabled */
710 static bool __maybe_unused cpus_have_hwcap(const struct arm64_cpu_capabilities *cap)
714 switch (cap->hwcap_type) {
716 rc = (elf_hwcap & cap->hwcap) != 0;
719 case CAP_COMPAT_HWCAP:
720 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
722 case CAP_COMPAT_HWCAP2:
723 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
734 static void setup_cpu_hwcaps(void)
737 const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps;
739 for (i = 0; hwcaps[i].desc; i++)
740 if (hwcaps[i].matches(&hwcaps[i]))
741 cap_set_hwcap(&hwcaps[i]);
744 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
749 for (i = 0; caps[i].desc; i++) {
750 if (!caps[i].matches(&caps[i]))
753 if (!cpus_have_cap(caps[i].capability))
754 pr_info("%s %s\n", info, caps[i].desc);
755 cpus_set_cap(caps[i].capability);
760 * Run through the enabled capabilities and enable() it on all active
763 static void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
767 for (i = 0; caps[i].desc; i++)
768 if (caps[i].enable && cpus_have_cap(caps[i].capability))
770 * Use stop_machine() as it schedules the work allowing
771 * us to modify PSTATE, instead of on_each_cpu() which
772 * uses an IPI, giving us a PSTATE that disappears when
775 stop_machine(caps[i].enable, NULL, cpu_online_mask);
778 #ifdef CONFIG_HOTPLUG_CPU
781 * Flag to indicate if we have computed the system wide
782 * capabilities based on the boot time active CPUs. This
783 * will be used to determine if a new booting CPU should
784 * go through the verification process to make sure that it
785 * supports the system capabilities, without using a hotplug
788 static bool sys_caps_initialised;
790 static inline void set_sys_caps_initialised(void)
792 sys_caps_initialised = true;
796 * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
798 static u64 __raw_read_system_reg(u32 sys_id)
801 case SYS_ID_PFR0_EL1: return (u64)read_cpuid(ID_PFR0_EL1);
802 case SYS_ID_PFR1_EL1: return (u64)read_cpuid(ID_PFR1_EL1);
803 case SYS_ID_DFR0_EL1: return (u64)read_cpuid(ID_DFR0_EL1);
804 case SYS_ID_MMFR0_EL1: return (u64)read_cpuid(ID_MMFR0_EL1);
805 case SYS_ID_MMFR1_EL1: return (u64)read_cpuid(ID_MMFR1_EL1);
806 case SYS_ID_MMFR2_EL1: return (u64)read_cpuid(ID_MMFR2_EL1);
807 case SYS_ID_MMFR3_EL1: return (u64)read_cpuid(ID_MMFR3_EL1);
808 case SYS_ID_ISAR0_EL1: return (u64)read_cpuid(ID_ISAR0_EL1);
809 case SYS_ID_ISAR1_EL1: return (u64)read_cpuid(ID_ISAR1_EL1);
810 case SYS_ID_ISAR2_EL1: return (u64)read_cpuid(ID_ISAR2_EL1);
811 case SYS_ID_ISAR3_EL1: return (u64)read_cpuid(ID_ISAR3_EL1);
812 case SYS_ID_ISAR4_EL1: return (u64)read_cpuid(ID_ISAR4_EL1);
813 case SYS_ID_ISAR5_EL1: return (u64)read_cpuid(ID_ISAR4_EL1);
814 case SYS_MVFR0_EL1: return (u64)read_cpuid(MVFR0_EL1);
815 case SYS_MVFR1_EL1: return (u64)read_cpuid(MVFR1_EL1);
816 case SYS_MVFR2_EL1: return (u64)read_cpuid(MVFR2_EL1);
818 case SYS_ID_AA64PFR0_EL1: return (u64)read_cpuid(ID_AA64PFR0_EL1);
819 case SYS_ID_AA64PFR1_EL1: return (u64)read_cpuid(ID_AA64PFR0_EL1);
820 case SYS_ID_AA64DFR0_EL1: return (u64)read_cpuid(ID_AA64DFR0_EL1);
821 case SYS_ID_AA64DFR1_EL1: return (u64)read_cpuid(ID_AA64DFR0_EL1);
822 case SYS_ID_AA64MMFR0_EL1: return (u64)read_cpuid(ID_AA64MMFR0_EL1);
823 case SYS_ID_AA64MMFR1_EL1: return (u64)read_cpuid(ID_AA64MMFR1_EL1);
824 case SYS_ID_AA64ISAR0_EL1: return (u64)read_cpuid(ID_AA64ISAR0_EL1);
825 case SYS_ID_AA64ISAR1_EL1: return (u64)read_cpuid(ID_AA64ISAR1_EL1);
827 case SYS_CNTFRQ_EL0: return (u64)read_cpuid(CNTFRQ_EL0);
828 case SYS_CTR_EL0: return (u64)read_cpuid(CTR_EL0);
829 case SYS_DCZID_EL0: return (u64)read_cpuid(DCZID_EL0);
837 * Park the CPU which doesn't have the capability as advertised
840 static void fail_incapable_cpu(char *cap_type,
841 const struct arm64_cpu_capabilities *cap)
843 int cpu = smp_processor_id();
845 pr_crit("CPU%d: missing %s : %s\n", cpu, cap_type, cap->desc);
846 /* Mark this CPU absent */
847 set_cpu_present(cpu, 0);
849 /* Check if we can park ourselves */
850 if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die)
851 cpu_ops[cpu]->cpu_die(cpu);
859 * Run through the enabled system capabilities and enable() it on this CPU.
860 * The capabilities were decided based on the available CPUs at the boot time.
861 * Any new CPU should match the system wide status of the capability. If the
862 * new CPU doesn't have a capability which the system now has enabled, we
863 * cannot do anything to fix it up and could cause unexpected failures. So
866 void verify_local_cpu_capabilities(void)
869 const struct arm64_cpu_capabilities *caps;
872 * If we haven't computed the system capabilities, there is nothing
875 if (!sys_caps_initialised)
878 caps = arm64_features;
879 for (i = 0; caps[i].desc; i++) {
880 if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg)
883 * If the new CPU misses an advertised feature, we cannot proceed
884 * further, park the cpu.
886 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
887 fail_incapable_cpu("arm64_features", &caps[i]);
889 caps[i].enable(NULL);
892 for (i = 0, caps = arm64_hwcaps; caps[i].desc; i++) {
893 if (!cpus_have_hwcap(&caps[i]))
895 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
896 fail_incapable_cpu("arm64_hwcaps", &caps[i]);
900 #else /* !CONFIG_HOTPLUG_CPU */
902 static inline void set_sys_caps_initialised(void)
906 #endif /* CONFIG_HOTPLUG_CPU */
908 static void setup_feature_capabilities(void)
910 update_cpu_capabilities(arm64_features, "detected feature:");
911 enable_cpu_capabilities(arm64_features);
914 void __init setup_cpu_features(void)
919 /* Set the CPU feature capabilies */
920 setup_feature_capabilities();
923 /* Advertise that we have computed the system capabilities */
924 set_sys_caps_initialised();
927 * Check for sane CTR_EL0.CWG value.
929 cwg = cache_type_cwg();
930 cls = cache_line_size();
932 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
934 if (L1_CACHE_BYTES < cls)
935 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
936 L1_CACHE_BYTES, cls);