2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
19 model = "Qualcomm Technologies, Inc. MSM8916";
20 compatible = "qcom,msm8916";
22 interrupt-parent = <&intc>;
32 device_type = "memory";
33 /* We expect the bootloader to fill in the reg */
43 compatible = "arm,cortex-a53", "arm,armv8";
49 compatible = "arm,cortex-a53", "arm,armv8";
55 compatible = "arm,cortex-a53", "arm,armv8";
61 compatible = "arm,cortex-a53", "arm,armv8";
67 compatible = "arm,armv8-timer";
68 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
69 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
70 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
71 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
77 ranges = <0 0 0 0xffffffff>;
78 compatible = "simple-bus";
81 compatible = "qcom,msm8916-pinctrl";
82 reg = <0x1000000 0x300000>;
83 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
87 #interrupt-cells = <2>;
89 blsp1_uart2_default: blsp1_uart2_default {
91 function = "blsp_uart2";
92 pins = "gpio4", "gpio5";
95 pins = "gpio4", "gpio5";
96 drive-strength = <16>;
101 blsp1_uart2_sleep: blsp1_uart2_sleep {
103 function = "blsp_uart2";
104 pins = "gpio4", "gpio5";
107 pins = "gpio4", "gpio5";
108 drive-strength = <2>;
114 gcc: qcom,gcc@1800000 {
115 compatible = "qcom,gcc-msm8916";
118 reg = <0x1800000 0x80000>;
121 blsp1_uart2: serial@78b0000 {
122 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
123 reg = <0x78b0000 0x200>;
124 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
126 clock-names = "core", "iface";
130 intc: interrupt-controller@b000000 {
131 compatible = "qcom,msm-qgic2";
132 interrupt-controller;
133 #interrupt-cells = <3>;
134 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
138 #address-cells = <1>;
141 compatible = "arm,armv7-timer-mem";
142 reg = <0xb020000 0x1000>;
143 clock-frequency = <19200000>;
147 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
149 reg = <0xb021000 0x1000>,
155 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
156 reg = <0xb023000 0x1000>;
162 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
163 reg = <0xb024000 0x1000>;
169 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
170 reg = <0xb025000 0x1000>;
176 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
177 reg = <0xb026000 0x1000>;
183 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
184 reg = <0xb027000 0x1000>;
190 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
191 reg = <0xb028000 0x1000>;