kernel/arch/arm64/boot/dts/mediatek/mt8173.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Eddie Huang <eddie.huang@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include "mt8173-pinfunc.h"
  17
  18 / {
  19         compatible = "mediatek,mt8173";
  20         interrupt-parent = <&sysirq>;
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu-map {
  29                         cluster0 {
  30                                 core0 {
  31                                         cpu = <&cpu0>;
  32                                 };
  33                                 core1 {
  34                                         cpu = <&cpu1>;
  35                                 };
  36                         };
  37
  38                         cluster1 {
  39                                 core0 {
  40                                         cpu = <&cpu2>;
  41                                 };
  42                                 core1 {
  43                                         cpu = <&cpu3>;
  44                                 };
  45                         };
  46                 };
  47
  48                 cpu0: cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a53";
  51                         reg = <0x000>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a53";
  57                         reg = <0x001>;
  58                         enable-method = "psci";
  59                 };
  60
  61                 cpu2: cpu@100 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a57";
  64                         reg = <0x100>;
  65                         enable-method = "psci";
  66                 };
  67
  68                 cpu3: cpu@101 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a57";
  71                         reg = <0x101>;
  72                         enable-method = "psci";
  73                 };
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci";
  78                 method = "smc";
  79                 cpu_suspend   = <0x84000001>;
  80                 cpu_off       = <0x84000002>;
  81                 cpu_on        = <0x84000003>;
  82         };
  83
  84         uart_clk: dummy26m {
  85                 compatible = "fixed-clock";
  86                 clock-frequency = <26000000>;
  87                 #clock-cells = <0>;
  88         };
  89
  90         timer {
  91                 compatible = "arm,armv8-timer";
  92                 interrupt-parent = <&gic>;
  93                 interrupts = <GIC_PPI 13
  94                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  95                              <GIC_PPI 14
  96                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  97                              <GIC_PPI 11
  98                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  99                              <GIC_PPI 10
 100                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 101         };
 102
 103         soc {
 104                 #address-cells = <2>;
 105                 #size-cells = <2>;
 106                 compatible = "simple-bus";
 107                 ranges;
 108
 109                 syscfg_pctl_a: syscfg_pctl_a@10005000 {
 110                         compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
 111                         reg = <0 0x10005000 0 0x1000>;
 112                 };
 113
 114                 pio: pinctrl@0x10005000 {
 115                         compatible = "mediatek,mt8173-pinctrl";
 116                         reg = <0 0x1000B000 0 0x1000>;
 117                         mediatek,pctl-regmap = <&syscfg_pctl_a>;
 118                         pins-are-numbered;
 119                         gpio-controller;
 120                         #gpio-cells = <2>;
 121                         interrupt-controller;
 122                         #interrupt-cells = <2>;
 123                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 124                                                 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 125                                                 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 126                 };
 127
 128                 sysirq: intpol-controller@10200620 {
 129                         compatible = "mediatek,mt8173-sysirq",
 130                                         "mediatek,mt6577-sysirq";
 131                         interrupt-controller;
 132                         #interrupt-cells = <3>;
 133                         interrupt-parent = <&gic>;
 134                         reg = <0 0x10200620 0 0x20>;
 135                 };
 136
 137                 gic: interrupt-controller@10220000 {
 138                         compatible = "arm,gic-400";
 139                         #interrupt-cells = <3>;
 140                         interrupt-parent = <&gic>;
 141                         interrupt-controller;
 142                         reg = <0 0x10221000 0 0x1000>,
 143                               <0 0x10222000 0 0x2000>,
 144                               <0 0x10224000 0 0x2000>,
 145                               <0 0x10226000 0 0x2000>;
 146                         interrupts = <GIC_PPI 9
 147                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 148                 };
 149
 150                 uart0: serial@11002000 {
 151                         compatible = "mediatek,mt8173-uart",
 152                                         "mediatek,mt6577-uart";
 153                         reg = <0 0x11002000 0 0x400>;
 154                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 155                         clocks = <&uart_clk>;
 156                         status = "disabled";
 157                 };
 158
 159                 uart1: serial@11003000 {
 160                         compatible = "mediatek,mt8173-uart",
 161                                         "mediatek,mt6577-uart";
 162                         reg = <0 0x11003000 0 0x400>;
 163                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 164                         clocks = <&uart_clk>;
 165                         status = "disabled";
 166                 };
 167
 168                 uart2: serial@11004000 {
 169                         compatible = "mediatek,mt8173-uart",
 170                                         "mediatek,mt6577-uart";
 171                         reg = <0 0x11004000 0 0x400>;
 172                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 173                         clocks = <&uart_clk>;
 174                         status = "disabled";
 175                 };
 176
 177                 uart3: serial@11005000 {
 178                         compatible = "mediatek,mt8173-uart",
 179                                         "mediatek,mt6577-uart";
 180                         reg = <0 0x11005000 0 0x400>;
 181                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 182                         clocks = <&uart_clk>;
 183                         status = "disabled";
 184                 };
 185         };
 186
 187 };
 188