3 select ACPI_GENERIC_GSI if ACPI
4 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_ELF_RANDOMIZE
7 select ARCH_HAS_GCOV_PROFILE_ALL
8 select ARCH_HAS_SG_CHAIN
9 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_SUPPORTS_ATOMIC_RMW
12 select ARCH_WANT_OPTIONAL_GPIOLIB
13 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
14 select ARCH_WANT_FRAME_POINTERS
18 select AUDIT_ARCH_COMPAT_GENERIC
19 select ARM_GIC_V2M if PCI_MSI
21 select ARM_GIC_V3_ITS if PCI_MSI
22 select BUILDTIME_EXTABLE_SORT
23 select CLONE_BACKWARDS
25 select CPU_PM if (SUSPEND || CPU_IDLE)
26 select DCACHE_WORD_ACCESS
27 select GENERIC_ALLOCATOR
28 select GENERIC_CLOCKEVENTS
29 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
30 select GENERIC_CPU_AUTOPROBE
31 select GENERIC_EARLY_IOREMAP
32 select GENERIC_IRQ_PROBE
33 select GENERIC_IRQ_SHOW
34 select GENERIC_IRQ_SHOW_LEVEL
35 select GENERIC_PCI_IOMAP
36 select GENERIC_SCHED_CLOCK
37 select GENERIC_SMP_IDLE_THREAD
38 select GENERIC_STRNCPY_FROM_USER
39 select GENERIC_STRNLEN_USER
40 select GENERIC_TIME_VSYSCALL
41 select HANDLE_DOMAIN_IRQ
42 select HARDIRQS_SW_RESEND
43 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
44 select HAVE_ARCH_AUDITSYSCALL
45 select HAVE_ARCH_BITREVERSE
46 select HAVE_ARCH_JUMP_LABEL
48 select HAVE_ARCH_SECCOMP_FILTER
49 select HAVE_ARCH_TRACEHOOK
51 select HAVE_C_RECORDMCOUNT
52 select HAVE_CC_STACKPROTECTOR
53 select HAVE_CMPXCHG_DOUBLE
54 select HAVE_DEBUG_BUGVERBOSE
55 select HAVE_DEBUG_KMEMLEAK
56 select HAVE_DMA_API_DEBUG
58 select HAVE_DMA_CONTIGUOUS
59 select HAVE_DYNAMIC_FTRACE
60 select HAVE_EFFICIENT_UNALIGNED_ACCESS
61 select HAVE_FTRACE_MCOUNT_RECORD
62 select HAVE_FUNCTION_TRACER
63 select HAVE_FUNCTION_GRAPH_TRACER
64 select HAVE_GENERIC_DMA_COHERENT
65 select HAVE_HW_BREAKPOINT if PERF_EVENTS
67 select HAVE_PATA_PLATFORM
68 select HAVE_PERF_EVENTS
70 select HAVE_PERF_USER_STACK_DUMP
71 select HAVE_RCU_TABLE_FREE
72 select HAVE_PREEMPT_LAZY
73 select HAVE_SYSCALL_TRACEPOINTS
75 select IRQ_FORCED_THREADING
76 select MODULES_USE_ELF_RELA
79 select OF_EARLY_FLATTREE
80 select OF_RESERVED_MEM
81 select PERF_USE_VMALLOC
86 select SYSCTL_EXCEPTION_TRACE
87 select HAVE_CONTEXT_TRACKING
89 ARM 64-bit (AArch64) Linux support.
94 config ARCH_PHYS_ADDR_T_64BIT
103 config STACKTRACE_SUPPORT
106 config ILLEGAL_POINTER_VALUE
108 default 0xdead000000000000
110 config LOCKDEP_SUPPORT
113 config TRACE_IRQFLAGS_SUPPORT
116 config RWSEM_XCHGADD_ALGORITHM
119 config GENERIC_HWEIGHT
125 config GENERIC_CALIBRATE_DELAY
131 config HAVE_GENERIC_RCU_GUP
134 config ARCH_DMA_ADDR_T_64BIT
137 config NEED_DMA_MAP_STATE
140 config NEED_SG_DMA_LENGTH
149 config KERNEL_MODE_NEON
152 config FIX_EARLYCON_MEM
155 config PGTABLE_LEVELS
157 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
158 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
159 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
160 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
162 source "init/Kconfig"
164 source "kernel/Kconfig.freezer"
166 menu "Platform selection"
171 This enables support for Samsung Exynos SoC family
174 bool "ARMv8 based Samsung Exynos7"
176 select COMMON_CLK_SAMSUNG
177 select HAVE_S3C2410_WATCHDOG if WATCHDOG
178 select HAVE_S3C_RTC if RTC_CLASS
180 select PINCTRL_EXYNOS
183 This enables support for Samsung Exynos7 SoC family
185 config ARCH_FSL_LS2085A
186 bool "Freescale LS2085A SOC"
188 This enables support for Freescale LS2085A SOC.
191 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
195 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
198 bool "Qualcomm Platforms"
201 This enables support for the ARMv8 based Qualcomm chipsets.
204 bool "AMD Seattle SoC Family"
206 This enables support for AMD Seattle SOC Family
209 bool "NVIDIA Tegra SoC Family"
210 select ARCH_HAS_RESET_CONTROLLER
211 select ARCH_REQUIRE_GPIOLIB
215 select GENERIC_CLOCKEVENTS
218 select RESET_CONTROLLER
220 This enables support for the NVIDIA Tegra SoC family.
222 config ARCH_TEGRA_132_SOC
223 bool "NVIDIA Tegra132 SoC"
224 depends on ARCH_TEGRA
225 select PINCTRL_TEGRA124
226 select USB_ULPI if USB_PHY
227 select USB_ULPI_VIEWPORT if USB_PHY
229 Enable support for NVIDIA Tegra132 SoC, based on the Denver
230 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
231 but contains an NVIDIA Denver CPU complex in place of
232 Tegra124's "4+1" Cortex-A15 CPU complex.
235 bool "Spreadtrum SoC platform"
237 Support for Spreadtrum ARM based SoCs
240 bool "Cavium Inc. Thunder SoC Family"
242 This enables support for Cavium's Thunder Family of SoCs.
245 bool "ARMv8 software model (Versatile Express)"
246 select ARCH_REQUIRE_GPIOLIB
247 select COMMON_CLK_VERSATILE
248 select POWER_RESET_VEXPRESS
249 select VEXPRESS_CONFIG
251 This enables support for the ARMv8 software model (Versatile
255 bool "AppliedMicro X-Gene SOC Family"
257 This enables support for AppliedMicro X-Gene SOC Family
260 bool "Xilinx ZynqMP Family"
262 This enables support for Xilinx ZynqMP Family
271 This feature enables support for PCI bus system. If you say Y
272 here, the kernel will include drivers and infrastructure code
273 to support PCI bus devices.
278 config PCI_DOMAINS_GENERIC
284 source "drivers/pci/Kconfig"
285 source "drivers/pci/pcie/Kconfig"
286 source "drivers/pci/hotplug/Kconfig"
290 menu "Kernel Features"
292 menu "ARM errata workarounds via the alternatives framework"
294 config ARM64_ERRATUM_826319
295 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
298 This option adds an alternative code sequence to work around ARM
299 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
300 AXI master interface and an L2 cache.
302 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
303 and is unable to accept a certain write via this interface, it will
304 not progress on read data presented on the read data channel and the
307 The workaround promotes data cache clean instructions to
308 data cache clean-and-invalidate.
309 Please note that this does not necessarily enable the workaround,
310 as it depends on the alternative framework, which will only patch
311 the kernel if an affected CPU is detected.
315 config ARM64_ERRATUM_827319
316 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
319 This option adds an alternative code sequence to work around ARM
320 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
321 master interface and an L2 cache.
323 Under certain conditions this erratum can cause a clean line eviction
324 to occur at the same time as another transaction to the same address
325 on the AMBA 5 CHI interface, which can cause data corruption if the
326 interconnect reorders the two transactions.
328 The workaround promotes data cache clean instructions to
329 data cache clean-and-invalidate.
330 Please note that this does not necessarily enable the workaround,
331 as it depends on the alternative framework, which will only patch
332 the kernel if an affected CPU is detected.
336 config ARM64_ERRATUM_824069
337 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
340 This option adds an alternative code sequence to work around ARM
341 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
342 to a coherent interconnect.
344 If a Cortex-A53 processor is executing a store or prefetch for
345 write instruction at the same time as a processor in another
346 cluster is executing a cache maintenance operation to the same
347 address, then this erratum might cause a clean cache line to be
348 incorrectly marked as dirty.
350 The workaround promotes data cache clean instructions to
351 data cache clean-and-invalidate.
352 Please note that this option does not necessarily enable the
353 workaround, as it depends on the alternative framework, which will
354 only patch the kernel if an affected CPU is detected.
358 config ARM64_ERRATUM_819472
359 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
362 This option adds an alternative code sequence to work around ARM
363 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
364 present when it is connected to a coherent interconnect.
366 If the processor is executing a load and store exclusive sequence at
367 the same time as a processor in another cluster is executing a cache
368 maintenance operation to the same address, then this erratum might
369 cause data corruption.
371 The workaround promotes data cache clean instructions to
372 data cache clean-and-invalidate.
373 Please note that this does not necessarily enable the workaround,
374 as it depends on the alternative framework, which will only patch
375 the kernel if an affected CPU is detected.
379 config ARM64_ERRATUM_832075
380 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
383 This option adds an alternative code sequence to work around ARM
384 erratum 832075 on Cortex-A57 parts up to r1p2.
386 Affected Cortex-A57 parts might deadlock when exclusive load/store
387 instructions to Write-Back memory are mixed with Device loads.
389 The workaround is to promote device loads to use Load-Acquire
391 Please note that this does not necessarily enable the workaround,
392 as it depends on the alternative framework, which will only patch
393 the kernel if an affected CPU is detected.
397 config ARM64_ERRATUM_845719
398 bool "Cortex-A53: 845719: a load might read incorrect data"
402 This option adds an alternative code sequence to work around ARM
403 erratum 845719 on Cortex-A53 parts up to r0p4.
405 When running a compat (AArch32) userspace on an affected Cortex-A53
406 part, a load at EL0 from a virtual address that matches the bottom 32
407 bits of the virtual address used by a recent load at (AArch64) EL1
408 might return incorrect data.
410 The workaround is to write the contextidr_el1 register on exception
411 return to a 32-bit task.
412 Please note that this does not necessarily enable the workaround,
413 as it depends on the alternative framework, which will only patch
414 the kernel if an affected CPU is detected.
418 config ARM64_ERRATUM_843419
419 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
423 This option builds kernel modules using the large memory model in
424 order to avoid the use of the ADRP instruction, which can cause
425 a subsequent memory access to use an incorrect address on Cortex-A53
428 Note that the kernel itself must be linked with a version of ld
429 which fixes potentially affected ADRP instructions through the
439 default ARM64_4K_PAGES
441 Page size (translation granule) configuration.
443 config ARM64_4K_PAGES
446 This feature enables 4KB pages support.
448 config ARM64_64K_PAGES
451 This feature enables 64KB pages support (4KB by default)
452 allowing only two levels of page tables and faster TLB
453 look-up. AArch32 emulation is not available when this feature
459 prompt "Virtual address space size"
460 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
461 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
463 Allows choosing one of multiple possible virtual address
464 space sizes. The level of translation table is determined by
465 a combination of page size and virtual address space size.
467 config ARM64_VA_BITS_39
469 depends on ARM64_4K_PAGES
471 config ARM64_VA_BITS_42
473 depends on ARM64_64K_PAGES
475 config ARM64_VA_BITS_48
482 default 39 if ARM64_VA_BITS_39
483 default 42 if ARM64_VA_BITS_42
484 default 48 if ARM64_VA_BITS_48
486 config CPU_BIG_ENDIAN
487 bool "Build big-endian kernel"
489 Say Y if you plan on running a kernel in big-endian mode.
492 bool "Symmetric Multi-Processing"
494 This enables support for systems with more than one CPU. If
495 you say N here, the kernel will run on single and
496 multiprocessor machines, but will use only one CPU of a
497 multiprocessor machine. If you say Y here, the kernel will run
498 on many, but not all, single processor machines. On a single
499 processor machine, the kernel will run faster if you say N
502 If you don't know what to do here, say N.
505 bool "Multi-core scheduler support"
508 Multi-core scheduler support improves the CPU scheduler's decision
509 making when dealing with multi-core CPU chips at a cost of slightly
510 increased overhead in some places. If unsure say N here.
513 bool "SMT scheduler support"
516 Improves the CPU scheduler's decision making when dealing with
517 MultiThreading at a cost of slightly increased overhead in some
518 places. If unsure say N here.
521 int "Maximum number of CPUs (2-4096)"
524 # These have to remain sorted largest to smallest
528 bool "Support for hot-pluggable CPUs"
531 Say Y here to experiment with turning CPUs off and on. CPUs
532 can be controlled through /sys/devices/system/cpu.
534 source kernel/Kconfig.preempt
544 config ARCH_HAS_HOLES_MEMORYMODEL
545 def_bool y if SPARSEMEM
547 config ARCH_SPARSEMEM_ENABLE
549 select SPARSEMEM_VMEMMAP_ENABLE
551 config ARCH_SPARSEMEM_DEFAULT
552 def_bool ARCH_SPARSEMEM_ENABLE
554 config ARCH_SELECT_MEMORY_MODEL
555 def_bool ARCH_SPARSEMEM_ENABLE
557 config HAVE_ARCH_PFN_VALID
558 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
560 config HW_PERF_EVENTS
561 bool "Enable hardware performance counter support for perf events"
562 depends on PERF_EVENTS
565 Enable hardware performance counter support for perf events. If
566 disabled, perf events will use software events only.
568 config SYS_SUPPORTS_HUGETLBFS
571 config ARCH_WANT_GENERAL_HUGETLB
574 config ARCH_WANT_HUGE_PMD_SHARE
575 def_bool y if !ARM64_64K_PAGES
577 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
580 config ARCH_HAS_CACHE_LINE_SIZE
586 bool "Enable seccomp to safely compute untrusted bytecode"
588 This kernel feature is useful for number crunching applications
589 that may need to compute untrusted bytecode during their
590 execution. By using pipes or other transports made available to
591 the process as file descriptors supporting the read/write
592 syscalls, it's possible to isolate those applications in
593 their own address space using seccomp. Once seccomp is
594 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
595 and the task is only allowed to execute a few safe syscalls
596 defined by each seccomp mode.
603 bool "Xen guest support on ARM64"
604 depends on ARM64 && OF && !PREEMPT_RT_FULL
607 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
609 config FORCE_MAX_ZONEORDER
611 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
614 menuconfig ARMV8_DEPRECATED
615 bool "Emulate deprecated/obsolete ARMv8 instructions"
618 Legacy software support may require certain instructions
619 that have been deprecated or obsoleted in the architecture.
621 Enable this config to enable selective emulation of these
629 bool "Emulate SWP/SWPB instructions"
631 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
632 they are always undefined. Say Y here to enable software
633 emulation of these instructions for userspace using LDXR/STXR.
635 In some older versions of glibc [<=2.8] SWP is used during futex
636 trylock() operations with the assumption that the code will not
637 be preempted. This invalid assumption may be more likely to fail
638 with SWP emulation enabled, leading to deadlock of the user
641 NOTE: when accessing uncached shared regions, LDXR/STXR rely
642 on an external transaction monitoring block called a global
643 monitor to maintain update atomicity. If your system does not
644 implement a global monitor, this option can cause programs that
645 perform SWP operations to uncached memory to deadlock.
649 config CP15_BARRIER_EMULATION
650 bool "Emulate CP15 Barrier instructions"
652 The CP15 barrier instructions - CP15ISB, CP15DSB, and
653 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
654 strongly recommended to use the ISB, DSB, and DMB
655 instructions instead.
657 Say Y here to enable software emulation of these
658 instructions for AArch32 userspace code. When this option is
659 enabled, CP15 barrier usage is traced which can help
660 identify software that needs updating.
664 config SETEND_EMULATION
665 bool "Emulate SETEND instruction"
667 The SETEND instruction alters the data-endianness of the
668 AArch32 EL0, and is deprecated in ARMv8.
670 Say Y here to enable software emulation of the instruction
671 for AArch32 userspace code.
673 Note: All the cpus on the system must have mixed endian support at EL0
674 for this feature to be enabled. If a new CPU - which doesn't support mixed
675 endian - is hotplugged in after this feature has been enabled, there could
676 be unexpected results in the applications.
686 string "Default kernel command string"
689 Provide a set of default command-line options at build time by
690 entering them here. As a minimum, you should specify the the
691 root device (e.g. root=/dev/nfs).
694 bool "Always use the default kernel command string"
696 Always use the default kernel command string, even if the boot
697 loader passes other arguments to the kernel.
698 This is useful if you cannot or don't want to change the
699 command-line options your boot loader passes to the kernel.
705 bool "UEFI runtime support"
706 depends on OF && !CPU_BIG_ENDIAN
709 select EFI_PARAMS_FROM_FDT
710 select EFI_RUNTIME_WRAPPERS
715 This option provides support for runtime services provided
716 by UEFI firmware (such as non-volatile variables, realtime
717 clock, and platform reset). A UEFI stub is also provided to
718 allow the kernel to be booted as an EFI application. This
719 is only useful on systems that have UEFI firmware.
722 bool "Enable support for SMBIOS (DMI) tables"
726 This enables SMBIOS/DMI feature for systems.
728 This option is only useful on systems that have UEFI firmware.
729 However, even with this option, the resultant kernel should
730 continue to boot on existing non-UEFI platforms.
734 menu "Userspace binary formats"
736 source "fs/Kconfig.binfmt"
739 bool "Kernel support for 32-bit EL0"
740 depends on !ARM64_64K_PAGES || EXPERT
741 select COMPAT_BINFMT_ELF
743 select OLD_SIGSUSPEND3
744 select COMPAT_OLD_SIGACTION
746 This option enables support for a 32-bit EL0 running under a 64-bit
747 kernel at EL1. AArch32-specific components such as system calls,
748 the user helper functions, VFP support and the ptrace interface are
749 handled appropriately by the kernel.
751 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
752 will only be able to execute AArch32 binaries that were compiled with
753 64k aligned segments.
755 If you want to execute 32-bit userspace applications, say Y.
757 config SYSVIPC_COMPAT
759 depends on COMPAT && SYSVIPC
763 menu "Power management options"
765 source "kernel/power/Kconfig"
767 config ARCH_SUSPEND_POSSIBLE
772 menu "CPU Power Management"
774 source "drivers/cpuidle/Kconfig"
776 source "drivers/cpufreq/Kconfig"
782 source "drivers/Kconfig"
784 source "drivers/firmware/Kconfig"
786 source "drivers/acpi/Kconfig"
790 source "arch/arm64/kvm/Kconfig"
792 source "arch/arm64/Kconfig.debug"
794 source "security/Kconfig"
796 source "crypto/Kconfig"
798 source "arch/arm64/crypto/Kconfig"